1 files changed, 10 insertions, 10 deletions

diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 0d159d64a345..667d53dd7012 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -28,11 +28,11 @@
 #include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
 
-#define WUPCR           0xe6151010
-#define SRESCR          0xe6151018
-#define PSTR            0xe6151040
-#define SBAR            0xe6180020
-#define APARMBAREA      0xe6f10020
+#define WUPCR           IOMEM(0xe6151010)
+#define SRESCR          IOMEM(0xe6151018)
+#define PSTR            IOMEM(0xe6151040)
+#define SBAR            IOMEM(0xe6180020)
+#define APARMBAREA      IOMEM(0xe6f10020)
 
 static void __iomem *scu_base_addr(void)
 {
@@ -80,10 +80,10 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
         /* enable cache coherency */
         modify_scu_cpu_psr(0, 3 << (cpu * 8));
 
-        if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
-                __raw_writel(1 << cpu, __io(WUPCR));    /* wake up */
+        if (((__raw_readw(PSTR) >> (4 * cpu)) & 3) == 3)
+                __raw_writel(1 << cpu, WUPCR);  /* wake up */
         else
-                __raw_writel(1 << cpu, __io(SRESCR));   /* reset */
+                __raw_writel(1 << cpu, SRESCR); /* reset */
 
         return 0;
 }
@@ -95,8 +95,8 @@ void __init sh73a0_smp_prepare_cpus(void)
         scu_enable(scu_base_addr());
 
         /* Map the reset vector (in headsmp.S) */
-        __raw_writel(0, __io(APARMBAREA));      /* 4k */
-        __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
+        __raw_writel(0, APARMBAREA);      /* 4k */
+        __raw_writel(__pa(shmobile_secondary_vector), SBAR);
 
         /* enable cache coherency on CPU0 */
         modify_scu_cpu_psr(0, 3 << (cpu * 8));