diff options
Diffstat (limited to 'arch/arm/mach-shmobile/setup-sh7377.c')
| -rw-r--r-- | arch/arm/mach-shmobile/setup-sh7377.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c index 8099b0b8a934..e238d0e9453b 100644 --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ b/arch/arm/mach-shmobile/setup-sh7377.c | |||
| @@ -38,7 +38,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
| 38 | .flags = UPF_BOOT_AUTOCONF, | 38 | .flags = UPF_BOOT_AUTOCONF, |
| 39 | .scscr = SCSCR_RE | SCSCR_TE, | 39 | .scscr = SCSCR_RE | SCSCR_TE, |
| 40 | .scbrr_algo_id = SCBRR_ALGO_4, | 40 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 41 | .type = PORT_SCIF, | 41 | .type = PORT_SCIFA, |
| 42 | .irqs = { evt2irq(0xc00), evt2irq(0xc00), | 42 | .irqs = { evt2irq(0xc00), evt2irq(0xc00), |
| 43 | evt2irq(0xc00), evt2irq(0xc00) }, | 43 | evt2irq(0xc00), evt2irq(0xc00) }, |
| 44 | }; | 44 | }; |
| @@ -57,7 +57,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
| 57 | .flags = UPF_BOOT_AUTOCONF, | 57 | .flags = UPF_BOOT_AUTOCONF, |
| 58 | .scscr = SCSCR_RE | SCSCR_TE, | 58 | .scscr = SCSCR_RE | SCSCR_TE, |
| 59 | .scbrr_algo_id = SCBRR_ALGO_4, | 59 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 60 | .type = PORT_SCIF, | 60 | .type = PORT_SCIFA, |
| 61 | .irqs = { evt2irq(0xc20), evt2irq(0xc20), | 61 | .irqs = { evt2irq(0xc20), evt2irq(0xc20), |
| 62 | evt2irq(0xc20), evt2irq(0xc20) }, | 62 | evt2irq(0xc20), evt2irq(0xc20) }, |
| 63 | }; | 63 | }; |
| @@ -76,7 +76,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
| 76 | .flags = UPF_BOOT_AUTOCONF, | 76 | .flags = UPF_BOOT_AUTOCONF, |
| 77 | .scscr = SCSCR_RE | SCSCR_TE, | 77 | .scscr = SCSCR_RE | SCSCR_TE, |
| 78 | .scbrr_algo_id = SCBRR_ALGO_4, | 78 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 79 | .type = PORT_SCIF, | 79 | .type = PORT_SCIFA, |
| 80 | .irqs = { evt2irq(0xc40), evt2irq(0xc40), | 80 | .irqs = { evt2irq(0xc40), evt2irq(0xc40), |
| 81 | evt2irq(0xc40), evt2irq(0xc40) }, | 81 | evt2irq(0xc40), evt2irq(0xc40) }, |
| 82 | }; | 82 | }; |
| @@ -95,7 +95,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
| 95 | .flags = UPF_BOOT_AUTOCONF, | 95 | .flags = UPF_BOOT_AUTOCONF, |
| 96 | .scscr = SCSCR_RE | SCSCR_TE, | 96 | .scscr = SCSCR_RE | SCSCR_TE, |
| 97 | .scbrr_algo_id = SCBRR_ALGO_4, | 97 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 98 | .type = PORT_SCIF, | 98 | .type = PORT_SCIFA, |
| 99 | .irqs = { evt2irq(0xc60), evt2irq(0xc60), | 99 | .irqs = { evt2irq(0xc60), evt2irq(0xc60), |
| 100 | evt2irq(0xc60), evt2irq(0xc60) }, | 100 | evt2irq(0xc60), evt2irq(0xc60) }, |
| 101 | }; | 101 | }; |
| @@ -114,7 +114,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
| 114 | .flags = UPF_BOOT_AUTOCONF, | 114 | .flags = UPF_BOOT_AUTOCONF, |
| 115 | .scscr = SCSCR_RE | SCSCR_TE, | 115 | .scscr = SCSCR_RE | SCSCR_TE, |
| 116 | .scbrr_algo_id = SCBRR_ALGO_4, | 116 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 117 | .type = PORT_SCIF, | 117 | .type = PORT_SCIFA, |
| 118 | .irqs = { evt2irq(0xd20), evt2irq(0xd20), | 118 | .irqs = { evt2irq(0xd20), evt2irq(0xd20), |
| 119 | evt2irq(0xd20), evt2irq(0xd20) }, | 119 | evt2irq(0xd20), evt2irq(0xd20) }, |
| 120 | }; | 120 | }; |
| @@ -133,7 +133,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
| 133 | .flags = UPF_BOOT_AUTOCONF, | 133 | .flags = UPF_BOOT_AUTOCONF, |
| 134 | .scscr = SCSCR_RE | SCSCR_TE, | 134 | .scscr = SCSCR_RE | SCSCR_TE, |
| 135 | .scbrr_algo_id = SCBRR_ALGO_4, | 135 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 136 | .type = PORT_SCIF, | 136 | .type = PORT_SCIFA, |
| 137 | .irqs = { evt2irq(0xd40), evt2irq(0xd40), | 137 | .irqs = { evt2irq(0xd40), evt2irq(0xd40), |
| 138 | evt2irq(0xd40), evt2irq(0xd40) }, | 138 | evt2irq(0xd40), evt2irq(0xd40) }, |
| 139 | }; | 139 | }; |
| @@ -152,7 +152,7 @@ static struct plat_sci_port scif6_platform_data = { | |||
| 152 | .flags = UPF_BOOT_AUTOCONF, | 152 | .flags = UPF_BOOT_AUTOCONF, |
| 153 | .scscr = SCSCR_RE | SCSCR_TE, | 153 | .scscr = SCSCR_RE | SCSCR_TE, |
| 154 | .scbrr_algo_id = SCBRR_ALGO_4, | 154 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 155 | .type = PORT_SCIF, | 155 | .type = PORT_SCIFA, |
| 156 | .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), | 156 | .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), |
| 157 | intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, | 157 | intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, |
| 158 | }; | 158 | }; |
| @@ -171,7 +171,7 @@ static struct plat_sci_port scif7_platform_data = { | |||
| 171 | .flags = UPF_BOOT_AUTOCONF, | 171 | .flags = UPF_BOOT_AUTOCONF, |
| 172 | .scscr = SCSCR_RE | SCSCR_TE, | 172 | .scscr = SCSCR_RE | SCSCR_TE, |
| 173 | .scbrr_algo_id = SCBRR_ALGO_4, | 173 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 174 | .type = PORT_SCIF, | 174 | .type = PORT_SCIFB, |
| 175 | .irqs = { evt2irq(0xd60), evt2irq(0xd60), | 175 | .irqs = { evt2irq(0xd60), evt2irq(0xd60), |
| 176 | evt2irq(0xd60), evt2irq(0xd60) }, | 176 | evt2irq(0xd60), evt2irq(0xd60) }, |
| 177 | }; | 177 | }; |