diff options
Diffstat (limited to 'arch/arm/mach-shmobile/setup-r8a7778.c')
-rw-r--r-- | arch/arm/mach-shmobile/setup-r8a7778.c | 83 |
1 files changed, 67 insertions, 16 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 01c62bedf9cf..30b4a336308f 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c | |||
@@ -3,6 +3,7 @@ | |||
3 | * | 3 | * |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | 4 | * Copyright (C) 2013 Renesas Solutions Corp. |
5 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 5 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
6 | * Copyright (C) 2013 Cogent Embedded, Inc. | ||
6 | * | 7 | * |
7 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | 9 | * it under the terms of the GNU General Public License as published by |
@@ -23,6 +24,7 @@ | |||
23 | #include <linux/irqchip/arm-gic.h> | 24 | #include <linux/irqchip/arm-gic.h> |
24 | #include <linux/of.h> | 25 | #include <linux/of.h> |
25 | #include <linux/of_platform.h> | 26 | #include <linux/of_platform.h> |
27 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> | ||
26 | #include <linux/platform_device.h> | 28 | #include <linux/platform_device.h> |
27 | #include <linux/irqchip.h> | 29 | #include <linux/irqchip.h> |
28 | #include <linux/serial_sci.h> | 30 | #include <linux/serial_sci.h> |
@@ -78,22 +80,20 @@ static struct sh_timer_config sh_tmu1_platform_data = { | |||
78 | .clocksource_rating = 200, | 80 | .clocksource_rating = 200, |
79 | }; | 81 | }; |
80 | 82 | ||
81 | #define PLATFORM_INFO(n, i) \ | 83 | /* Ether */ |
82 | { \ | 84 | static struct resource ether_resources[] = { |
83 | .parent = &platform_bus, \ | 85 | DEFINE_RES_MEM(0xfde00000, 0x400), |
84 | .name = #n, \ | 86 | DEFINE_RES_IRQ(gic_iid(0x89)), |
85 | .id = i, \ | ||
86 | .res = n ## i ## _resources, \ | ||
87 | .num_res = ARRAY_SIZE(n ## i ##_resources), \ | ||
88 | .data = &n ## i ##_platform_data, \ | ||
89 | .size_data = sizeof(n ## i ## _platform_data), \ | ||
90 | } | ||
91 | |||
92 | struct platform_device_info platform_devinfo[] = { | ||
93 | PLATFORM_INFO(sh_tmu, 0), | ||
94 | PLATFORM_INFO(sh_tmu, 1), | ||
95 | }; | 87 | }; |
96 | 88 | ||
89 | #define r8a7778_register_tmu(idx) \ | ||
90 | platform_device_register_resndata( \ | ||
91 | &platform_bus, "sh_tmu", idx, \ | ||
92 | sh_tmu##idx##_resources, \ | ||
93 | ARRAY_SIZE(sh_tmu##idx##_resources), \ | ||
94 | &sh_tmu##idx##_platform_data, \ | ||
95 | sizeof(sh_tmu##idx##_platform_data)) | ||
96 | |||
97 | void __init r8a7778_add_standard_devices(void) | 97 | void __init r8a7778_add_standard_devices(void) |
98 | { | 98 | { |
99 | int i; | 99 | int i; |
@@ -114,8 +114,59 @@ void __init r8a7778_add_standard_devices(void) | |||
114 | &scif_platform_data[i], | 114 | &scif_platform_data[i], |
115 | sizeof(struct plat_sci_port)); | 115 | sizeof(struct plat_sci_port)); |
116 | 116 | ||
117 | for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++) | 117 | r8a7778_register_tmu(0); |
118 | platform_device_register_full(&platform_devinfo[i]); | 118 | r8a7778_register_tmu(1); |
119 | } | ||
120 | |||
121 | void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) | ||
122 | { | ||
123 | platform_device_register_resndata(&platform_bus, "sh_eth", -1, | ||
124 | ether_resources, | ||
125 | ARRAY_SIZE(ether_resources), | ||
126 | pdata, sizeof(*pdata)); | ||
127 | } | ||
128 | |||
129 | static struct renesas_intc_irqpin_config irqpin_platform_data = { | ||
130 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ | ||
131 | .sense_bitfield_width = 2, | ||
132 | }; | ||
133 | |||
134 | static struct resource irqpin_resources[] = { | ||
135 | DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ | ||
136 | DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ | ||
137 | DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ | ||
138 | DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ | ||
139 | DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ | ||
140 | DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ | ||
141 | DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ | ||
142 | DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ | ||
143 | DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ | ||
144 | }; | ||
145 | |||
146 | void __init r8a7778_init_irq_extpin(int irlm) | ||
147 | { | ||
148 | void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); | ||
149 | unsigned long tmp; | ||
150 | |||
151 | if (!icr0) { | ||
152 | pr_warn("r8a7778: unable to setup external irq pin mode\n"); | ||
153 | return; | ||
154 | } | ||
155 | |||
156 | tmp = ioread32(icr0); | ||
157 | if (irlm) | ||
158 | tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ | ||
159 | else | ||
160 | tmp &= ~(1 << 23); /* IRL mode - not supported */ | ||
161 | tmp |= (1 << 21); /* LVLMODE = 1 */ | ||
162 | iowrite32(tmp, icr0); | ||
163 | iounmap(icr0); | ||
164 | |||
165 | if (irlm) | ||
166 | platform_device_register_resndata( | ||
167 | &platform_bus, "renesas_intc_irqpin", -1, | ||
168 | irqpin_resources, ARRAY_SIZE(irqpin_resources), | ||
169 | &irqpin_platform_data, sizeof(irqpin_platform_data)); | ||
119 | } | 170 | } |
120 | 171 | ||
121 | #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ | 172 | #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ |