1 files changed, 34 insertions, 0 deletions

diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index 5abe02fbd6b9..a2d99b3a9fa8 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -508,6 +508,14 @@ enum {
         SDHICMD2_PU_MARK,
         MMCCMD0_PU_MARK,
         MMCCMD1_PU_MARK,
+        MMCD0_0_PU_MARK,
+        MMCD0_1_PU_MARK,
+        MMCD0_2_PU_MARK,
+        MMCD0_3_PU_MARK,
+        MMCD0_4_PU_MARK,
+        MMCD0_5_PU_MARK,
+        MMCD0_6_PU_MARK,
+        MMCD0_7_PU_MARK,
         FSIBISLD_PU_MARK,
         FSIACK_PU_MARK,
         FSIAILR_PU_MARK,
@@ -1561,6 +1569,24 @@ static pinmux_enum_t pinmux_data[] = {
                 MSEL4CR_MSEL15_0),
         PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
                 MSEL4CR_MSEL15_1),
+
+        PINMUX_DATA(MMCD0_0_PU_MARK,
+                    PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_1_PU_MARK,
+                    PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_2_PU_MARK,
+                    PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_3_PU_MARK,
+                    PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_4_PU_MARK,
+                    PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_5_PU_MARK,
+                    PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_6_PU_MARK,
+                    PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_7_PU_MARK,
+                    PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
+
         PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
         PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
         PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
@@ -2236,6 +2262,14 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(SDHICMD2_PU),
         GPIO_FN(MMCCMD0_PU),
         GPIO_FN(MMCCMD1_PU),
+        GPIO_FN(MMCD0_0_PU),
+        GPIO_FN(MMCD0_1_PU),
+        GPIO_FN(MMCD0_2_PU),
+        GPIO_FN(MMCD0_3_PU),
+        GPIO_FN(MMCD0_4_PU),
+        GPIO_FN(MMCD0_5_PU),
+        GPIO_FN(MMCD0_6_PU),
+        GPIO_FN(MMCD0_7_PU),
         GPIO_FN(FSIACK_PU),
         GPIO_FN(FSIAILR_PU),
         GPIO_FN(FSIAIBT_PU),