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Diffstat (limited to 'arch/arm/mach-shmobile/intc-sh7377.c')
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c294
1 files changed, 294 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index 5c781e2d1897..deac5cfe3524 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = {
346 intca_sense_registers, intca_ack_registers), 346 intca_sense_registers, intca_ack_registers),
347}; 347};
348 348
349/* this macro ignore entry which is also in INTCA */
350#define __IGNORE(a...)
351#define __IGNORE0(a...) 0
352
353enum {
354 UNUSED_INTCS = 0,
355
356 INTCS,
357
358 /* interrupt sources INTCS */
359 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
360 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
361 CEU,
362 BEU_BEU0, BEU_BEU1, BEU_BEU2,
363 __IGNORE(MFI)
364 __IGNORE(BBIF2)
365 VPU,
366 TSIF1,
367 __IGNORE(SGX540)
368 _2DDMAC,
369 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
370 IPMMU_IPMMUR, IPMMU_IPMMUR2,
371 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
372 __IGNORE(KEYSC)
373 __IGNORE(TTI20)
374 __IGNORE(MSIOF)
375 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
376 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
377 CMT0,
378 TSIF0,
379 __IGNORE(CMT2)
380 LMB,
381 __IGNORE(MSUG)
382 __IGNORE(MSU_MSU, MSU_MSU2)
383 __IGNORE(CTI)
384 MVI3,
385 __IGNORE(RWDT0)
386 __IGNORE(RWDT1)
387 ICB,
388 PEP,
389 ASA,
390 __IGNORE(_2DG)
391 HQE,
392 JPU,
393 LCDC0,
394 __IGNORE(LCRC)
395 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
396 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
397 FRC,
398 LCDC1,
399 CSIRX,
400 DSITX_DSITX0, DSITX_DSITX1,
401 __IGNORE(SPU2_SPU0, SPU2_SPU1)
402 __IGNORE(FSI)
403 __IGNORE(FMSI)
404 __IGNORE(SCUV)
405 TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
406 TSIF2,
407 CMT4,
408 __IGNORE(MFIS2)
409 CPORTS2R,
410
411 /* interrupt groups INTCS */
412 RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
413 IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
414};
415
416#define INTCS_INTVECT 0x0F80
417static struct intc_vect intcs_vectors[] __initdata = {
418 INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
419 INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
420 INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
421 INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
422 INTCS_VECT(CEU, 0x0880),
423 INTCS_VECT(BEU_BEU0, 0x08A0),
424 INTCS_VECT(BEU_BEU1, 0x08C0),
425 INTCS_VECT(BEU_BEU2, 0x08E0),
426 __IGNORE(INTCS_VECT(MFI, 0x0900))
427 __IGNORE(INTCS_VECT(BBIF2, 0x0960))
428 INTCS_VECT(VPU, 0x0980),
429 INTCS_VECT(TSIF1, 0x09A0),
430 __IGNORE(INTCS_VECT(SGX540, 0x09E0))
431 INTCS_VECT(_2DDMAC, 0x0A00),
432 INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
433 INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
434 INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
435 INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
436 INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
437 INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
438 __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
439 __IGNORE(INTCS_VECT(TTI20, 0x0C80))
440 __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
441 INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
442 INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
443 INTCS_VECT(TMU_TUNI0, 0x0E80),
444 INTCS_VECT(TMU_TUNI1, 0x0EA0),
445 INTCS_VECT(TMU_TUNI2, 0x0EC0),
446 INTCS_VECT(CMT0, 0x0F00),
447 INTCS_VECT(TSIF0, 0x0F20),
448 __IGNORE(INTCS_VECT(CMT2, 0x0F40))
449 INTCS_VECT(LMB, 0x0F60),
450 __IGNORE(INTCS_VECT(MSUG, 0x0F80))
451 __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
452 __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
453 __IGNORE(INTCS_VECT(CTI, 0x0400))
454 INTCS_VECT(MVI3, 0x0420),
455 __IGNORE(INTCS_VECT(RWDT0, 0x0440))
456 __IGNORE(INTCS_VECT(RWDT1, 0x0460))
457 INTCS_VECT(ICB, 0x0480),
458 INTCS_VECT(PEP, 0x04A0),
459 INTCS_VECT(ASA, 0x04C0),
460 __IGNORE(INTCS_VECT(_2DG, 0x04E0))
461 INTCS_VECT(HQE, 0x0540),
462 INTCS_VECT(JPU, 0x0560),
463 INTCS_VECT(LCDC0, 0x0580),
464 __IGNORE(INTCS_VECT(LCRC, 0x05A0))
465 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
466 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
467 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
468 INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
469 INTCS_VECT(FRC, 0x1700),
470 INTCS_VECT(LCDC1, 0x1780),
471 INTCS_VECT(CSIRX, 0x17A0),
472 INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
473 __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
474 __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
475 __IGNORE(INTCS_VECT(FSI, 0x1840))
476 __IGNORE(INTCS_VECT(FMSI, 0x1860))
477 __IGNORE(INTCS_VECT(SCUV, 0x1880))
478 INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
479 INTCS_VECT(TMU1_TUNI12, 0x1940),
480 INTCS_VECT(TSIF2, 0x1960),
481 INTCS_VECT(CMT4, 0x1980),
482 __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
483 INTCS_VECT(CPORTS2R, 0x1A20),
484
485 INTC_VECT(INTCS, INTCS_INTVECT),
486};
487
488static struct intc_group intcs_groups[] __initdata = {
489 INTC_GROUP(RTDMAC1_1,
490 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
491 RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
492 INTC_GROUP(RTDMAC1_2,
493 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
494 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
495 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
496 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
497 __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
498 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
499 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
500 INTC_GROUP(RTDMAC2_1,
501 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
502 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
503 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
504 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
505 __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
506 INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
507};
508
509static struct intc_mask_reg intcs_mask_registers[] __initdata = {
510 { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
511 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
512 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
513 { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
514 { 0, 0, 0, VPU,
515 __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
516 { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
517 { 0, 0, 0, _2DDMAC,
518 __IGNORE0(_2DG), ASA, PEP, ICB } },
519 { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
520 { 0, 0, MVI3, __IGNORE0(CTI),
521 JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
522 { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
523 { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
524 RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
525 __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
526 { 0, 0, MSIOF, 0,
527 SGX540, 0, TTI20, 0 } })
528 { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
529 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
530 0, 0, 0, 0 } },
531 __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
532 { 0, 0, 0, 0,
533 0, MSU_MSU, MSU_MSU2, MSUG } })
534 { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
535 { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
536 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
537 { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
538 { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
539 0, 0, 0, 0 } },
540 { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
541 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
542 0, TSIF1, LMB, TSIF0 } },
543 { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
544 { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
545 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
546 { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
547 { FRC, 0, 0, 0,
548 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
549 __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
550 {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
551 SCUV, 0, 0, 0 } })
552 { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
553 { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
554 CMT4, 0, 0, 0 } },
555 { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
556 { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
557 0, 0, 0, 0 } },
558 { 0xFFD20104, 0, 16, /* INTAMASK */
559 { 0, 0, 0, 0, 0, 0, 0, 0,
560 0, 0, 0, 0, 0, 0, 0, INTCS } }
561};
562
563static struct intc_prio_reg intcs_prio_registers[] __initdata = {
564 /* IPRAS */
565 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
566 /* IPRBS */
567 { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
568 /* IPRCS */
569 __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
570 /* IPRES */
571 { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
572 /* IPRFS */
573 { 0xFFD20014, 0, 16, 4,
574 { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
575 /* IPRGS */
576 { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
577 /* IPRHS */
578 { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
579 /* IPRIS */
580 { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
581 /* IPRJS */
582 __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
583 /* IPRKS */
584 { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
585 /* IPRLS */
586 { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
587 /* IPRMS */
588 { 0xFFD20030, 0, 16, 4,
589 { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
590 /* IPRAS3 */
591 { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
592 /* IPRBS3 */
593 { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
594 /* IPRIS3 */
595 { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
596 /* IPRJS3 */
597 { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
598 /* IPRKS3 */
599 __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
600 /* IPRLS3 */
601 __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
602 /* IPRMS3 */
603 { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
604 /* IPRNS3 */
605 { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
606 /* IPROS3 */
607 { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
608};
609
610static struct resource intcs_resources[] __initdata = {
611 [0] = {
612 .start = 0xffd20000,
613 .end = 0xffd500ff,
614 .flags = IORESOURCE_MEM,
615 }
616};
617
618static struct intc_desc intcs_desc __initdata = {
619 .name = "sh7377-intcs",
620 .resource = intcs_resources,
621 .num_resources = ARRAY_SIZE(intcs_resources),
622 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
623 intcs_mask_registers, intcs_prio_registers,
624 NULL, NULL),
625};
626
627static void intcs_demux(unsigned int irq, struct irq_desc *desc)
628{
629 void __iomem *reg = (void *)get_irq_data(irq);
630 unsigned int evtcodeas = ioread32(reg);
631
632 generic_handle_irq(intcs_evt2irq(evtcodeas));
633}
634
635#define INTEVTSA 0xFFD20100
349void __init sh7377_init_irq(void) 636void __init sh7377_init_irq(void)
350{ 637{
638 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
639
351 register_intc_controller(&intca_desc); 640 register_intc_controller(&intca_desc);
641 register_intc_controller(&intcs_desc);
642
643 /* demux using INTEVTSA */
644 set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
645 set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
352} 646}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 23:00:04 -0500