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Diffstat (limited to 'arch/arm/mach-shmobile/intc-sh7377.c')
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c36
1 files changed, 19 insertions, 17 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index 125021cfba5c..5c781e2d1897 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -27,6 +27,8 @@
27 27
28enum { 28enum {
29 UNUSED_INTCA = 0, 29 UNUSED_INTCA = 0,
30 ENABLED,
31 DISABLED,
30 32
31 /* interrupt sources INTCA */ 33 /* interrupt sources INTCA */
32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, 34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -49,8 +51,8 @@ enum {
49 MSIOF2, MSIOF1, 51 MSIOF2, MSIOF1,
50 SCIFA4, SCIFA5, SCIFB, 52 SCIFA4, SCIFA5, SCIFB,
51 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 53 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
52 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, 54 SDHI0,
53 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, SDHI1_SDHI1I3, 55 SDHI1,
54 MSU_MSU, MSU_MSU2, 56 MSU_MSU, MSU_MSU2,
55 IRREM, 57 IRREM,
56 MSUG, 58 MSUG,
@@ -84,7 +86,7 @@ enum {
84 86
85 /* interrupt groups INTCA */ 87 /* interrupt groups INTCA */
86 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, 88 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
87 AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, 89 AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
88 ICUSB, ICUDMC 90 ICUSB, ICUDMC
89}; 91};
90 92
@@ -128,10 +130,10 @@ static struct intc_vect intca_vectors[] = {
128 INTC_VECT(SCIFB, 0x0d60), 130 INTC_VECT(SCIFB, 0x0d60),
129 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), 131 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
130 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), 132 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
131 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), 133 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
132 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), 134 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
133 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), 135 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
134 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), INTC_VECT(SDHI1_SDHI1I3, 0x0ee0), 136 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
135 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), 137 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
136 INTC_VECT(IRREM, 0x0f60), 138 INTC_VECT(IRREM, 0x0f60),
137 INTC_VECT(MSUG, 0x0fa0), 139 INTC_VECT(MSUG, 0x0fa0),
@@ -195,10 +197,6 @@ static struct intc_group intca_groups[] __initdata = {
195 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, 197 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
196 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 198 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
197 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 199 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
198 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
199 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
200 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
201 SDHI1_SDHI1I2, SDHI1_SDHI1I3),
202 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), 200 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
203 INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1), 201 INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
204 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), 202 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
@@ -236,10 +234,10 @@ static struct intc_mask_reg intca_mask_registers[] = {
236 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 234 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
237 0, 0, MSIOF2, 0 } }, 235 0, 0, MSIOF2, 0 } },
238 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
239 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, 237 { DISABLED, DISABLED, ENABLED, ENABLED,
240 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
241 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
242 { SDHI1_SDHI1I3, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, 240 { DISABLED, DISABLED, ENABLED, ENABLED,
243 TTI20, USBDMAC_USHDMI, 0, MSUG } }, 241 TTI20, USBDMAC_USHDMI, 0, MSUG } },
244 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
245 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -339,10 +337,14 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
339 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 337 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
340}; 338};
341 339
342static DECLARE_INTC_DESC_ACK(intca_desc, "sh7377-intca", 340static struct intc_desc intca_desc __initdata = {
343 intca_vectors, intca_groups, 341 .name = "sh7377-intca",
344 intca_mask_registers, intca_prio_registers, 342 .force_enable = ENABLED,
345 intca_sense_registers, intca_ack_registers); 343 .force_disable = DISABLED,
344 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
345 intca_mask_registers, intca_prio_registers,
346 intca_sense_registers, intca_ack_registers),
347};
346 348
347void __init sh7377_init_irq(void) 349void __init sh7377_init_irq(void)
348{ 350{