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Diffstat (limited to 'arch/arm/mach-shmobile/intc-sh7372.c')
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c232
1 files changed, 226 insertions, 6 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 3ce9d9bd5899..e3551b56cd03 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -319,17 +319,17 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
319 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, 319 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
320 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, 320 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
321 CMT14, CMT15 } }, 321 CMT14, CMT15 } },
322 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, 322 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
323 MMC_MMC_ERR, MMC_MMC_NOR } }, 323 MMC_MMC_ERR, MMC_MMC_NOR } },
324 { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, 324 { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
325 IIC4_WAITI4, IIC4_DTEI4 } }, 325 IIC4_WAITI4, IIC4_DTEI4 } },
326 { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, 326 { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
327 IIC3_WAITI3, IIC3_DTEI3 } }, 327 IIC3_WAITI3, IIC3_DTEI3 } },
328 { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, 328 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
329 0/*TXI*/, 0/*TEI*/} }, 329 0/*TXI*/, 0/*TEI*/} },
330 { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, 330 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
331 USB1_USB1I1, USB1_USB1I0 } }, 331 USB1_USB1I1, USB1_USB1I0 } },
332 { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, 332 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
333}; 333};
334 334
335static struct intc_sense_reg intca_sense_registers[] __initdata = { 335static struct intc_sense_reg intca_sense_registers[] __initdata = {
@@ -363,7 +363,227 @@ static struct intc_desc intca_desc __initdata = {
363 intca_sense_registers, intca_ack_registers), 363 intca_sense_registers, intca_ack_registers),
364}; 364};
365 365
366enum {
367 UNUSED_INTCS = 0,
368
369 INTCS,
370
371 /* interrupt sources INTCS */
372 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
373 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
374 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
375 VPU,
376 TSIF1,
377 _3DG_SGX530,
378 _2DDMAC,
379 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
380 IPMMU_IPMMUR, IPMMU_IPMMUR2,
381 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
382 MSIOF,
383 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
384 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
385 CMT0,
386 TSIF0,
387 LMB,
388 CTI,
389 ICB,
390 JPU_JPEG,
391 LCDC,
392 LCRC,
393 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
394 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
395 ISP,
396 LCDC1,
397 CSIRX,
398 DSITX_DSITX0,
399 DSITX_DSITX1,
400 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
401 CMT4,
402 DSITX1_DSITX1_0,
403 DSITX1_DSITX1_1,
404 CPORTS2R,
405 JPU6E,
406
407 /* interrupt groups INTCS */
408 RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
409 RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
410};
411
412static struct intc_vect intcs_vectors[] = {
413 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
414 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
415 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
416 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
417 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
418 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
419 INTCS_VECT(VPU, 0x980),
420 INTCS_VECT(TSIF1, 0x9a0),
421 INTCS_VECT(_3DG_SGX530, 0x9e0),
422 INTCS_VECT(_2DDMAC, 0xa00),
423 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
424 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
425 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
426 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
427 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
428 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
429 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
430 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
431 INTCS_VECT(TMU_TUNI2, 0xec0),
432 INTCS_VECT(CMT0, 0xf00),
433 INTCS_VECT(TSIF0, 0xf20),
434 INTCS_VECT(LMB, 0xf60),
435 INTCS_VECT(CTI, 0x400),
436 INTCS_VECT(ICB, 0x480),
437 INTCS_VECT(JPU_JPEG, 0x560),
438 INTCS_VECT(LCDC, 0x580),
439 INTCS_VECT(LCRC, 0x5a0),
440 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
441 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
442 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
443 INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
444 INTCS_VECT(ISP, 0x1720),
445 INTCS_VECT(LCDC1, 0x1780),
446 INTCS_VECT(CSIRX, 0x17a0),
447 INTCS_VECT(DSITX_DSITX0, 0x17c0),
448 INTCS_VECT(DSITX_DSITX1, 0x17e0),
449 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
450 INTCS_VECT(TMU1_TUNI2, 0x1940),
451 INTCS_VECT(CMT4, 0x1980),
452 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
453 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
454 INTCS_VECT(CPORTS2R, 0x1a20),
455 INTCS_VECT(JPU6E, 0x1a80),
456
457 INTC_VECT(INTCS, 0xf80),
458};
459
460static struct intc_group intcs_groups[] __initdata = {
461 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
462 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
463 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
464 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
465 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
466 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
467 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
468 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
469 INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
470 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
471 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
472 RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
473 INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
474 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
475};
476
477static struct intc_mask_reg intcs_mask_registers[] = {
478 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
479 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
480 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
481 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
482 { 0, 0, 0, VPU,
483 0, 0, 0, 0 } },
484 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
485 { 0, 0, 0, _2DDMAC,
486 0, 0, 0, ICB } },
487 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
488 { 0, 0, 0, CTI,
489 JPU_JPEG, 0, LCRC, LCDC } },
490 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
491 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
492 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
493 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
494 { 0, 0, MSIOF, 0,
495 _3DG_SGX530, 0, 0, 0 } },
496 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
497 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
498 0, 0, 0, 0 } },
499 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
500 { 0, 0, 0, CMT0,
501 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
502 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
503 { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
504 0, 0, 0, 0 } },
505 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
506 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
507 0, TSIF1, LMB, TSIF0 } },
508 { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
509 { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
510 RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
511 { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
512 { 0, ISP, 0, 0,
513 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
514 { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
515 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
516 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
517 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
518 { 0, CPORTS2R, 0, 0,
519 JPU6E, 0, 0, 0 } },
520 { 0xffd20104, 0, 16, /* INTAMASK */
521 { 0, 0, 0, 0, 0, 0, 0, 0,
522 0, 0, 0, 0, 0, 0, 0, INTCS } },
523};
524
525/* Priority is needed for INTCA to receive the INTCS interrupt */
526static struct intc_prio_reg intcs_prio_registers[] = {
527 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
528 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
529 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
530 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
531 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
532 TMU_TUNI2, TSIF1 } },
533 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
534 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
535 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
536 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
537 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
538 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
539 { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
540 { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
541 { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
542 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
543 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
544 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
545 DSITX1_DSITX1_1, 0 } },
546 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
547 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
548};
549
550static struct resource intcs_resources[] __initdata = {
551 [0] = {
552 .start = 0xffd20000,
553 .end = 0xffd201ff,
554 .flags = IORESOURCE_MEM,
555 },
556 [1] = {
557 .start = 0xffd50000,
558 .end = 0xffd501ff,
559 .flags = IORESOURCE_MEM,
560 }
561};
562
563static struct intc_desc intcs_desc __initdata = {
564 .name = "sh7372-intcs",
565 .resource = intcs_resources,
566 .num_resources = ARRAY_SIZE(intcs_resources),
567 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
568 intcs_prio_registers, NULL, NULL),
569};
570
571static void intcs_demux(unsigned int irq, struct irq_desc *desc)
572{
573 void __iomem *reg = (void *)get_irq_data(irq);
574 unsigned int evtcodeas = ioread32(reg);
575
576 generic_handle_irq(intcs_evt2irq(evtcodeas));
577}
578
366void __init sh7372_init_irq(void) 579void __init sh7372_init_irq(void)
367{ 580{
581 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
582
368 register_intc_controller(&intca_desc); 583 register_intc_controller(&intca_desc);
584 register_intc_controller(&intcs_desc);
585
586 /* demux using INTEVTSA */
587 set_irq_data(evt2irq(0xf80), (void *)intevtsa);
588 set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
369} 589}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 16:47:09 -0500