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-rw-r--r--arch/arm/mach-s5pv210/clock.c107
-rw-r--r--arch/arm/mach-s5pv210/common.c19
-rw-r--r--arch/arm/mach-s5pv210/dma.c241
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h2
4 files changed, 138 insertions, 231 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 04c9b578e626..d8df66887060 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -810,46 +810,6 @@ static struct clksrc_clk clksrcs[] = {
810 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, 810 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
811 }, { 811 }, {
812 .clk = { 812 .clk = {
813 .name = "uclk1",
814 .devname = "s5pv210-uart.0",
815 .enable = s5pv210_clk_mask0_ctrl,
816 .ctrlbit = (1 << 12),
817 },
818 .sources = &clkset_uart,
819 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
820 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
821 }, {
822 .clk = {
823 .name = "uclk1",
824 .devname = "s5pv210-uart.1",
825 .enable = s5pv210_clk_mask0_ctrl,
826 .ctrlbit = (1 << 13),
827 },
828 .sources = &clkset_uart,
829 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
830 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
831 }, {
832 .clk = {
833 .name = "uclk1",
834 .devname = "s5pv210-uart.2",
835 .enable = s5pv210_clk_mask0_ctrl,
836 .ctrlbit = (1 << 14),
837 },
838 .sources = &clkset_uart,
839 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
840 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
841 }, {
842 .clk = {
843 .name = "uclk1",
844 .devname = "s5pv210-uart.3",
845 .enable = s5pv210_clk_mask0_ctrl,
846 .ctrlbit = (1 << 15),
847 },
848 .sources = &clkset_uart,
849 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
850 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
851 }, {
852 .clk = {
853 .name = "sclk_fimc", 813 .name = "sclk_fimc",
854 .devname = "s5pv210-fimc.0", 814 .devname = "s5pv210-fimc.0",
855 .enable = s5pv210_clk_mask1_ctrl, 815 .enable = s5pv210_clk_mask1_ctrl,
@@ -1023,6 +983,61 @@ static struct clksrc_clk clksrcs[] = {
1023 }, 983 },
1024}; 984};
1025 985
986static struct clksrc_clk clk_sclk_uart0 = {
987 .clk = {
988 .name = "uclk1",
989 .devname = "s5pv210-uart.0",
990 .enable = s5pv210_clk_mask0_ctrl,
991 .ctrlbit = (1 << 12),
992 },
993 .sources = &clkset_uart,
994 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
995 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
996};
997
998static struct clksrc_clk clk_sclk_uart1 = {
999 .clk = {
1000 .name = "uclk1",
1001 .devname = "s5pv210-uart.1",
1002 .enable = s5pv210_clk_mask0_ctrl,
1003 .ctrlbit = (1 << 13),
1004 },
1005 .sources = &clkset_uart,
1006 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
1007 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
1008};
1009
1010static struct clksrc_clk clk_sclk_uart2 = {
1011 .clk = {
1012 .name = "uclk1",
1013 .devname = "s5pv210-uart.2",
1014 .enable = s5pv210_clk_mask0_ctrl,
1015 .ctrlbit = (1 << 14),
1016 },
1017 .sources = &clkset_uart,
1018 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
1019 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
1020};
1021
1022static struct clksrc_clk clk_sclk_uart3 = {
1023 .clk = {
1024 .name = "uclk1",
1025 .devname = "s5pv210-uart.3",
1026 .enable = s5pv210_clk_mask0_ctrl,
1027 .ctrlbit = (1 << 15),
1028 },
1029 .sources = &clkset_uart,
1030 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
1031 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
1032};
1033
1034static struct clksrc_clk *clksrc_cdev[] = {
1035 &clk_sclk_uart0,
1036 &clk_sclk_uart1,
1037 &clk_sclk_uart2,
1038 &clk_sclk_uart3,
1039};
1040
1026/* Clock initialisation code */ 1041/* Clock initialisation code */
1027static struct clksrc_clk *sysclks[] = { 1042static struct clksrc_clk *sysclks[] = {
1028 &clk_mout_apll, 1043 &clk_mout_apll,
@@ -1262,6 +1277,14 @@ static struct clk *clks[] __initdata = {
1262 &clk_pcmcdclk2, 1277 &clk_pcmcdclk2,
1263}; 1278};
1264 1279
1280static struct clk_lookup s5pv210_clk_lookup[] = {
1281 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1282 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1283 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1284 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1285 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1286};
1287
1265void __init s5pv210_register_clocks(void) 1288void __init s5pv210_register_clocks(void)
1266{ 1289{
1267 int ptr; 1290 int ptr;
@@ -1274,11 +1297,15 @@ void __init s5pv210_register_clocks(void)
1274 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1297 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1275 s3c_register_clksrc(sclk_tv[ptr], 1); 1298 s3c_register_clksrc(sclk_tv[ptr], 1);
1276 1299
1300 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1301 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1302
1277 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1303 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1278 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1304 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1279 1305
1280 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1306 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1281 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1307 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1308 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1282 1309
1283 s3c24xx_register_clock(&dummy_apb_pclk); 1310 s3c24xx_register_clock(&dummy_apb_pclk);
1284 s3c_pwmclk_init(); 1311 s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 0ec393305d7c..9c1bcdcc12c3 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -254,28 +254,9 @@ int __init s5pv210_init(void)
254 return device_register(&s5pv210_dev); 254 return device_register(&s5pv210_dev);
255} 255}
256 256
257static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = {
258 [0] = {
259 .name = "pclk",
260 .divisor = 1,
261 .min_baud = 0,
262 .max_baud = 0,
263 },
264};
265
266/* uart registration process */ 257/* uart registration process */
267 258
268void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no) 259void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
269{ 260{
270 struct s3c2410_uartcfg *tcfg = cfg;
271 u32 ucnt;
272
273 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
274 if (!tcfg->clocks) {
275 tcfg->clocks = s5pv210_serial_clocks;
276 tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks);
277 }
278 }
279
280 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); 261 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
281} 262}
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 86b749c18b77..a6113e0267f2 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -35,90 +35,40 @@
35 35
36static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
37 37
38struct dma_pl330_peri pdma0_peri[28] = { 38u8 pdma0_peri[] = {
39 { 39 DMACH_UART0_RX,
40 .peri_id = (u8)DMACH_UART0_RX, 40 DMACH_UART0_TX,
41 .rqtype = DEVTOMEM, 41 DMACH_UART1_RX,
42 }, { 42 DMACH_UART1_TX,
43 .peri_id = (u8)DMACH_UART0_TX, 43 DMACH_UART2_RX,
44 .rqtype = MEMTODEV, 44 DMACH_UART2_TX,
45 }, { 45 DMACH_UART3_RX,
46 .peri_id = (u8)DMACH_UART1_RX, 46 DMACH_UART3_TX,
47 .rqtype = DEVTOMEM, 47 DMACH_MAX,
48 }, { 48 DMACH_I2S0_RX,
49 .peri_id = (u8)DMACH_UART1_TX, 49 DMACH_I2S0_TX,
50 .rqtype = MEMTODEV, 50 DMACH_I2S0S_TX,
51 }, { 51 DMACH_I2S1_RX,
52 .peri_id = (u8)DMACH_UART2_RX, 52 DMACH_I2S1_TX,
53 .rqtype = DEVTOMEM, 53 DMACH_MAX,
54 }, { 54 DMACH_MAX,
55 .peri_id = (u8)DMACH_UART2_TX, 55 DMACH_SPI0_RX,
56 .rqtype = MEMTODEV, 56 DMACH_SPI0_TX,
57 }, { 57 DMACH_SPI1_RX,
58 .peri_id = (u8)DMACH_UART3_RX, 58 DMACH_SPI1_TX,
59 .rqtype = DEVTOMEM, 59 DMACH_MAX,
60 }, { 60 DMACH_MAX,
61 .peri_id = (u8)DMACH_UART3_TX, 61 DMACH_AC97_MICIN,
62 .rqtype = MEMTODEV, 62 DMACH_AC97_PCMIN,
63 }, { 63 DMACH_AC97_PCMOUT,
64 .peri_id = DMACH_MAX, 64 DMACH_MAX,
65 }, { 65 DMACH_PWM,
66 .peri_id = (u8)DMACH_I2S0_RX, 66 DMACH_SPDIF,
67 .rqtype = DEVTOMEM,
68 }, {
69 .peri_id = (u8)DMACH_I2S0_TX,
70 .rqtype = MEMTODEV,
71 }, {
72 .peri_id = (u8)DMACH_I2S0S_TX,
73 .rqtype = MEMTODEV,
74 }, {
75 .peri_id = (u8)DMACH_I2S1_RX,
76 .rqtype = DEVTOMEM,
77 }, {
78 .peri_id = (u8)DMACH_I2S1_TX,
79 .rqtype = MEMTODEV,
80 }, {
81 .peri_id = (u8)DMACH_MAX,
82 }, {
83 .peri_id = (u8)DMACH_MAX,
84 }, {
85 .peri_id = (u8)DMACH_SPI0_RX,
86 .rqtype = DEVTOMEM,
87 }, {
88 .peri_id = (u8)DMACH_SPI0_TX,
89 .rqtype = MEMTODEV,
90 }, {
91 .peri_id = (u8)DMACH_SPI1_RX,
92 .rqtype = DEVTOMEM,
93 }, {
94 .peri_id = (u8)DMACH_SPI1_TX,
95 .rqtype = MEMTODEV,
96 }, {
97 .peri_id = (u8)DMACH_MAX,
98 }, {
99 .peri_id = (u8)DMACH_MAX,
100 }, {
101 .peri_id = (u8)DMACH_AC97_MICIN,
102 .rqtype = DEVTOMEM,
103 }, {
104 .peri_id = (u8)DMACH_AC97_PCMIN,
105 .rqtype = DEVTOMEM,
106 }, {
107 .peri_id = (u8)DMACH_AC97_PCMOUT,
108 .rqtype = MEMTODEV,
109 }, {
110 .peri_id = (u8)DMACH_MAX,
111 }, {
112 .peri_id = (u8)DMACH_PWM,
113 }, {
114 .peri_id = (u8)DMACH_SPDIF,
115 .rqtype = MEMTODEV,
116 },
117}; 67};
118 68
119struct dma_pl330_platdata s5pv210_pdma0_pdata = { 69struct dma_pl330_platdata s5pv210_pdma0_pdata = {
120 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 70 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
121 .peri = pdma0_peri, 71 .peri_id = pdma0_peri,
122}; 72};
123 73
124struct amba_device s5pv210_device_pdma0 = { 74struct amba_device s5pv210_device_pdma0 = {
@@ -137,102 +87,44 @@ struct amba_device s5pv210_device_pdma0 = {
137 .periphid = 0x00041330, 87 .periphid = 0x00041330,
138}; 88};
139 89
140struct dma_pl330_peri pdma1_peri[32] = { 90u8 pdma1_peri[] = {
141 { 91 DMACH_UART0_RX,
142 .peri_id = (u8)DMACH_UART0_RX, 92 DMACH_UART0_TX,
143 .rqtype = DEVTOMEM, 93 DMACH_UART1_RX,
144 }, { 94 DMACH_UART1_TX,
145 .peri_id = (u8)DMACH_UART0_TX, 95 DMACH_UART2_RX,
146 .rqtype = MEMTODEV, 96 DMACH_UART2_TX,
147 }, { 97 DMACH_UART3_RX,
148 .peri_id = (u8)DMACH_UART1_RX, 98 DMACH_UART3_TX,
149 .rqtype = DEVTOMEM, 99 DMACH_MAX,
150 }, { 100 DMACH_I2S0_RX,
151 .peri_id = (u8)DMACH_UART1_TX, 101 DMACH_I2S0_TX,
152 .rqtype = MEMTODEV, 102 DMACH_I2S0S_TX,
153 }, { 103 DMACH_I2S1_RX,
154 .peri_id = (u8)DMACH_UART2_RX, 104 DMACH_I2S1_TX,
155 .rqtype = DEVTOMEM, 105 DMACH_I2S2_RX,
156 }, { 106 DMACH_I2S2_TX,
157 .peri_id = (u8)DMACH_UART2_TX, 107 DMACH_SPI0_RX,
158 .rqtype = MEMTODEV, 108 DMACH_SPI0_TX,
159 }, { 109 DMACH_SPI1_RX,
160 .peri_id = (u8)DMACH_UART3_RX, 110 DMACH_SPI1_TX,
161 .rqtype = DEVTOMEM, 111 DMACH_MAX,
162 }, { 112 DMACH_MAX,
163 .peri_id = (u8)DMACH_UART3_TX, 113 DMACH_PCM0_RX,
164 .rqtype = MEMTODEV, 114 DMACH_PCM0_TX,
165 }, { 115 DMACH_PCM1_RX,
166 .peri_id = DMACH_MAX, 116 DMACH_PCM1_TX,
167 }, { 117 DMACH_MSM_REQ0,
168 .peri_id = (u8)DMACH_I2S0_RX, 118 DMACH_MSM_REQ1,
169 .rqtype = DEVTOMEM, 119 DMACH_MSM_REQ2,
170 }, { 120 DMACH_MSM_REQ3,
171 .peri_id = (u8)DMACH_I2S0_TX, 121 DMACH_PCM2_RX,
172 .rqtype = MEMTODEV, 122 DMACH_PCM2_TX,
173 }, {
174 .peri_id = (u8)DMACH_I2S0S_TX,
175 .rqtype = MEMTODEV,
176 }, {
177 .peri_id = (u8)DMACH_I2S1_RX,
178 .rqtype = DEVTOMEM,
179 }, {
180 .peri_id = (u8)DMACH_I2S1_TX,
181 .rqtype = MEMTODEV,
182 }, {
183 .peri_id = (u8)DMACH_I2S2_RX,
184 .rqtype = DEVTOMEM,
185 }, {
186 .peri_id = (u8)DMACH_I2S2_TX,
187 .rqtype = MEMTODEV,
188 }, {
189 .peri_id = (u8)DMACH_SPI0_RX,
190 .rqtype = DEVTOMEM,
191 }, {
192 .peri_id = (u8)DMACH_SPI0_TX,
193 .rqtype = MEMTODEV,
194 }, {
195 .peri_id = (u8)DMACH_SPI1_RX,
196 .rqtype = DEVTOMEM,
197 }, {
198 .peri_id = (u8)DMACH_SPI1_TX,
199 .rqtype = MEMTODEV,
200 }, {
201 .peri_id = (u8)DMACH_MAX,
202 }, {
203 .peri_id = (u8)DMACH_MAX,
204 }, {
205 .peri_id = (u8)DMACH_PCM0_RX,
206 .rqtype = DEVTOMEM,
207 }, {
208 .peri_id = (u8)DMACH_PCM0_TX,
209 .rqtype = MEMTODEV,
210 }, {
211 .peri_id = (u8)DMACH_PCM1_RX,
212 .rqtype = DEVTOMEM,
213 }, {
214 .peri_id = (u8)DMACH_PCM1_TX,
215 .rqtype = MEMTODEV,
216 }, {
217 .peri_id = (u8)DMACH_MSM_REQ0,
218 }, {
219 .peri_id = (u8)DMACH_MSM_REQ1,
220 }, {
221 .peri_id = (u8)DMACH_MSM_REQ2,
222 }, {
223 .peri_id = (u8)DMACH_MSM_REQ3,
224 }, {
225 .peri_id = (u8)DMACH_PCM2_RX,
226 .rqtype = DEVTOMEM,
227 }, {
228 .peri_id = (u8)DMACH_PCM2_TX,
229 .rqtype = MEMTODEV,
230 },
231}; 123};
232 124
233struct dma_pl330_platdata s5pv210_pdma1_pdata = { 125struct dma_pl330_platdata s5pv210_pdma1_pdata = {
234 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 126 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
235 .peri = pdma1_peri, 127 .peri_id = pdma1_peri,
236}; 128};
237 129
238struct amba_device s5pv210_device_pdma1 = { 130struct amba_device s5pv210_device_pdma1 = {
@@ -253,7 +145,12 @@ struct amba_device s5pv210_device_pdma1 = {
253 145
254static int __init s5pv210_dma_init(void) 146static int __init s5pv210_dma_init(void)
255{ 147{
148 dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
149 dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
256 amba_device_register(&s5pv210_device_pdma0, &iomem_resource); 150 amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
151
152 dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
153 dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
257 amba_device_register(&s5pv210_device_pdma1, &iomem_resource); 154 amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
258 155
259 return 0; 156 return 0;
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 5e0de3a31f3d..e777e010ed2e 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -118,6 +118,8 @@
118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8) 118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
119#define IRQ_VIC_END S5P_IRQ_VIC3(31) 119#define IRQ_VIC_END S5P_IRQ_VIC3(31)
120 120
121#define IRQ_TIMER_BASE (11)
122
121#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) 123#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
122#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) 124#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
123 125
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 04:07:22 -0500