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-rw-r--r--arch/arm/mach-s5pv210/Kconfig2
-rw-r--r--arch/arm/mach-s5pv210/Makefile1
-rw-r--r--arch/arm/mach-s5pv210/clock.c174
-rw-r--r--arch/arm/mach-s5pv210/cpu.c2
-rw-r--r--arch/arm/mach-s5pv210/cpufreq.c485
-rw-r--r--arch/arm/mach-s5pv210/dev-audio.c2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5pv210/include/mach/pm-core.h3
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-audss.h18
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-fb.h21
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c2
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c12
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c57
-rw-r--r--arch/arm/mach-s5pv210/pm.c2
-rw-r--r--arch/arm/mach-s5pv210/setup-fb-24bpp.c1
-rw-r--r--arch/arm/mach-s5pv210/sleep.S21
17 files changed, 112 insertions, 701 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 37b5a97594a5..69dd87cd8e22 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -90,6 +90,7 @@ config MACH_GONI
90 select S3C_DEV_HSMMC2 90 select S3C_DEV_HSMMC2
91 select S3C_DEV_I2C1 91 select S3C_DEV_I2C1
92 select S3C_DEV_I2C2 92 select S3C_DEV_I2C2
93 select S5P_DEV_MFC
93 select S3C_DEV_USB_HSOTG 94 select S3C_DEV_USB_HSOTG
94 select S5P_DEV_ONENAND 95 select S5P_DEV_ONENAND
95 select SAMSUNG_DEV_KEYPAD 96 select SAMSUNG_DEV_KEYPAD
@@ -134,6 +135,7 @@ config MACH_SMDKV210
134 select S3C_DEV_RTC 135 select S3C_DEV_RTC
135 select S3C_DEV_WDT 136 select S3C_DEV_WDT
136 select SAMSUNG_DEV_ADC 137 select SAMSUNG_DEV_ADC
138 select SAMSUNG_DEV_BACKLIGHT
137 select SAMSUNG_DEV_IDE 139 select SAMSUNG_DEV_IDE
138 select SAMSUNG_DEV_KEYPAD 140 select SAMSUNG_DEV_KEYPAD
139 select SAMSUNG_DEV_PWM 141 select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 50907aca006c..599a3c0e8f6c 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -15,7 +15,6 @@ obj- :=
15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o 15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o 16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o 17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19 18
20# machine support 19# machine support
21 20
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d599499cefe..52a8e607bcc2 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -36,7 +36,6 @@ static unsigned long xtal;
36static struct clksrc_clk clk_mout_apll = { 36static struct clksrc_clk clk_mout_apll = {
37 .clk = { 37 .clk = {
38 .name = "mout_apll", 38 .name = "mout_apll",
39 .id = -1,
40 }, 39 },
41 .sources = &clk_src_apll, 40 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
45static struct clksrc_clk clk_mout_epll = { 44static struct clksrc_clk clk_mout_epll = {
46 .clk = { 45 .clk = {
47 .name = "mout_epll", 46 .name = "mout_epll",
48 .id = -1,
49 }, 47 },
50 .sources = &clk_src_epll, 48 .sources = &clk_src_epll,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
54static struct clksrc_clk clk_mout_mpll = { 52static struct clksrc_clk clk_mout_mpll = {
55 .clk = { 53 .clk = {
56 .name = "mout_mpll", 54 .name = "mout_mpll",
57 .id = -1,
58 }, 55 },
59 .sources = &clk_src_mpll, 56 .sources = &clk_src_mpll,
60 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
73static struct clksrc_clk clk_armclk = { 70static struct clksrc_clk clk_armclk = {
74 .clk = { 71 .clk = {
75 .name = "armclk", 72 .name = "armclk",
76 .id = -1,
77 }, 73 },
78 .sources = &clkset_armclk, 74 .sources = &clkset_armclk,
79 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
83static struct clksrc_clk clk_hclk_msys = { 79static struct clksrc_clk clk_hclk_msys = {
84 .clk = { 80 .clk = {
85 .name = "hclk_msys", 81 .name = "hclk_msys",
86 .id = -1,
87 .parent = &clk_armclk.clk, 82 .parent = &clk_armclk.clk,
88 }, 83 },
89 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
92static struct clksrc_clk clk_pclk_msys = { 87static struct clksrc_clk clk_pclk_msys = {
93 .clk = { 88 .clk = {
94 .name = "pclk_msys", 89 .name = "pclk_msys",
95 .id = -1,
96 .parent = &clk_hclk_msys.clk, 90 .parent = &clk_hclk_msys.clk,
97 }, 91 },
98 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
101static struct clksrc_clk clk_sclk_a2m = { 95static struct clksrc_clk clk_sclk_a2m = {
102 .clk = { 96 .clk = {
103 .name = "sclk_a2m", 97 .name = "sclk_a2m",
104 .id = -1,
105 .parent = &clk_mout_apll.clk, 98 .parent = &clk_mout_apll.clk,
106 }, 99 },
107 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
120static struct clksrc_clk clk_hclk_dsys = { 113static struct clksrc_clk clk_hclk_dsys = {
121 .clk = { 114 .clk = {
122 .name = "hclk_dsys", 115 .name = "hclk_dsys",
123 .id = -1,
124 }, 116 },
125 .sources = &clkset_hclk_sys, 117 .sources = &clkset_hclk_sys,
126 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
130static struct clksrc_clk clk_pclk_dsys = { 122static struct clksrc_clk clk_pclk_dsys = {
131 .clk = { 123 .clk = {
132 .name = "pclk_dsys", 124 .name = "pclk_dsys",
133 .id = -1,
134 .parent = &clk_hclk_dsys.clk, 125 .parent = &clk_hclk_dsys.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
139static struct clksrc_clk clk_hclk_psys = { 130static struct clksrc_clk clk_hclk_psys = {
140 .clk = { 131 .clk = {
141 .name = "hclk_psys", 132 .name = "hclk_psys",
142 .id = -1,
143 }, 133 },
144 .sources = &clkset_hclk_sys, 134 .sources = &clkset_hclk_sys,
145 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
149static struct clksrc_clk clk_pclk_psys = { 139static struct clksrc_clk clk_pclk_psys = {
150 .clk = { 140 .clk = {
151 .name = "pclk_psys", 141 .name = "pclk_psys",
152 .id = -1,
153 .parent = &clk_hclk_psys.clk, 142 .parent = &clk_hclk_psys.clk,
154 }, 143 },
155 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, 144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187 176
188static struct clk clk_sclk_hdmi27m = { 177static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m", 178 .name = "sclk_hdmi27m",
190 .id = -1,
191 .rate = 27000000, 179 .rate = 27000000,
192}; 180};
193 181
194static struct clk clk_sclk_hdmiphy = { 182static struct clk clk_sclk_hdmiphy = {
195 .name = "sclk_hdmiphy", 183 .name = "sclk_hdmiphy",
196 .id = -1,
197}; 184};
198 185
199static struct clk clk_sclk_usbphy0 = { 186static struct clk clk_sclk_usbphy0 = {
200 .name = "sclk_usbphy0", 187 .name = "sclk_usbphy0",
201 .id = -1,
202}; 188};
203 189
204static struct clk clk_sclk_usbphy1 = { 190static struct clk clk_sclk_usbphy1 = {
205 .name = "sclk_usbphy1", 191 .name = "sclk_usbphy1",
206 .id = -1,
207}; 192};
208 193
209static struct clk clk_pcmcdclk0 = { 194static struct clk clk_pcmcdclk0 = {
210 .name = "pcmcdclk", 195 .name = "pcmcdclk",
211 .id = -1,
212}; 196};
213 197
214static struct clk clk_pcmcdclk1 = { 198static struct clk clk_pcmcdclk1 = {
215 .name = "pcmcdclk", 199 .name = "pcmcdclk",
216 .id = -1,
217}; 200};
218 201
219static struct clk clk_pcmcdclk2 = { 202static struct clk clk_pcmcdclk2 = {
220 .name = "pcmcdclk", 203 .name = "pcmcdclk",
221 .id = -1,
222}; 204};
223 205
224static struct clk *clkset_vpllsrc_list[] = { 206static struct clk *clkset_vpllsrc_list[] = {
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
234static struct clksrc_clk clk_vpllsrc = { 216static struct clksrc_clk clk_vpllsrc = {
235 .clk = { 217 .clk = {
236 .name = "vpll_src", 218 .name = "vpll_src",
237 .id = -1,
238 .enable = s5pv210_clk_mask0_ctrl, 219 .enable = s5pv210_clk_mask0_ctrl,
239 .ctrlbit = (1 << 7), 220 .ctrlbit = (1 << 7),
240 }, 221 },
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
255static struct clksrc_clk clk_sclk_vpll = { 236static struct clksrc_clk clk_sclk_vpll = {
256 .clk = { 237 .clk = {
257 .name = "sclk_vpll", 238 .name = "sclk_vpll",
258 .id = -1,
259 }, 239 },
260 .sources = &clkset_sclk_vpll, 240 .sources = &clkset_sclk_vpll,
261 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 241 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
276static struct clksrc_clk clk_mout_dmc0 = { 256static struct clksrc_clk clk_mout_dmc0 = {
277 .clk = { 257 .clk = {
278 .name = "mout_dmc0", 258 .name = "mout_dmc0",
279 .id = -1,
280 }, 259 },
281 .sources = &clkset_moutdmc0src, 260 .sources = &clkset_moutdmc0src,
282 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 261 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
285static struct clksrc_clk clk_sclk_dmc0 = { 264static struct clksrc_clk clk_sclk_dmc0 = {
286 .clk = { 265 .clk = {
287 .name = "sclk_dmc0", 266 .name = "sclk_dmc0",
288 .id = -1,
289 .parent = &clk_mout_dmc0.clk, 267 .parent = &clk_mout_dmc0.clk,
290 }, 268 },
291 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, 269 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@@ -312,181 +290,175 @@ static struct clk_ops clk_fout_apll_ops = {
312static struct clk init_clocks_off[] = { 290static struct clk init_clocks_off[] = {
313 { 291 {
314 .name = "pdma", 292 .name = "pdma",
315 .id = 0, 293 .devname = "s3c-pl330.0",
316 .parent = &clk_hclk_psys.clk, 294 .parent = &clk_hclk_psys.clk,
317 .enable = s5pv210_clk_ip0_ctrl, 295 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 3), 296 .ctrlbit = (1 << 3),
319 }, { 297 }, {
320 .name = "pdma", 298 .name = "pdma",
321 .id = 1, 299 .devname = "s3c-pl330.1",
322 .parent = &clk_hclk_psys.clk, 300 .parent = &clk_hclk_psys.clk,
323 .enable = s5pv210_clk_ip0_ctrl, 301 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 4), 302 .ctrlbit = (1 << 4),
325 }, { 303 }, {
326 .name = "rot", 304 .name = "rot",
327 .id = -1,
328 .parent = &clk_hclk_dsys.clk, 305 .parent = &clk_hclk_dsys.clk,
329 .enable = s5pv210_clk_ip0_ctrl, 306 .enable = s5pv210_clk_ip0_ctrl,
330 .ctrlbit = (1<<29), 307 .ctrlbit = (1<<29),
331 }, { 308 }, {
332 .name = "fimc", 309 .name = "fimc",
333 .id = 0, 310 .devname = "s5pv210-fimc.0",
334 .parent = &clk_hclk_dsys.clk, 311 .parent = &clk_hclk_dsys.clk,
335 .enable = s5pv210_clk_ip0_ctrl, 312 .enable = s5pv210_clk_ip0_ctrl,
336 .ctrlbit = (1 << 24), 313 .ctrlbit = (1 << 24),
337 }, { 314 }, {
338 .name = "fimc", 315 .name = "fimc",
339 .id = 1, 316 .devname = "s5pv210-fimc.1",
340 .parent = &clk_hclk_dsys.clk, 317 .parent = &clk_hclk_dsys.clk,
341 .enable = s5pv210_clk_ip0_ctrl, 318 .enable = s5pv210_clk_ip0_ctrl,
342 .ctrlbit = (1 << 25), 319 .ctrlbit = (1 << 25),
343 }, { 320 }, {
344 .name = "fimc", 321 .name = "fimc",
345 .id = 2, 322 .devname = "s5pv210-fimc.2",
346 .parent = &clk_hclk_dsys.clk, 323 .parent = &clk_hclk_dsys.clk,
347 .enable = s5pv210_clk_ip0_ctrl, 324 .enable = s5pv210_clk_ip0_ctrl,
348 .ctrlbit = (1 << 26), 325 .ctrlbit = (1 << 26),
349 }, { 326 }, {
327 .name = "mfc",
328 .devname = "s5p-mfc",
329 .parent = &clk_pclk_psys.clk,
330 .enable = s5pv210_clk_ip0_ctrl,
331 .ctrlbit = (1 << 16),
332 }, {
350 .name = "otg", 333 .name = "otg",
351 .id = -1,
352 .parent = &clk_hclk_psys.clk, 334 .parent = &clk_hclk_psys.clk,
353 .enable = s5pv210_clk_ip1_ctrl, 335 .enable = s5pv210_clk_ip1_ctrl,
354 .ctrlbit = (1<<16), 336 .ctrlbit = (1<<16),
355 }, { 337 }, {
356 .name = "usb-host", 338 .name = "usb-host",
357 .id = -1,
358 .parent = &clk_hclk_psys.clk, 339 .parent = &clk_hclk_psys.clk,
359 .enable = s5pv210_clk_ip1_ctrl, 340 .enable = s5pv210_clk_ip1_ctrl,
360 .ctrlbit = (1<<17), 341 .ctrlbit = (1<<17),
361 }, { 342 }, {
362 .name = "lcd", 343 .name = "lcd",
363 .id = -1,
364 .parent = &clk_hclk_dsys.clk, 344 .parent = &clk_hclk_dsys.clk,
365 .enable = s5pv210_clk_ip1_ctrl, 345 .enable = s5pv210_clk_ip1_ctrl,
366 .ctrlbit = (1<<0), 346 .ctrlbit = (1<<0),
367 }, { 347 }, {
368 .name = "cfcon", 348 .name = "cfcon",
369 .id = 0,
370 .parent = &clk_hclk_psys.clk, 349 .parent = &clk_hclk_psys.clk,
371 .enable = s5pv210_clk_ip1_ctrl, 350 .enable = s5pv210_clk_ip1_ctrl,
372 .ctrlbit = (1<<25), 351 .ctrlbit = (1<<25),
373 }, { 352 }, {
374 .name = "hsmmc", 353 .name = "hsmmc",
375 .id = 0, 354 .devname = "s3c-sdhci.0",
376 .parent = &clk_hclk_psys.clk, 355 .parent = &clk_hclk_psys.clk,
377 .enable = s5pv210_clk_ip2_ctrl, 356 .enable = s5pv210_clk_ip2_ctrl,
378 .ctrlbit = (1<<16), 357 .ctrlbit = (1<<16),
379 }, { 358 }, {
380 .name = "hsmmc", 359 .name = "hsmmc",
381 .id = 1, 360 .devname = "s3c-sdhci.1",
382 .parent = &clk_hclk_psys.clk, 361 .parent = &clk_hclk_psys.clk,
383 .enable = s5pv210_clk_ip2_ctrl, 362 .enable = s5pv210_clk_ip2_ctrl,
384 .ctrlbit = (1<<17), 363 .ctrlbit = (1<<17),
385 }, { 364 }, {
386 .name = "hsmmc", 365 .name = "hsmmc",
387 .id = 2, 366 .devname = "s3c-sdhci.2",
388 .parent = &clk_hclk_psys.clk, 367 .parent = &clk_hclk_psys.clk,
389 .enable = s5pv210_clk_ip2_ctrl, 368 .enable = s5pv210_clk_ip2_ctrl,
390 .ctrlbit = (1<<18), 369 .ctrlbit = (1<<18),
391 }, { 370 }, {
392 .name = "hsmmc", 371 .name = "hsmmc",
393 .id = 3, 372 .devname = "s3c-sdhci.3",
394 .parent = &clk_hclk_psys.clk, 373 .parent = &clk_hclk_psys.clk,
395 .enable = s5pv210_clk_ip2_ctrl, 374 .enable = s5pv210_clk_ip2_ctrl,
396 .ctrlbit = (1<<19), 375 .ctrlbit = (1<<19),
397 }, { 376 }, {
398 .name = "systimer", 377 .name = "systimer",
399 .id = -1,
400 .parent = &clk_pclk_psys.clk, 378 .parent = &clk_pclk_psys.clk,
401 .enable = s5pv210_clk_ip3_ctrl, 379 .enable = s5pv210_clk_ip3_ctrl,
402 .ctrlbit = (1<<16), 380 .ctrlbit = (1<<16),
403 }, { 381 }, {
404 .name = "watchdog", 382 .name = "watchdog",
405 .id = -1,
406 .parent = &clk_pclk_psys.clk, 383 .parent = &clk_pclk_psys.clk,
407 .enable = s5pv210_clk_ip3_ctrl, 384 .enable = s5pv210_clk_ip3_ctrl,
408 .ctrlbit = (1<<22), 385 .ctrlbit = (1<<22),
409 }, { 386 }, {
410 .name = "rtc", 387 .name = "rtc",
411 .id = -1,
412 .parent = &clk_pclk_psys.clk, 388 .parent = &clk_pclk_psys.clk,
413 .enable = s5pv210_clk_ip3_ctrl, 389 .enable = s5pv210_clk_ip3_ctrl,
414 .ctrlbit = (1<<15), 390 .ctrlbit = (1<<15),
415 }, { 391 }, {
416 .name = "i2c", 392 .name = "i2c",
417 .id = 0, 393 .devname = "s3c2440-i2c.0",
418 .parent = &clk_pclk_psys.clk, 394 .parent = &clk_pclk_psys.clk,
419 .enable = s5pv210_clk_ip3_ctrl, 395 .enable = s5pv210_clk_ip3_ctrl,
420 .ctrlbit = (1<<7), 396 .ctrlbit = (1<<7),
421 }, { 397 }, {
422 .name = "i2c", 398 .name = "i2c",
423 .id = 1, 399 .devname = "s3c2440-i2c.1",
424 .parent = &clk_pclk_psys.clk, 400 .parent = &clk_pclk_psys.clk,
425 .enable = s5pv210_clk_ip3_ctrl, 401 .enable = s5pv210_clk_ip3_ctrl,
426 .ctrlbit = (1 << 10), 402 .ctrlbit = (1 << 10),
427 }, { 403 }, {
428 .name = "i2c", 404 .name = "i2c",
429 .id = 2, 405 .devname = "s3c2440-i2c.2",
430 .parent = &clk_pclk_psys.clk, 406 .parent = &clk_pclk_psys.clk,
431 .enable = s5pv210_clk_ip3_ctrl, 407 .enable = s5pv210_clk_ip3_ctrl,
432 .ctrlbit = (1<<9), 408 .ctrlbit = (1<<9),
433 }, { 409 }, {
434 .name = "spi", 410 .name = "spi",
435 .id = 0, 411 .devname = "s3c64xx-spi.0",
436 .parent = &clk_pclk_psys.clk, 412 .parent = &clk_pclk_psys.clk,
437 .enable = s5pv210_clk_ip3_ctrl, 413 .enable = s5pv210_clk_ip3_ctrl,
438 .ctrlbit = (1<<12), 414 .ctrlbit = (1<<12),
439 }, { 415 }, {
440 .name = "spi", 416 .name = "spi",
441 .id = 1, 417 .devname = "s3c64xx-spi.1",
442 .parent = &clk_pclk_psys.clk, 418 .parent = &clk_pclk_psys.clk,
443 .enable = s5pv210_clk_ip3_ctrl, 419 .enable = s5pv210_clk_ip3_ctrl,
444 .ctrlbit = (1<<13), 420 .ctrlbit = (1<<13),
445 }, { 421 }, {
446 .name = "spi", 422 .name = "spi",
447 .id = 2, 423 .devname = "s3c64xx-spi.2",
448 .parent = &clk_pclk_psys.clk, 424 .parent = &clk_pclk_psys.clk,
449 .enable = s5pv210_clk_ip3_ctrl, 425 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1<<14), 426 .ctrlbit = (1<<14),
451 }, { 427 }, {
452 .name = "timers", 428 .name = "timers",
453 .id = -1,
454 .parent = &clk_pclk_psys.clk, 429 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl, 430 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<23), 431 .ctrlbit = (1<<23),
457 }, { 432 }, {
458 .name = "adc", 433 .name = "adc",
459 .id = -1,
460 .parent = &clk_pclk_psys.clk, 434 .parent = &clk_pclk_psys.clk,
461 .enable = s5pv210_clk_ip3_ctrl, 435 .enable = s5pv210_clk_ip3_ctrl,
462 .ctrlbit = (1<<24), 436 .ctrlbit = (1<<24),
463 }, { 437 }, {
464 .name = "keypad", 438 .name = "keypad",
465 .id = -1,
466 .parent = &clk_pclk_psys.clk, 439 .parent = &clk_pclk_psys.clk,
467 .enable = s5pv210_clk_ip3_ctrl, 440 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1<<21), 441 .ctrlbit = (1<<21),
469 }, { 442 }, {
470 .name = "iis", 443 .name = "iis",
471 .id = 0, 444 .devname = "samsung-i2s.0",
472 .parent = &clk_p, 445 .parent = &clk_p,
473 .enable = s5pv210_clk_ip3_ctrl, 446 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1<<4), 447 .ctrlbit = (1<<4),
475 }, { 448 }, {
476 .name = "iis", 449 .name = "iis",
477 .id = 1, 450 .devname = "samsung-i2s.1",
478 .parent = &clk_p, 451 .parent = &clk_p,
479 .enable = s5pv210_clk_ip3_ctrl, 452 .enable = s5pv210_clk_ip3_ctrl,
480 .ctrlbit = (1 << 5), 453 .ctrlbit = (1 << 5),
481 }, { 454 }, {
482 .name = "iis", 455 .name = "iis",
483 .id = 2, 456 .devname = "samsung-i2s.2",
484 .parent = &clk_p, 457 .parent = &clk_p,
485 .enable = s5pv210_clk_ip3_ctrl, 458 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1 << 6), 459 .ctrlbit = (1 << 6),
487 }, { 460 }, {
488 .name = "spdif", 461 .name = "spdif",
489 .id = -1,
490 .parent = &clk_p, 462 .parent = &clk_p,
491 .enable = s5pv210_clk_ip3_ctrl, 463 .enable = s5pv210_clk_ip3_ctrl,
492 .ctrlbit = (1 << 0), 464 .ctrlbit = (1 << 0),
@@ -496,38 +468,36 @@ static struct clk init_clocks_off[] = {
496static struct clk init_clocks[] = { 468static struct clk init_clocks[] = {
497 { 469 {
498 .name = "hclk_imem", 470 .name = "hclk_imem",
499 .id = -1,
500 .parent = &clk_hclk_msys.clk, 471 .parent = &clk_hclk_msys.clk,
501 .ctrlbit = (1 << 5), 472 .ctrlbit = (1 << 5),
502 .enable = s5pv210_clk_ip0_ctrl, 473 .enable = s5pv210_clk_ip0_ctrl,
503 .ops = &clk_hclk_imem_ops, 474 .ops = &clk_hclk_imem_ops,
504 }, { 475 }, {
505 .name = "uart", 476 .name = "uart",
506 .id = 0, 477 .devname = "s5pv210-uart.0",
507 .parent = &clk_pclk_psys.clk, 478 .parent = &clk_pclk_psys.clk,
508 .enable = s5pv210_clk_ip3_ctrl, 479 .enable = s5pv210_clk_ip3_ctrl,
509 .ctrlbit = (1 << 17), 480 .ctrlbit = (1 << 17),
510 }, { 481 }, {
511 .name = "uart", 482 .name = "uart",
512 .id = 1, 483 .devname = "s5pv210-uart.1",
513 .parent = &clk_pclk_psys.clk, 484 .parent = &clk_pclk_psys.clk,
514 .enable = s5pv210_clk_ip3_ctrl, 485 .enable = s5pv210_clk_ip3_ctrl,
515 .ctrlbit = (1 << 18), 486 .ctrlbit = (1 << 18),
516 }, { 487 }, {
517 .name = "uart", 488 .name = "uart",
518 .id = 2, 489 .devname = "s5pv210-uart.2",
519 .parent = &clk_pclk_psys.clk, 490 .parent = &clk_pclk_psys.clk,
520 .enable = s5pv210_clk_ip3_ctrl, 491 .enable = s5pv210_clk_ip3_ctrl,
521 .ctrlbit = (1 << 19), 492 .ctrlbit = (1 << 19),
522 }, { 493 }, {
523 .name = "uart", 494 .name = "uart",
524 .id = 3, 495 .devname = "s5pv210-uart.3",
525 .parent = &clk_pclk_psys.clk, 496 .parent = &clk_pclk_psys.clk,
526 .enable = s5pv210_clk_ip3_ctrl, 497 .enable = s5pv210_clk_ip3_ctrl,
527 .ctrlbit = (1 << 20), 498 .ctrlbit = (1 << 20),
528 }, { 499 }, {
529 .name = "sromc", 500 .name = "sromc",
530 .id = -1,
531 .parent = &clk_hclk_psys.clk, 501 .parent = &clk_hclk_psys.clk,
532 .enable = s5pv210_clk_ip1_ctrl, 502 .enable = s5pv210_clk_ip1_ctrl,
533 .ctrlbit = (1 << 26), 503 .ctrlbit = (1 << 26),
@@ -579,7 +549,6 @@ static struct clksrc_sources clkset_sclk_dac = {
579static struct clksrc_clk clk_sclk_dac = { 549static struct clksrc_clk clk_sclk_dac = {
580 .clk = { 550 .clk = {
581 .name = "sclk_dac", 551 .name = "sclk_dac",
582 .id = -1,
583 .enable = s5pv210_clk_mask0_ctrl, 552 .enable = s5pv210_clk_mask0_ctrl,
584 .ctrlbit = (1 << 2), 553 .ctrlbit = (1 << 2),
585 }, 554 },
@@ -590,7 +559,6 @@ static struct clksrc_clk clk_sclk_dac = {
590static struct clksrc_clk clk_sclk_pixel = { 559static struct clksrc_clk clk_sclk_pixel = {
591 .clk = { 560 .clk = {
592 .name = "sclk_pixel", 561 .name = "sclk_pixel",
593 .id = -1,
594 .parent = &clk_sclk_vpll.clk, 562 .parent = &clk_sclk_vpll.clk,
595 }, 563 },
596 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, 564 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@@ -609,7 +577,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
609static struct clksrc_clk clk_sclk_hdmi = { 577static struct clksrc_clk clk_sclk_hdmi = {
610 .clk = { 578 .clk = {
611 .name = "sclk_hdmi", 579 .name = "sclk_hdmi",
612 .id = -1,
613 .enable = s5pv210_clk_mask0_ctrl, 580 .enable = s5pv210_clk_mask0_ctrl,
614 .ctrlbit = (1 << 0), 581 .ctrlbit = (1 << 0),
615 }, 582 },
@@ -647,7 +614,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
647static struct clksrc_clk clk_sclk_audio0 = { 614static struct clksrc_clk clk_sclk_audio0 = {
648 .clk = { 615 .clk = {
649 .name = "sclk_audio", 616 .name = "sclk_audio",
650 .id = 0, 617 .devname = "soc-audio.0",
651 .enable = s5pv210_clk_mask0_ctrl, 618 .enable = s5pv210_clk_mask0_ctrl,
652 .ctrlbit = (1 << 24), 619 .ctrlbit = (1 << 24),
653 }, 620 },
@@ -676,7 +643,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
676static struct clksrc_clk clk_sclk_audio1 = { 643static struct clksrc_clk clk_sclk_audio1 = {
677 .clk = { 644 .clk = {
678 .name = "sclk_audio", 645 .name = "sclk_audio",
679 .id = 1, 646 .devname = "soc-audio.1",
680 .enable = s5pv210_clk_mask0_ctrl, 647 .enable = s5pv210_clk_mask0_ctrl,
681 .ctrlbit = (1 << 25), 648 .ctrlbit = (1 << 25),
682 }, 649 },
@@ -705,7 +672,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
705static struct clksrc_clk clk_sclk_audio2 = { 672static struct clksrc_clk clk_sclk_audio2 = {
706 .clk = { 673 .clk = {
707 .name = "sclk_audio", 674 .name = "sclk_audio",
708 .id = 2, 675 .devname = "soc-audio.2",
709 .enable = s5pv210_clk_mask0_ctrl, 676 .enable = s5pv210_clk_mask0_ctrl,
710 .ctrlbit = (1 << 26), 677 .ctrlbit = (1 << 26),
711 }, 678 },
@@ -725,48 +692,12 @@ static struct clksrc_sources clkset_sclk_spdif = {
725 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), 692 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
726}; 693};
727 694
728static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
729{
730 struct clk *pclk;
731 int ret;
732
733 pclk = clk_get_parent(clk);
734 if (IS_ERR(pclk))
735 return -EINVAL;
736
737 ret = pclk->ops->set_rate(pclk, rate);
738 clk_put(pclk);
739
740 return ret;
741}
742
743static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
744{
745 struct clk *pclk;
746 int rate;
747
748 pclk = clk_get_parent(clk);
749 if (IS_ERR(pclk))
750 return -EINVAL;
751
752 rate = pclk->ops->get_rate(clk);
753 clk_put(pclk);
754
755 return rate;
756}
757
758static struct clk_ops s5pv210_sclk_spdif_ops = {
759 .set_rate = s5pv210_spdif_set_rate,
760 .get_rate = s5pv210_spdif_get_rate,
761};
762
763static struct clksrc_clk clk_sclk_spdif = { 695static struct clksrc_clk clk_sclk_spdif = {
764 .clk = { 696 .clk = {
765 .name = "sclk_spdif", 697 .name = "sclk_spdif",
766 .id = -1,
767 .enable = s5pv210_clk_mask0_ctrl, 698 .enable = s5pv210_clk_mask0_ctrl,
768 .ctrlbit = (1 << 27), 699 .ctrlbit = (1 << 27),
769 .ops = &s5pv210_sclk_spdif_ops, 700 .ops = &s5p_sclk_spdif_ops,
770 }, 701 },
771 .sources = &clkset_sclk_spdif, 702 .sources = &clkset_sclk_spdif,
772 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, 703 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
@@ -793,7 +724,6 @@ static struct clksrc_clk clksrcs[] = {
793 { 724 {
794 .clk = { 725 .clk = {
795 .name = "sclk_dmc", 726 .name = "sclk_dmc",
796 .id = -1,
797 }, 727 },
798 .sources = &clkset_group1, 728 .sources = &clkset_group1,
799 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 729 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -801,7 +731,6 @@ static struct clksrc_clk clksrcs[] = {
801 }, { 731 }, {
802 .clk = { 732 .clk = {
803 .name = "sclk_onenand", 733 .name = "sclk_onenand",
804 .id = -1,
805 }, 734 },
806 .sources = &clkset_sclk_onenand, 735 .sources = &clkset_sclk_onenand,
807 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, 736 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@@ -809,7 +738,7 @@ static struct clksrc_clk clksrcs[] = {
809 }, { 738 }, {
810 .clk = { 739 .clk = {
811 .name = "uclk1", 740 .name = "uclk1",
812 .id = 0, 741 .devname = "s5pv210-uart.0",
813 .enable = s5pv210_clk_mask0_ctrl, 742 .enable = s5pv210_clk_mask0_ctrl,
814 .ctrlbit = (1 << 12), 743 .ctrlbit = (1 << 12),
815 }, 744 },
@@ -819,7 +748,7 @@ static struct clksrc_clk clksrcs[] = {
819 }, { 748 }, {
820 .clk = { 749 .clk = {
821 .name = "uclk1", 750 .name = "uclk1",
822 .id = 1, 751 .devname = "s5pv210-uart.1",
823 .enable = s5pv210_clk_mask0_ctrl, 752 .enable = s5pv210_clk_mask0_ctrl,
824 .ctrlbit = (1 << 13), 753 .ctrlbit = (1 << 13),
825 }, 754 },
@@ -829,7 +758,7 @@ static struct clksrc_clk clksrcs[] = {
829 }, { 758 }, {
830 .clk = { 759 .clk = {
831 .name = "uclk1", 760 .name = "uclk1",
832 .id = 2, 761 .devname = "s5pv210-uart.2",
833 .enable = s5pv210_clk_mask0_ctrl, 762 .enable = s5pv210_clk_mask0_ctrl,
834 .ctrlbit = (1 << 14), 763 .ctrlbit = (1 << 14),
835 }, 764 },
@@ -839,7 +768,7 @@ static struct clksrc_clk clksrcs[] = {
839 }, { 768 }, {
840 .clk = { 769 .clk = {
841 .name = "uclk1", 770 .name = "uclk1",
842 .id = 3, 771 .devname = "s5pv210-uart.3",
843 .enable = s5pv210_clk_mask0_ctrl, 772 .enable = s5pv210_clk_mask0_ctrl,
844 .ctrlbit = (1 << 15), 773 .ctrlbit = (1 << 15),
845 }, 774 },
@@ -849,7 +778,6 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 778 }, {
850 .clk = { 779 .clk = {
851 .name = "sclk_mixer", 780 .name = "sclk_mixer",
852 .id = -1,
853 .enable = s5pv210_clk_mask0_ctrl, 781 .enable = s5pv210_clk_mask0_ctrl,
854 .ctrlbit = (1 << 1), 782 .ctrlbit = (1 << 1),
855 }, 783 },
@@ -858,7 +786,7 @@ static struct clksrc_clk clksrcs[] = {
858 }, { 786 }, {
859 .clk = { 787 .clk = {
860 .name = "sclk_fimc", 788 .name = "sclk_fimc",
861 .id = 0, 789 .devname = "s5pv210-fimc.0",
862 .enable = s5pv210_clk_mask1_ctrl, 790 .enable = s5pv210_clk_mask1_ctrl,
863 .ctrlbit = (1 << 2), 791 .ctrlbit = (1 << 2),
864 }, 792 },
@@ -868,7 +796,7 @@ static struct clksrc_clk clksrcs[] = {
868 }, { 796 }, {
869 .clk = { 797 .clk = {
870 .name = "sclk_fimc", 798 .name = "sclk_fimc",
871 .id = 1, 799 .devname = "s5pv210-fimc.1",
872 .enable = s5pv210_clk_mask1_ctrl, 800 .enable = s5pv210_clk_mask1_ctrl,
873 .ctrlbit = (1 << 3), 801 .ctrlbit = (1 << 3),
874 }, 802 },
@@ -878,7 +806,7 @@ static struct clksrc_clk clksrcs[] = {
878 }, { 806 }, {
879 .clk = { 807 .clk = {
880 .name = "sclk_fimc", 808 .name = "sclk_fimc",
881 .id = 2, 809 .devname = "s5pv210-fimc.2",
882 .enable = s5pv210_clk_mask1_ctrl, 810 .enable = s5pv210_clk_mask1_ctrl,
883 .ctrlbit = (1 << 4), 811 .ctrlbit = (1 << 4),
884 }, 812 },
@@ -888,7 +816,7 @@ static struct clksrc_clk clksrcs[] = {
888 }, { 816 }, {
889 .clk = { 817 .clk = {
890 .name = "sclk_cam", 818 .name = "sclk_cam",
891 .id = 0, 819 .devname = "s5pv210-fimc.0",
892 .enable = s5pv210_clk_mask0_ctrl, 820 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 3), 821 .ctrlbit = (1 << 3),
894 }, 822 },
@@ -898,7 +826,7 @@ static struct clksrc_clk clksrcs[] = {
898 }, { 826 }, {
899 .clk = { 827 .clk = {
900 .name = "sclk_cam", 828 .name = "sclk_cam",
901 .id = 1, 829 .devname = "s5pv210-fimc.1",
902 .enable = s5pv210_clk_mask0_ctrl, 830 .enable = s5pv210_clk_mask0_ctrl,
903 .ctrlbit = (1 << 4), 831 .ctrlbit = (1 << 4),
904 }, 832 },
@@ -908,7 +836,6 @@ static struct clksrc_clk clksrcs[] = {
908 }, { 836 }, {
909 .clk = { 837 .clk = {
910 .name = "sclk_fimd", 838 .name = "sclk_fimd",
911 .id = -1,
912 .enable = s5pv210_clk_mask0_ctrl, 839 .enable = s5pv210_clk_mask0_ctrl,
913 .ctrlbit = (1 << 5), 840 .ctrlbit = (1 << 5),
914 }, 841 },
@@ -918,7 +845,7 @@ static struct clksrc_clk clksrcs[] = {
918 }, { 845 }, {
919 .clk = { 846 .clk = {
920 .name = "sclk_mmc", 847 .name = "sclk_mmc",
921 .id = 0, 848 .devname = "s3c-sdhci.0",
922 .enable = s5pv210_clk_mask0_ctrl, 849 .enable = s5pv210_clk_mask0_ctrl,
923 .ctrlbit = (1 << 8), 850 .ctrlbit = (1 << 8),
924 }, 851 },
@@ -928,7 +855,7 @@ static struct clksrc_clk clksrcs[] = {
928 }, { 855 }, {
929 .clk = { 856 .clk = {
930 .name = "sclk_mmc", 857 .name = "sclk_mmc",
931 .id = 1, 858 .devname = "s3c-sdhci.1",
932 .enable = s5pv210_clk_mask0_ctrl, 859 .enable = s5pv210_clk_mask0_ctrl,
933 .ctrlbit = (1 << 9), 860 .ctrlbit = (1 << 9),
934 }, 861 },
@@ -938,7 +865,7 @@ static struct clksrc_clk clksrcs[] = {
938 }, { 865 }, {
939 .clk = { 866 .clk = {
940 .name = "sclk_mmc", 867 .name = "sclk_mmc",
941 .id = 2, 868 .devname = "s3c-sdhci.2",
942 .enable = s5pv210_clk_mask0_ctrl, 869 .enable = s5pv210_clk_mask0_ctrl,
943 .ctrlbit = (1 << 10), 870 .ctrlbit = (1 << 10),
944 }, 871 },
@@ -948,7 +875,7 @@ static struct clksrc_clk clksrcs[] = {
948 }, { 875 }, {
949 .clk = { 876 .clk = {
950 .name = "sclk_mmc", 877 .name = "sclk_mmc",
951 .id = 3, 878 .devname = "s3c-sdhci.3",
952 .enable = s5pv210_clk_mask0_ctrl, 879 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 11), 880 .ctrlbit = (1 << 11),
954 }, 881 },
@@ -958,7 +885,7 @@ static struct clksrc_clk clksrcs[] = {
958 }, { 885 }, {
959 .clk = { 886 .clk = {
960 .name = "sclk_mfc", 887 .name = "sclk_mfc",
961 .id = -1, 888 .devname = "s5p-mfc",
962 .enable = s5pv210_clk_ip0_ctrl, 889 .enable = s5pv210_clk_ip0_ctrl,
963 .ctrlbit = (1 << 16), 890 .ctrlbit = (1 << 16),
964 }, 891 },
@@ -968,7 +895,6 @@ static struct clksrc_clk clksrcs[] = {
968 }, { 895 }, {
969 .clk = { 896 .clk = {
970 .name = "sclk_g2d", 897 .name = "sclk_g2d",
971 .id = -1,
972 .enable = s5pv210_clk_ip0_ctrl, 898 .enable = s5pv210_clk_ip0_ctrl,
973 .ctrlbit = (1 << 12), 899 .ctrlbit = (1 << 12),
974 }, 900 },
@@ -978,7 +904,6 @@ static struct clksrc_clk clksrcs[] = {
978 }, { 904 }, {
979 .clk = { 905 .clk = {
980 .name = "sclk_g3d", 906 .name = "sclk_g3d",
981 .id = -1,
982 .enable = s5pv210_clk_ip0_ctrl, 907 .enable = s5pv210_clk_ip0_ctrl,
983 .ctrlbit = (1 << 8), 908 .ctrlbit = (1 << 8),
984 }, 909 },
@@ -988,7 +913,6 @@ static struct clksrc_clk clksrcs[] = {
988 }, { 913 }, {
989 .clk = { 914 .clk = {
990 .name = "sclk_csis", 915 .name = "sclk_csis",
991 .id = -1,
992 .enable = s5pv210_clk_mask0_ctrl, 916 .enable = s5pv210_clk_mask0_ctrl,
993 .ctrlbit = (1 << 6), 917 .ctrlbit = (1 << 6),
994 }, 918 },
@@ -998,7 +922,7 @@ static struct clksrc_clk clksrcs[] = {
998 }, { 922 }, {
999 .clk = { 923 .clk = {
1000 .name = "sclk_spi", 924 .name = "sclk_spi",
1001 .id = 0, 925 .devname = "s3c64xx-spi.0",
1002 .enable = s5pv210_clk_mask0_ctrl, 926 .enable = s5pv210_clk_mask0_ctrl,
1003 .ctrlbit = (1 << 16), 927 .ctrlbit = (1 << 16),
1004 }, 928 },
@@ -1008,7 +932,7 @@ static struct clksrc_clk clksrcs[] = {
1008 }, { 932 }, {
1009 .clk = { 933 .clk = {
1010 .name = "sclk_spi", 934 .name = "sclk_spi",
1011 .id = 1, 935 .devname = "s3c64xx-spi.1",
1012 .enable = s5pv210_clk_mask0_ctrl, 936 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 17), 937 .ctrlbit = (1 << 17),
1014 }, 938 },
@@ -1018,7 +942,6 @@ static struct clksrc_clk clksrcs[] = {
1018 }, { 942 }, {
1019 .clk = { 943 .clk = {
1020 .name = "sclk_pwi", 944 .name = "sclk_pwi",
1021 .id = -1,
1022 .enable = s5pv210_clk_mask0_ctrl, 945 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 29), 946 .ctrlbit = (1 << 29),
1024 }, 947 },
@@ -1028,7 +951,6 @@ static struct clksrc_clk clksrcs[] = {
1028 }, { 951 }, {
1029 .clk = { 952 .clk = {
1030 .name = "sclk_pwm", 953 .name = "sclk_pwm",
1031 .id = -1,
1032 .enable = s5pv210_clk_mask0_ctrl, 954 .enable = s5pv210_clk_mask0_ctrl,
1033 .ctrlbit = (1 << 19), 955 .ctrlbit = (1 << 19),
1034 }, 956 },
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 61e6c24b90ac..79907ec78d43 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
126 s5pv210_default_sdhci2(); 126 s5pv210_default_sdhci2();
127 s5pv210_default_sdhci3(); 127 s5pv210_default_sdhci3();
128 128
129 s3c_adc_setname("s3c64xx-adc"); 129 s3c_adc_setname("samsung-adc-v3");
130 130
131 s3c_cfcon_setname("s5pv210-pata"); 131 s3c_cfcon_setname("s5pv210-pata");
132 132
diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c
deleted file mode 100644
index 153af8b359ec..000000000000
--- a/arch/arm/mach-s5pv210/cpufreq.c
+++ /dev/null
@@ -1,485 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/cpufreq.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * CPU frequency scaling for S5PC110/S5PV210
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/cpufreq.h>
20
21#include <mach/map.h>
22#include <mach/regs-clock.h>
23
24static struct clk *cpu_clk;
25static struct clk *dmc0_clk;
26static struct clk *dmc1_clk;
27static struct cpufreq_freqs freqs;
28
29/* APLL M,P,S values for 1G/800Mhz */
30#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
31#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
32
33/*
34 * DRAM configurations to calculate refresh counter for changing
35 * frequency of memory.
36 */
37struct dram_conf {
38 unsigned long freq; /* HZ */
39 unsigned long refresh; /* DRAM refresh counter * 1000 */
40};
41
42/* DRAM configuration (DMC0 and DMC1) */
43static struct dram_conf s5pv210_dram_conf[2];
44
45enum perf_level {
46 L0, L1, L2, L3, L4,
47};
48
49enum s5pv210_mem_type {
50 LPDDR = 0x1,
51 LPDDR2 = 0x2,
52 DDR2 = 0x4,
53};
54
55enum s5pv210_dmc_port {
56 DMC0 = 0,
57 DMC1,
58};
59
60static struct cpufreq_frequency_table s5pv210_freq_table[] = {
61 {L0, 1000*1000},
62 {L1, 800*1000},
63 {L2, 400*1000},
64 {L3, 200*1000},
65 {L4, 100*1000},
66 {0, CPUFREQ_TABLE_END},
67};
68
69static u32 clkdiv_val[5][11] = {
70 /*
71 * Clock divider value for following
72 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
73 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
74 * ONEDRAM, MFC, G3D }
75 */
76
77 /* L0 : [1000/200/100][166/83][133/66][200/200] */
78 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
79
80 /* L1 : [800/200/100][166/83][133/66][200/200] */
81 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
82
83 /* L2 : [400/200/100][166/83][133/66][200/200] */
84 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
85
86 /* L3 : [200/200/100][166/83][133/66][200/200] */
87 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
88
89 /* L4 : [100/100/100][83/83][66/66][100/100] */
90 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
91};
92
93/*
94 * This function set DRAM refresh counter
95 * accoriding to operating frequency of DRAM
96 * ch: DMC port number 0 or 1
97 * freq: Operating frequency of DRAM(KHz)
98 */
99static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
100{
101 unsigned long tmp, tmp1;
102 void __iomem *reg = NULL;
103
104 if (ch == DMC0) {
105 reg = (S5P_VA_DMC0 + 0x30);
106 } else if (ch == DMC1) {
107 reg = (S5P_VA_DMC1 + 0x30);
108 } else {
109 printk(KERN_ERR "Cannot find DMC port\n");
110 return;
111 }
112
113 /* Find current DRAM frequency */
114 tmp = s5pv210_dram_conf[ch].freq;
115
116 do_div(tmp, freq);
117
118 tmp1 = s5pv210_dram_conf[ch].refresh;
119
120 do_div(tmp1, tmp);
121
122 __raw_writel(tmp1, reg);
123}
124
125int s5pv210_verify_speed(struct cpufreq_policy *policy)
126{
127 if (policy->cpu)
128 return -EINVAL;
129
130 return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
131}
132
133unsigned int s5pv210_getspeed(unsigned int cpu)
134{
135 if (cpu)
136 return 0;
137
138 return clk_get_rate(cpu_clk) / 1000;
139}
140
141static int s5pv210_target(struct cpufreq_policy *policy,
142 unsigned int target_freq,
143 unsigned int relation)
144{
145 unsigned long reg;
146 unsigned int index, priv_index;
147 unsigned int pll_changing = 0;
148 unsigned int bus_speed_changing = 0;
149
150 freqs.old = s5pv210_getspeed(0);
151
152 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
153 target_freq, relation, &index))
154 return -EINVAL;
155
156 freqs.new = s5pv210_freq_table[index].frequency;
157 freqs.cpu = 0;
158
159 if (freqs.new == freqs.old)
160 return 0;
161
162 /* Finding current running level index */
163 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
164 freqs.old, relation, &priv_index))
165 return -EINVAL;
166
167 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
168
169 if (freqs.new > freqs.old) {
170 /* Voltage up: will be implemented */
171 }
172
173 /* Check if there need to change PLL */
174 if ((index == L0) || (priv_index == L0))
175 pll_changing = 1;
176
177 /* Check if there need to change System bus clock */
178 if ((index == L4) || (priv_index == L4))
179 bus_speed_changing = 1;
180
181 if (bus_speed_changing) {
182 /*
183 * Reconfigure DRAM refresh counter value for minimum
184 * temporary clock while changing divider.
185 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
186 */
187 if (pll_changing)
188 s5pv210_set_refresh(DMC1, 83000);
189 else
190 s5pv210_set_refresh(DMC1, 100000);
191
192 s5pv210_set_refresh(DMC0, 83000);
193 }
194
195 /*
196 * APLL should be changed in this level
197 * APLL -> MPLL(for stable transition) -> APLL
198 * Some clock source's clock API are not prepared.
199 * Do not use clock API in below code.
200 */
201 if (pll_changing) {
202 /*
203 * 1. Temporary Change divider for MFC and G3D
204 * SCLKA2M(200/1=200)->(200/4=50)Mhz
205 */
206 reg = __raw_readl(S5P_CLK_DIV2);
207 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
208 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
209 (3 << S5P_CLKDIV2_MFC_SHIFT);
210 __raw_writel(reg, S5P_CLK_DIV2);
211
212 /* For MFC, G3D dividing */
213 do {
214 reg = __raw_readl(S5P_CLKDIV_STAT0);
215 } while (reg & ((1 << 16) | (1 << 17)));
216
217 /*
218 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
219 * (200/4=50)->(667/4=166)Mhz
220 */
221 reg = __raw_readl(S5P_CLK_SRC2);
222 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
223 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
224 (1 << S5P_CLKSRC2_MFC_SHIFT);
225 __raw_writel(reg, S5P_CLK_SRC2);
226
227 do {
228 reg = __raw_readl(S5P_CLKMUX_STAT1);
229 } while (reg & ((1 << 7) | (1 << 3)));
230
231 /*
232 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
233 * true refresh counter is already programed in upper
234 * code. 0x287@83Mhz
235 */
236 if (!bus_speed_changing)
237 s5pv210_set_refresh(DMC1, 133000);
238
239 /* 4. SCLKAPLL -> SCLKMPLL */
240 reg = __raw_readl(S5P_CLK_SRC0);
241 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
242 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
243 __raw_writel(reg, S5P_CLK_SRC0);
244
245 do {
246 reg = __raw_readl(S5P_CLKMUX_STAT0);
247 } while (reg & (0x1 << 18));
248
249 }
250
251 /* Change divider */
252 reg = __raw_readl(S5P_CLK_DIV0);
253
254 reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
255 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
256 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
257 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
258
259 reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
260 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
261 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
262 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
263 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
264 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
265 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
266 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
267
268 __raw_writel(reg, S5P_CLK_DIV0);
269
270 do {
271 reg = __raw_readl(S5P_CLKDIV_STAT0);
272 } while (reg & 0xff);
273
274 /* ARM MCS value changed */
275 reg = __raw_readl(S5P_ARM_MCS_CON);
276 reg &= ~0x3;
277 if (index >= L3)
278 reg |= 0x3;
279 else
280 reg |= 0x1;
281
282 __raw_writel(reg, S5P_ARM_MCS_CON);
283
284 if (pll_changing) {
285 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
286 __raw_writel(0x2cf, S5P_APLL_LOCK);
287
288 /*
289 * 6. Turn on APLL
290 * 6-1. Set PMS values
291 * 6-2. Wait untile the PLL is locked
292 */
293 if (index == L0)
294 __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
295 else
296 __raw_writel(APLL_VAL_800, S5P_APLL_CON);
297
298 do {
299 reg = __raw_readl(S5P_APLL_CON);
300 } while (!(reg & (0x1 << 29)));
301
302 /*
303 * 7. Change souce clock from SCLKMPLL(667Mhz)
304 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
305 * (667/4=166)->(200/4=50)Mhz
306 */
307 reg = __raw_readl(S5P_CLK_SRC2);
308 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
309 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
310 (0 << S5P_CLKSRC2_MFC_SHIFT);
311 __raw_writel(reg, S5P_CLK_SRC2);
312
313 do {
314 reg = __raw_readl(S5P_CLKMUX_STAT1);
315 } while (reg & ((1 << 7) | (1 << 3)));
316
317 /*
318 * 8. Change divider for MFC and G3D
319 * (200/4=50)->(200/1=200)Mhz
320 */
321 reg = __raw_readl(S5P_CLK_DIV2);
322 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
323 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
324 (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
325 __raw_writel(reg, S5P_CLK_DIV2);
326
327 /* For MFC, G3D dividing */
328 do {
329 reg = __raw_readl(S5P_CLKDIV_STAT0);
330 } while (reg & ((1 << 16) | (1 << 17)));
331
332 /* 9. Change MPLL to APLL in MSYS_MUX */
333 reg = __raw_readl(S5P_CLK_SRC0);
334 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
335 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
336 __raw_writel(reg, S5P_CLK_SRC0);
337
338 do {
339 reg = __raw_readl(S5P_CLKMUX_STAT0);
340 } while (reg & (0x1 << 18));
341
342 /*
343 * 10. DMC1 refresh counter
344 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
345 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
346 */
347 if (!bus_speed_changing)
348 s5pv210_set_refresh(DMC1, 200000);
349 }
350
351 /*
352 * L4 level need to change memory bus speed, hence onedram clock divier
353 * and memory refresh parameter should be changed
354 */
355 if (bus_speed_changing) {
356 reg = __raw_readl(S5P_CLK_DIV6);
357 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
358 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
359 __raw_writel(reg, S5P_CLK_DIV6);
360
361 do {
362 reg = __raw_readl(S5P_CLKDIV_STAT1);
363 } while (reg & (1 << 15));
364
365 /* Reconfigure DRAM refresh counter value */
366 if (index != L4) {
367 /*
368 * DMC0 : 166Mhz
369 * DMC1 : 200Mhz
370 */
371 s5pv210_set_refresh(DMC0, 166000);
372 s5pv210_set_refresh(DMC1, 200000);
373 } else {
374 /*
375 * DMC0 : 83Mhz
376 * DMC1 : 100Mhz
377 */
378 s5pv210_set_refresh(DMC0, 83000);
379 s5pv210_set_refresh(DMC1, 100000);
380 }
381 }
382
383 if (freqs.new < freqs.old) {
384 /* Voltage down: will be implemented */
385 }
386
387 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
388
389 printk(KERN_DEBUG "Perf changed[L%d]\n", index);
390
391 return 0;
392}
393
394#ifdef CONFIG_PM
395static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
396{
397 return 0;
398}
399
400static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
401{
402 return 0;
403}
404#endif
405
406static int check_mem_type(void __iomem *dmc_reg)
407{
408 unsigned long val;
409
410 val = __raw_readl(dmc_reg + 0x4);
411 val = (val & (0xf << 8));
412
413 return val >> 8;
414}
415
416static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
417{
418 unsigned long mem_type;
419
420 cpu_clk = clk_get(NULL, "armclk");
421 if (IS_ERR(cpu_clk))
422 return PTR_ERR(cpu_clk);
423
424 dmc0_clk = clk_get(NULL, "sclk_dmc0");
425 if (IS_ERR(dmc0_clk)) {
426 clk_put(cpu_clk);
427 return PTR_ERR(dmc0_clk);
428 }
429
430 dmc1_clk = clk_get(NULL, "hclk_msys");
431 if (IS_ERR(dmc1_clk)) {
432 clk_put(dmc0_clk);
433 clk_put(cpu_clk);
434 return PTR_ERR(dmc1_clk);
435 }
436
437 if (policy->cpu != 0)
438 return -EINVAL;
439
440 /*
441 * check_mem_type : This driver only support LPDDR & LPDDR2.
442 * other memory type is not supported.
443 */
444 mem_type = check_mem_type(S5P_VA_DMC0);
445
446 if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
447 printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
448 return -EINVAL;
449 }
450
451 /* Find current refresh counter and frequency each DMC */
452 s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
453 s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
454
455 s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
456 s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
457
458 policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
459
460 cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
461
462 policy->cpuinfo.transition_latency = 40000;
463
464 return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
465}
466
467static struct cpufreq_driver s5pv210_driver = {
468 .flags = CPUFREQ_STICKY,
469 .verify = s5pv210_verify_speed,
470 .target = s5pv210_target,
471 .get = s5pv210_getspeed,
472 .init = s5pv210_cpu_init,
473 .name = "s5pv210",
474#ifdef CONFIG_PM
475 .suspend = s5pv210_cpufreq_suspend,
476 .resume = s5pv210_cpufreq_resume,
477#endif
478};
479
480static int __init s5pv210_cpufreq_init(void)
481{
482 return cpufreq_register_driver(&s5pv210_driver);
483}
484
485late_initcall(s5pv210_cpufreq_init);
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 8d58f1926241..63f5d82004b5 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -18,6 +18,7 @@
18#include <mach/map.h> 18#include <mach/map.h>
19#include <mach/dma.h> 19#include <mach/dma.h>
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21#include <mach/regs-audss.h>
21 22
22static const char *rclksrc[] = { 23static const char *rclksrc[] = {
23 [0] = "busclk", 24 [0] = "busclk",
@@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI 53 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
53 | QUIRK_NEED_RSTCLR, 54 | QUIRK_NEED_RSTCLR,
54 .src_clk = rclksrc, 55 .src_clk = rclksrc,
56 .idma_addr = S5PV210_AUDSS_INT_MEM,
55 }, 57 },
56 }, 58 },
57}; 59};
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 1dd58836fd4f..aac343c180b2 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -59,6 +59,8 @@
59 59
60#define S5PV210_PA_CFCON 0xE8200000 60#define S5PV210_PA_CFCON 0xE8200000
61 61
62#define S5PV210_PA_MFC 0xF1700000
63
62#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 64#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
63 65
64#define S5PV210_PA_HSOTG 0xEC000000 66#define S5PV210_PA_HSOTG 0xEC000000
@@ -107,6 +109,7 @@
107#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 109#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
108#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 110#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
109#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS 111#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
112#define S5P_PA_MFC S5PV210_PA_MFC
110#define S5P_PA_ONENAND S5PC110_PA_ONENAND 113#define S5P_PA_ONENAND S5PC110_PA_ONENAND
111#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 114#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
112#define S5P_PA_SDRAM S5PV210_PA_SDRAM 115#define S5P_PA_SDRAM S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
index e8d394f8b057..3e22109e1b7b 100644
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
41{ 41{
42 /* nothing here yet */ 42 /* nothing here yet */
43} 43}
44
45static inline void s3c_pm_restored_gpios(void) { }
46static inline void s3c_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
new file mode 100644
index 000000000000..eacc1f790807
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
2 *
3 * Copyright (c) 2011 Samsung Electronics
4 * http://www.samsung.com
5 *
6 * S5PV210 Audio SubSystem clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_AUDSS_H
14#define __PLAT_REGS_AUDSS_H __FILE__
15
16#define S5PV210_AUDSS_INT_MEM (0xC0000000)
17
18#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h
deleted file mode 100644
index 60d992989bdc..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
3 *
4 * Dummy framebuffer to allow build for the moment.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __ASM_ARCH_MACH_REGS_FB_H
12#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
13
14#include <plat/regs-fb-v4.h>
15
16static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
17{
18 return 0x2400 + (window * 256 *4 ) + reg;
19}
20
21#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 4e1d8ff5ae59..509627f25111 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -29,7 +29,6 @@
29 29
30#include <mach/map.h> 30#include <mach/map.h>
31#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
32#include <mach/regs-fb.h>
33 32
34#include <plat/gpio-cfg.h> 33#include <plat/gpio-cfg.h>
35#include <plat/regs-serial.h> 34#include <plat/regs-serial.h>
@@ -40,6 +39,7 @@
40#include <plat/fimc-core.h> 39#include <plat/fimc-core.h>
41#include <plat/sdhci.h> 40#include <plat/sdhci.h>
42#include <plat/s5p-time.h> 41#include <plat/s5p-time.h>
42#include <plat/regs-fb-v4.h>
43 43
44/* Following are default values for UCON, ULCON and UFCON UART registers */ 44/* Following are default values for UCON, ULCON and UFCON UART registers */
45#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 45#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 31d5aa769753..85c2d51a0956 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -34,7 +34,6 @@
34 34
35#include <mach/map.h> 35#include <mach/map.h>
36#include <mach/regs-clock.h> 36#include <mach/regs-clock.h>
37#include <mach/regs-fb.h>
38 37
39#include <plat/gpio-cfg.h> 38#include <plat/gpio-cfg.h>
40#include <plat/regs-serial.h> 39#include <plat/regs-serial.h>
@@ -47,6 +46,8 @@
47#include <plat/sdhci.h> 46#include <plat/sdhci.h>
48#include <plat/clock.h> 47#include <plat/clock.h>
49#include <plat/s5p-time.h> 48#include <plat/s5p-time.h>
49#include <plat/mfc.h>
50#include <plat/regs-fb-v4.h>
50 51
51/* Following are default values for UCON, ULCON and UFCON UART registers */ 52/* Following are default values for UCON, ULCON and UFCON UART registers */
52#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 53#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -808,6 +809,9 @@ static struct platform_device *goni_devices[] __initdata = {
808 &goni_i2c_gpio5, 809 &goni_i2c_gpio5,
809 &mmc2_fixed_voltage, 810 &mmc2_fixed_voltage,
810 &goni_device_gpiokeys, 811 &goni_device_gpiokeys,
812 &s5p_device_mfc,
813 &s5p_device_mfc_l,
814 &s5p_device_mfc_r,
811 &s3c_device_i2c0, 815 &s3c_device_i2c0,
812 &s5p_device_fimc0, 816 &s5p_device_fimc0,
813 &s5p_device_fimc1, 817 &s5p_device_fimc1,
@@ -841,6 +845,11 @@ static void __init goni_map_io(void)
841 s5p_set_timer_source(S5P_PWM3, S5P_PWM4); 845 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
842} 846}
843 847
848static void __init goni_reserve(void)
849{
850 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
851}
852
844static void __init goni_machine_init(void) 853static void __init goni_machine_init(void)
845{ 854{
846 /* Radio: call before I2C 1 registeration */ 855 /* Radio: call before I2C 1 registeration */
@@ -893,4 +902,5 @@ MACHINE_START(GONI, "GONI")
893 .map_io = goni_map_io, 902 .map_io = goni_map_io,
894 .init_machine = goni_machine_init, 903 .init_machine = goni_machine_init,
895 .timer = &s5p_timer, 904 .timer = &s5p_timer,
905 .reserve = &goni_reserve,
896MACHINE_END 906MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index c6a9e86c2d5c..5e011fc6720d 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -29,7 +29,6 @@
29 29
30#include <mach/map.h> 30#include <mach/map.h>
31#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
32#include <mach/regs-fb.h>
33 32
34#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
35#include <plat/regs-srom.h> 34#include <plat/regs-srom.h>
@@ -45,6 +44,8 @@
45#include <plat/pm.h> 44#include <plat/pm.h>
46#include <plat/fb.h> 45#include <plat/fb.h>
47#include <plat/s5p-time.h> 46#include <plat/s5p-time.h>
47#include <plat/backlight.h>
48#include <plat/regs-fb-v4.h>
48 49
49/* Following are default values for UCON, ULCON and UFCON UART registers */ 50/* Following are default values for UCON, ULCON and UFCON UART registers */
50#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 51#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -210,45 +211,6 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
210 .setup_gpio = s5pv210_fb_gpio_setup_24bpp, 211 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
211}; 212};
212 213
213static int smdkv210_backlight_init(struct device *dev)
214{
215 int ret;
216
217 ret = gpio_request(S5PV210_GPD0(3), "Backlight");
218 if (ret) {
219 printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n");
220 return ret;
221 }
222
223 /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */
224 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2));
225
226 return 0;
227}
228
229static void smdkv210_backlight_exit(struct device *dev)
230{
231 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT);
232 gpio_free(S5PV210_GPD0(3));
233}
234
235static struct platform_pwm_backlight_data smdkv210_backlight_data = {
236 .pwm_id = 3,
237 .max_brightness = 255,
238 .dft_brightness = 255,
239 .pwm_period_ns = 78770,
240 .init = smdkv210_backlight_init,
241 .exit = smdkv210_backlight_exit,
242};
243
244static struct platform_device smdkv210_backlight_device = {
245 .name = "pwm-backlight",
246 .dev = {
247 .parent = &s3c_device_timer[3].dev,
248 .platform_data = &smdkv210_backlight_data,
249 },
250};
251
252static struct platform_device *smdkv210_devices[] __initdata = { 214static struct platform_device *smdkv210_devices[] __initdata = {
253 &s3c_device_adc, 215 &s3c_device_adc,
254 &s3c_device_cfcon, 216 &s3c_device_cfcon,
@@ -267,11 +229,10 @@ static struct platform_device *smdkv210_devices[] __initdata = {
267 &s5pv210_device_iis0, 229 &s5pv210_device_iis0,
268 &s5pv210_device_spdif, 230 &s5pv210_device_spdif,
269 &samsung_asoc_dma, 231 &samsung_asoc_dma,
232 &samsung_asoc_idma,
270 &samsung_device_keypad, 233 &samsung_device_keypad,
271 &smdkv210_dm9000, 234 &smdkv210_dm9000,
272 &smdkv210_lcd_lte480wv, 235 &smdkv210_lcd_lte480wv,
273 &s3c_device_timer[3],
274 &smdkv210_backlight_device,
275}; 236};
276 237
277static void __init smdkv210_dm9000_init(void) 238static void __init smdkv210_dm9000_init(void)
@@ -310,6 +271,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
310 .oversampling_shift = 2, 271 .oversampling_shift = 2,
311}; 272};
312 273
274/* LCD Backlight data */
275static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
276 .no = S5PV210_GPD0(3),
277 .func = S3C_GPIO_SFN(2),
278};
279
280static struct platform_pwm_backlight_data smdkv210_bl_data = {
281 .pwm_id = 3,
282};
283
313static void __init smdkv210_map_io(void) 284static void __init smdkv210_map_io(void)
314{ 285{
315 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 286 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -341,6 +312,8 @@ static void __init smdkv210_machine_init(void)
341 312
342 s3c_fb_set_platdata(&smdkv210_lcd0_pdata); 313 s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
343 314
315 samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
316
344 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); 317 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
345} 318}
346 319
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 24febae3d4c0..309e388a8a83 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = {
88 SAVE_ITEM(S3C2410_TCNTO(0)), 88 SAVE_ITEM(S3C2410_TCNTO(0)),
89}; 89};
90 90
91void s5pv210_cpu_suspend(void) 91void s5pv210_cpu_suspend(unsigned long arg)
92{ 92{
93 unsigned long tmp; 93 unsigned long tmp;
94 94
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
index e932ebfac56d..55103c8220b3 100644
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -15,7 +15,6 @@
15#include <linux/fb.h> 15#include <linux/fb.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17 17
18#include <mach/regs-fb.h>
19#include <mach/map.h> 18#include <mach/map.h>
20#include <plat/fb.h> 19#include <plat/fb.h>
21#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index a3d649466fb1..e3452ccd4b08 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -32,27 +32,6 @@
32 32
33 .text 33 .text
34 34
35 /* s3c_cpu_save
36 *
37 * entry:
38 * r1 = v:p offset
39 */
40
41ENTRY(s3c_cpu_save)
42
43 stmfd sp!, { r3 - r12, lr }
44 ldr r3, =resume_with_mmu
45 bl cpu_suspend
46
47 ldr r0, =pm_cpu_sleep
48 ldr r0, [ r0 ]
49 mov pc, r0
50
51resume_with_mmu:
52 ldmfd sp!, { r3 - r12, pc }
53
54 .ltorg
55
56 /* sleep magic, to allow the bootloader to check for an valid 35 /* sleep magic, to allow the bootloader to check for an valid
57 * image to resume to. Must be the first word before the 36 * image to resume to. Must be the first word before the
58 * s3c_cpu_resume entry. 37 * s3c_cpu_resume entry.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 02:46:16 -0500