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-rw-r--r--arch/arm/mach-s5pv210/clock.c324
1 files changed, 200 insertions, 124 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a69e9e..cead51321b29 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = {
399 .enable = s5pv210_clk_ip1_ctrl, 399 .enable = s5pv210_clk_ip1_ctrl,
400 .ctrlbit = (1<<25), 400 .ctrlbit = (1<<25),
401 }, { 401 }, {
402 .name = "hsmmc",
403 .devname = "s3c-sdhci.0",
404 .parent = &clk_hclk_psys.clk,
405 .enable = s5pv210_clk_ip2_ctrl,
406 .ctrlbit = (1<<16),
407 }, {
408 .name = "hsmmc",
409 .devname = "s3c-sdhci.1",
410 .parent = &clk_hclk_psys.clk,
411 .enable = s5pv210_clk_ip2_ctrl,
412 .ctrlbit = (1<<17),
413 }, {
414 .name = "hsmmc",
415 .devname = "s3c-sdhci.2",
416 .parent = &clk_hclk_psys.clk,
417 .enable = s5pv210_clk_ip2_ctrl,
418 .ctrlbit = (1<<18),
419 }, {
420 .name = "hsmmc",
421 .devname = "s3c-sdhci.3",
422 .parent = &clk_hclk_psys.clk,
423 .enable = s5pv210_clk_ip2_ctrl,
424 .ctrlbit = (1<<19),
425 }, {
426 .name = "systimer", 402 .name = "systimer",
427 .parent = &clk_pclk_psys.clk, 403 .parent = &clk_pclk_psys.clk,
428 .enable = s5pv210_clk_ip3_ctrl, 404 .enable = s5pv210_clk_ip3_ctrl,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
559 }, 535 },
560}; 536};
561 537
538static struct clk clk_hsmmc0 = {
539 .name = "hsmmc",
540 .devname = "s3c-sdhci.0",
541 .parent = &clk_hclk_psys.clk,
542 .enable = s5pv210_clk_ip2_ctrl,
543 .ctrlbit = (1<<16),
544};
545
546static struct clk clk_hsmmc1 = {
547 .name = "hsmmc",
548 .devname = "s3c-sdhci.1",
549 .parent = &clk_hclk_psys.clk,
550 .enable = s5pv210_clk_ip2_ctrl,
551 .ctrlbit = (1<<17),
552};
553
554static struct clk clk_hsmmc2 = {
555 .name = "hsmmc",
556 .devname = "s3c-sdhci.2",
557 .parent = &clk_hclk_psys.clk,
558 .enable = s5pv210_clk_ip2_ctrl,
559 .ctrlbit = (1<<18),
560};
561
562static struct clk clk_hsmmc3 = {
563 .name = "hsmmc",
564 .devname = "s3c-sdhci.3",
565 .parent = &clk_hclk_psys.clk,
566 .enable = s5pv210_clk_ip2_ctrl,
567 .ctrlbit = (1<<19),
568};
569
562static struct clk *clkset_uart_list[] = { 570static struct clk *clkset_uart_list[] = {
563 [6] = &clk_mout_mpll.clk, 571 [6] = &clk_mout_mpll.clk,
564 [7] = &clk_mout_epll.clk, 572 [7] = &clk_mout_epll.clk,
@@ -809,46 +817,6 @@ static struct clksrc_clk clksrcs[] = {
809 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, 817 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
810 }, { 818 }, {
811 .clk = { 819 .clk = {
812 .name = "uclk1",
813 .devname = "s5pv210-uart.0",
814 .enable = s5pv210_clk_mask0_ctrl,
815 .ctrlbit = (1 << 12),
816 },
817 .sources = &clkset_uart,
818 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
819 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
820 }, {
821 .clk = {
822 .name = "uclk1",
823 .devname = "s5pv210-uart.1",
824 .enable = s5pv210_clk_mask0_ctrl,
825 .ctrlbit = (1 << 13),
826 },
827 .sources = &clkset_uart,
828 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
830 }, {
831 .clk = {
832 .name = "uclk1",
833 .devname = "s5pv210-uart.2",
834 .enable = s5pv210_clk_mask0_ctrl,
835 .ctrlbit = (1 << 14),
836 },
837 .sources = &clkset_uart,
838 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
839 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
840 }, {
841 .clk = {
842 .name = "uclk1",
843 .devname = "s5pv210-uart.3",
844 .enable = s5pv210_clk_mask0_ctrl,
845 .ctrlbit = (1 << 15),
846 },
847 .sources = &clkset_uart,
848 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
849 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
850 }, {
851 .clk = {
852 .name = "sclk_fimc", 820 .name = "sclk_fimc",
853 .devname = "s5pv210-fimc.0", 821 .devname = "s5pv210-fimc.0",
854 .enable = s5pv210_clk_mask1_ctrl, 822 .enable = s5pv210_clk_mask1_ctrl,
@@ -906,46 +874,6 @@ static struct clksrc_clk clksrcs[] = {
906 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, 874 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
907 }, { 875 }, {
908 .clk = { 876 .clk = {
909 .name = "sclk_mmc",
910 .devname = "s3c-sdhci.0",
911 .enable = s5pv210_clk_mask0_ctrl,
912 .ctrlbit = (1 << 8),
913 },
914 .sources = &clkset_group2,
915 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
916 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
917 }, {
918 .clk = {
919 .name = "sclk_mmc",
920 .devname = "s3c-sdhci.1",
921 .enable = s5pv210_clk_mask0_ctrl,
922 .ctrlbit = (1 << 9),
923 },
924 .sources = &clkset_group2,
925 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
926 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
927 }, {
928 .clk = {
929 .name = "sclk_mmc",
930 .devname = "s3c-sdhci.2",
931 .enable = s5pv210_clk_mask0_ctrl,
932 .ctrlbit = (1 << 10),
933 },
934 .sources = &clkset_group2,
935 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
936 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
937 }, {
938 .clk = {
939 .name = "sclk_mmc",
940 .devname = "s3c-sdhci.3",
941 .enable = s5pv210_clk_mask0_ctrl,
942 .ctrlbit = (1 << 11),
943 },
944 .sources = &clkset_group2,
945 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
946 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
947 }, {
948 .clk = {
949 .name = "sclk_mfc", 877 .name = "sclk_mfc",
950 .devname = "s5p-mfc", 878 .devname = "s5p-mfc",
951 .enable = s5pv210_clk_ip0_ctrl, 879 .enable = s5pv210_clk_ip0_ctrl,
@@ -983,26 +911,6 @@ static struct clksrc_clk clksrcs[] = {
983 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, 911 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
984 }, { 912 }, {
985 .clk = { 913 .clk = {
986 .name = "sclk_spi",
987 .devname = "s3c64xx-spi.0",
988 .enable = s5pv210_clk_mask0_ctrl,
989 .ctrlbit = (1 << 16),
990 },
991 .sources = &clkset_group2,
992 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
993 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
994 }, {
995 .clk = {
996 .name = "sclk_spi",
997 .devname = "s3c64xx-spi.1",
998 .enable = s5pv210_clk_mask0_ctrl,
999 .ctrlbit = (1 << 17),
1000 },
1001 .sources = &clkset_group2,
1002 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1003 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1004 }, {
1005 .clk = {
1006 .name = "sclk_pwi", 914 .name = "sclk_pwi",
1007 .enable = s5pv210_clk_mask0_ctrl, 915 .enable = s5pv210_clk_mask0_ctrl,
1008 .ctrlbit = (1 << 29), 916 .ctrlbit = (1 << 29),
@@ -1022,6 +930,147 @@ static struct clksrc_clk clksrcs[] = {
1022 }, 930 },
1023}; 931};
1024 932
933static struct clksrc_clk clk_sclk_uart0 = {
934 .clk = {
935 .name = "uclk1",
936 .devname = "s5pv210-uart.0",
937 .enable = s5pv210_clk_mask0_ctrl,
938 .ctrlbit = (1 << 12),
939 },
940 .sources = &clkset_uart,
941 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
942 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
943};
944
945static struct clksrc_clk clk_sclk_uart1 = {
946 .clk = {
947 .name = "uclk1",
948 .devname = "s5pv210-uart.1",
949 .enable = s5pv210_clk_mask0_ctrl,
950 .ctrlbit = (1 << 13),
951 },
952 .sources = &clkset_uart,
953 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
954 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
955};
956
957static struct clksrc_clk clk_sclk_uart2 = {
958 .clk = {
959 .name = "uclk1",
960 .devname = "s5pv210-uart.2",
961 .enable = s5pv210_clk_mask0_ctrl,
962 .ctrlbit = (1 << 14),
963 },
964 .sources = &clkset_uart,
965 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
966 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
967};
968
969static struct clksrc_clk clk_sclk_uart3 = {
970 .clk = {
971 .name = "uclk1",
972 .devname = "s5pv210-uart.3",
973 .enable = s5pv210_clk_mask0_ctrl,
974 .ctrlbit = (1 << 15),
975 },
976 .sources = &clkset_uart,
977 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
978 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
979};
980
981static struct clksrc_clk clk_sclk_mmc0 = {
982 .clk = {
983 .name = "sclk_mmc",
984 .devname = "s3c-sdhci.0",
985 .enable = s5pv210_clk_mask0_ctrl,
986 .ctrlbit = (1 << 8),
987 },
988 .sources = &clkset_group2,
989 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
990 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
991};
992
993static struct clksrc_clk clk_sclk_mmc1 = {
994 .clk = {
995 .name = "sclk_mmc",
996 .devname = "s3c-sdhci.1",
997 .enable = s5pv210_clk_mask0_ctrl,
998 .ctrlbit = (1 << 9),
999 },
1000 .sources = &clkset_group2,
1001 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1002 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1003};
1004
1005static struct clksrc_clk clk_sclk_mmc2 = {
1006 .clk = {
1007 .name = "sclk_mmc",
1008 .devname = "s3c-sdhci.2",
1009 .enable = s5pv210_clk_mask0_ctrl,
1010 .ctrlbit = (1 << 10),
1011 },
1012 .sources = &clkset_group2,
1013 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1014 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1015};
1016
1017static struct clksrc_clk clk_sclk_mmc3 = {
1018 .clk = {
1019 .name = "sclk_mmc",
1020 .devname = "s3c-sdhci.3",
1021 .enable = s5pv210_clk_mask0_ctrl,
1022 .ctrlbit = (1 << 11),
1023 },
1024 .sources = &clkset_group2,
1025 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1026 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1027};
1028
1029static struct clksrc_clk clk_sclk_spi0 = {
1030 .clk = {
1031 .name = "sclk_spi",
1032 .devname = "s3c64xx-spi.0",
1033 .enable = s5pv210_clk_mask0_ctrl,
1034 .ctrlbit = (1 << 16),
1035 },
1036 .sources = &clkset_group2,
1037 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1038 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1039 };
1040
1041static struct clksrc_clk clk_sclk_spi1 = {
1042 .clk = {
1043 .name = "sclk_spi",
1044 .devname = "s3c64xx-spi.1",
1045 .enable = s5pv210_clk_mask0_ctrl,
1046 .ctrlbit = (1 << 17),
1047 },
1048 .sources = &clkset_group2,
1049 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1050 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1051 };
1052
1053
1054static struct clksrc_clk *clksrc_cdev[] = {
1055 &clk_sclk_uart0,
1056 &clk_sclk_uart1,
1057 &clk_sclk_uart2,
1058 &clk_sclk_uart3,
1059 &clk_sclk_mmc0,
1060 &clk_sclk_mmc1,
1061 &clk_sclk_mmc2,
1062 &clk_sclk_mmc3,
1063 &clk_sclk_spi0,
1064 &clk_sclk_spi1,
1065};
1066
1067static struct clk *clk_cdev[] = {
1068 &clk_hsmmc0,
1069 &clk_hsmmc1,
1070 &clk_hsmmc2,
1071 &clk_hsmmc3,
1072};
1073
1025/* Clock initialisation code */ 1074/* Clock initialisation code */
1026static struct clksrc_clk *sysclks[] = { 1075static struct clksrc_clk *sysclks[] = {
1027 &clk_mout_apll, 1076 &clk_mout_apll,
@@ -1261,6 +1310,25 @@ static struct clk *clks[] __initdata = {
1261 &clk_pcmcdclk2, 1310 &clk_pcmcdclk2,
1262}; 1311};
1263 1312
1313static struct clk_lookup s5pv210_clk_lookup[] = {
1314 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1315 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1316 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1317 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1318 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1319 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1320 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1321 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1322 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1323 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1324 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1325 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1326 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1327 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1328 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1329 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1330};
1331
1264void __init s5pv210_register_clocks(void) 1332void __init s5pv210_register_clocks(void)
1265{ 1333{
1266 int ptr; 1334 int ptr;
@@ -1273,11 +1341,19 @@ void __init s5pv210_register_clocks(void)
1273 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1341 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1274 s3c_register_clksrc(sclk_tv[ptr], 1); 1342 s3c_register_clksrc(sclk_tv[ptr], 1);
1275 1343
1344 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1345 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1346
1276 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1347 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1277 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1348 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1278 1349
1279 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1350 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1280 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1351 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1352 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1353
1354 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1355 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1356 s3c_disable_clocks(clk_cdev[ptr], 1);
1281 1357
1282 s3c24xx_register_clock(&dummy_apb_pclk); 1358 s3c24xx_register_clock(&dummy_apb_pclk);
1283 s3c_pwmclk_init(); 1359 s3c_pwmclk_init();
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 14:11:34 -0400