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-rw-r--r--arch/arm/mach-s5p64x0/Kconfig14
-rw-r--r--arch/arm/mach-s5p64x0/Makefile3
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c10
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c10
-rw-r--r--arch/arm/mach-s5p64x0/cpu.c3
-rw-r--r--arch/arm/mach-s5p64x0/dma.c269
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/dma.h4
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h4
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c74
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c75
-rw-r--r--arch/arm/mach-s5p64x0/setup-fb-24bpp.c29
13 files changed, 407 insertions, 95 deletions
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 65c7518dad7f..e361c41314e9 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,18 +9,24 @@ if ARCH_S5P64X0
9 9
10config CPU_S5P6440 10config CPU_S5P6440
11 bool 11 bool
12 select S3C_PL330_DMA 12 select SAMSUNG_DMADEV
13 select S5P_HRT 13 select S5P_HRT
14 help 14 help
15 Enable S5P6440 CPU support 15 Enable S5P6440 CPU support
16 16
17config CPU_S5P6450 17config CPU_S5P6450
18 bool 18 bool
19 select S3C_PL330_DMA 19 select SAMSUNG_DMADEV
20 select S5P_HRT 20 select S5P_HRT
21 help 21 help
22 Enable S5P6450 CPU support 22 Enable S5P6450 CPU support
23 23
24config S5P64X0_SETUP_FB_24BPP
25 bool
26 help
27 Common setup code for S5P64X0 based boards with a LCD display
28 through RGB interface.
29
24config S5P64X0_SETUP_I2C1 30config S5P64X0_SETUP_I2C1
25 bool 31 bool
26 help 32 help
@@ -31,6 +37,7 @@ config S5P64X0_SETUP_I2C1
31config MACH_SMDK6440 37config MACH_SMDK6440
32 bool "SMDK6440" 38 bool "SMDK6440"
33 select CPU_S5P6440 39 select CPU_S5P6440
40 select S3C_DEV_FB
34 select S3C_DEV_I2C1 41 select S3C_DEV_I2C1
35 select S3C_DEV_RTC 42 select S3C_DEV_RTC
36 select S3C_DEV_WDT 43 select S3C_DEV_WDT
@@ -39,6 +46,7 @@ config MACH_SMDK6440
39 select SAMSUNG_DEV_BACKLIGHT 46 select SAMSUNG_DEV_BACKLIGHT
40 select SAMSUNG_DEV_PWM 47 select SAMSUNG_DEV_PWM
41 select SAMSUNG_DEV_TS 48 select SAMSUNG_DEV_TS
49 select S5P64X0_SETUP_FB_24BPP
42 select S5P64X0_SETUP_I2C1 50 select S5P64X0_SETUP_I2C1
43 help 51 help
44 Machine support for the Samsung SMDK6440 52 Machine support for the Samsung SMDK6440
@@ -46,6 +54,7 @@ config MACH_SMDK6440
46config MACH_SMDK6450 54config MACH_SMDK6450
47 bool "SMDK6450" 55 bool "SMDK6450"
48 select CPU_S5P6450 56 select CPU_S5P6450
57 select S3C_DEV_FB
49 select S3C_DEV_I2C1 58 select S3C_DEV_I2C1
50 select S3C_DEV_RTC 59 select S3C_DEV_RTC
51 select S3C_DEV_WDT 60 select S3C_DEV_WDT
@@ -54,6 +63,7 @@ config MACH_SMDK6450
54 select SAMSUNG_DEV_BACKLIGHT 63 select SAMSUNG_DEV_BACKLIGHT
55 select SAMSUNG_DEV_PWM 64 select SAMSUNG_DEV_PWM
56 select SAMSUNG_DEV_TS 65 select SAMSUNG_DEV_TS
66 select S5P64X0_SETUP_FB_24BPP
57 select S5P64X0_SETUP_I2C1 67 select S5P64X0_SETUP_I2C1
58 help 68 help
59 Machine support for the Samsung SMDK6450 69 Machine support for the Samsung SMDK6450
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 5f6afdf067ed..eb7468012a37 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -12,7 +12,7 @@ obj- :=
12 12
13# Core support for S5P64X0 system 13# Core support for S5P64X0 system
14 14
15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o 15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o 16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o 17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o 18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
@@ -28,3 +28,4 @@ obj-y += dev-audio.o
28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o 28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
29 29
30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o 30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
31obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 0e9cd3092dd2..c54c65d511f0 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -146,7 +146,8 @@ static struct clk init_clocks_off[] = {
146 .enable = s5p64x0_hclk0_ctrl, 146 .enable = s5p64x0_hclk0_ctrl,
147 .ctrlbit = (1 << 8), 147 .ctrlbit = (1 << 8),
148 }, { 148 }, {
149 .name = "pdma", 149 .name = "dma",
150 .devname = "dma-pl330",
150 .parent = &clk_hclk_low.clk, 151 .parent = &clk_hclk_low.clk,
151 .enable = s5p64x0_hclk0_ctrl, 152 .enable = s5p64x0_hclk0_ctrl,
152 .ctrlbit = (1 << 12), 153 .ctrlbit = (1 << 12),
@@ -499,6 +500,11 @@ static struct clksrc_clk *sysclks[] = {
499 &clk_pclk_low, 500 &clk_pclk_low,
500}; 501};
501 502
503static struct clk dummy_apb_pclk = {
504 .name = "apb_pclk",
505 .id = -1,
506};
507
502void __init_or_cpufreq s5p6440_setup_clocks(void) 508void __init_or_cpufreq s5p6440_setup_clocks(void)
503{ 509{
504 struct clk *xtal_clk; 510 struct clk *xtal_clk;
@@ -581,5 +587,7 @@ void __init s5p6440_register_clocks(void)
581 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 587 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
582 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 588 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
583 589
590 s3c24xx_register_clock(&dummy_apb_pclk);
591
584 s3c_pwmclk_init(); 592 s3c_pwmclk_init();
585} 593}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d9dc16cde109..2d04abfba12e 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -179,7 +179,8 @@ static struct clk init_clocks_off[] = {
179 .enable = s5p64x0_hclk0_ctrl, 179 .enable = s5p64x0_hclk0_ctrl,
180 .ctrlbit = (1 << 3), 180 .ctrlbit = (1 << 3),
181 }, { 181 }, {
182 .name = "pdma", 182 .name = "dma",
183 .devname = "dma-pl330",
183 .parent = &clk_hclk_low.clk, 184 .parent = &clk_hclk_low.clk,
184 .enable = s5p64x0_hclk0_ctrl, 185 .enable = s5p64x0_hclk0_ctrl,
185 .ctrlbit = (1 << 12), 186 .ctrlbit = (1 << 12),
@@ -553,6 +554,11 @@ static struct clksrc_clk *sysclks[] = {
553 &clk_sclk_audio0, 554 &clk_sclk_audio0,
554}; 555};
555 556
557static struct clk dummy_apb_pclk = {
558 .name = "apb_pclk",
559 .id = -1,
560};
561
556void __init_or_cpufreq s5p6450_setup_clocks(void) 562void __init_or_cpufreq s5p6450_setup_clocks(void)
557{ 563{
558 struct clk *xtal_clk; 564 struct clk *xtal_clk;
@@ -632,5 +638,7 @@ void __init s5p6450_register_clocks(void)
632 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 638 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
633 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 639 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
634 640
641 s3c24xx_register_clock(&dummy_apb_pclk);
642
635 s3c_pwmclk_init(); 643 s3c_pwmclk_init();
636} 644}
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index a5c00952ea35..617da3b3bfb7 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -38,6 +38,7 @@
38#include <plat/s5p6440.h> 38#include <plat/s5p6440.h>
39#include <plat/s5p6450.h> 39#include <plat/s5p6450.h>
40#include <plat/adc-core.h> 40#include <plat/adc-core.h>
41#include <plat/fb-core.h>
41 42
42/* Initial IO mappings */ 43/* Initial IO mappings */
43 44
@@ -108,6 +109,7 @@ void __init s5p6440_map_io(void)
108{ 109{
109 /* initialize any device information early */ 110 /* initialize any device information early */
110 s3c_adc_setname("s3c64xx-adc"); 111 s3c_adc_setname("s3c64xx-adc");
112 s3c_fb_setname("s5p64x0-fb");
111 113
112 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 114 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
113 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); 115 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
@@ -117,6 +119,7 @@ void __init s5p6450_map_io(void)
117{ 119{
118 /* initialize any device information early */ 120 /* initialize any device information early */
119 s3c_adc_setname("s3c64xx-adc"); 121 s3c_adc_setname("s3c64xx-adc");
122 s3c_fb_setname("s5p64x0-fb");
120 123
121 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 124 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
122 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); 125 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 0e5b3e63e5b3..442dd4ad12da 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -21,115 +21,208 @@
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/ 22*/
23 23
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
26 29
27#include <mach/map.h> 30#include <mach/map.h>
28#include <mach/irqs.h> 31#include <mach/irqs.h>
29#include <mach/regs-clock.h> 32#include <mach/regs-clock.h>
33#include <mach/dma.h>
30 34
31#include <plat/cpu.h> 35#include <plat/cpu.h>
32#include <plat/devs.h> 36#include <plat/devs.h>
33#include <plat/s3c-pl330-pdata.h> 37#include <plat/irqs.h>
34 38
35static u64 dma_dmamask = DMA_BIT_MASK(32); 39static u64 dma_dmamask = DMA_BIT_MASK(32);
36 40
37static struct resource s5p64x0_pdma_resource[] = { 41struct dma_pl330_peri s5p6440_pdma_peri[22] = {
38 [0] = { 42 {
39 .start = S5P64X0_PA_PDMA, 43 .peri_id = (u8)DMACH_UART0_RX,
40 .end = S5P64X0_PA_PDMA + SZ_4K, 44 .rqtype = DEVTOMEM,
41 .flags = IORESOURCE_MEM, 45 }, {
42 }, 46 .peri_id = (u8)DMACH_UART0_TX,
43 [1] = { 47 .rqtype = MEMTODEV,
44 .start = IRQ_DMA0, 48 }, {
45 .end = IRQ_DMA0, 49 .peri_id = (u8)DMACH_UART1_RX,
46 .flags = IORESOURCE_IRQ, 50 .rqtype = DEVTOMEM,
51 }, {
52 .peri_id = (u8)DMACH_UART1_TX,
53 .rqtype = MEMTODEV,
54 }, {
55 .peri_id = (u8)DMACH_UART2_RX,
56 .rqtype = DEVTOMEM,
57 }, {
58 .peri_id = (u8)DMACH_UART2_TX,
59 .rqtype = MEMTODEV,
60 }, {
61 .peri_id = (u8)DMACH_UART3_RX,
62 .rqtype = DEVTOMEM,
63 }, {
64 .peri_id = (u8)DMACH_UART3_TX,
65 .rqtype = MEMTODEV,
66 }, {
67 .peri_id = DMACH_MAX,
68 }, {
69 .peri_id = DMACH_MAX,
70 }, {
71 .peri_id = (u8)DMACH_PCM0_TX,
72 .rqtype = MEMTODEV,
73 }, {
74 .peri_id = (u8)DMACH_PCM0_RX,
75 .rqtype = DEVTOMEM,
76 }, {
77 .peri_id = (u8)DMACH_I2S0_TX,
78 .rqtype = MEMTODEV,
79 }, {
80 .peri_id = (u8)DMACH_I2S0_RX,
81 .rqtype = DEVTOMEM,
82 }, {
83 .peri_id = (u8)DMACH_SPI0_TX,
84 .rqtype = MEMTODEV,
85 }, {
86 .peri_id = (u8)DMACH_SPI0_RX,
87 .rqtype = DEVTOMEM,
88 }, {
89 .peri_id = (u8)DMACH_MAX,
90 }, {
91 .peri_id = (u8)DMACH_MAX,
92 }, {
93 .peri_id = (u8)DMACH_MAX,
94 }, {
95 .peri_id = (u8)DMACH_MAX,
96 }, {
97 .peri_id = (u8)DMACH_SPI1_TX,
98 .rqtype = MEMTODEV,
99 }, {
100 .peri_id = (u8)DMACH_SPI1_RX,
101 .rqtype = DEVTOMEM,
47 }, 102 },
48}; 103};
49 104
50static struct s3c_pl330_platdata s5p6440_pdma_pdata = { 105struct dma_pl330_platdata s5p6440_pdma_pdata = {
51 .peri = { 106 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
52 [0] = DMACH_UART0_RX, 107 .peri = s5p6440_pdma_peri,
53 [1] = DMACH_UART0_TX,
54 [2] = DMACH_UART1_RX,
55 [3] = DMACH_UART1_TX,
56 [4] = DMACH_UART2_RX,
57 [5] = DMACH_UART2_TX,
58 [6] = DMACH_UART3_RX,
59 [7] = DMACH_UART3_TX,
60 [8] = DMACH_MAX,
61 [9] = DMACH_MAX,
62 [10] = DMACH_PCM0_TX,
63 [11] = DMACH_PCM0_RX,
64 [12] = DMACH_I2S0_TX,
65 [13] = DMACH_I2S0_RX,
66 [14] = DMACH_SPI0_TX,
67 [15] = DMACH_SPI0_RX,
68 [16] = DMACH_MAX,
69 [17] = DMACH_MAX,
70 [18] = DMACH_MAX,
71 [19] = DMACH_MAX,
72 [20] = DMACH_SPI1_TX,
73 [21] = DMACH_SPI1_RX,
74 [22] = DMACH_MAX,
75 [23] = DMACH_MAX,
76 [24] = DMACH_MAX,
77 [25] = DMACH_MAX,
78 [26] = DMACH_MAX,
79 [27] = DMACH_MAX,
80 [28] = DMACH_MAX,
81 [29] = DMACH_PWM,
82 [30] = DMACH_MAX,
83 [31] = DMACH_MAX,
84 },
85}; 108};
86 109
87static struct s3c_pl330_platdata s5p6450_pdma_pdata = { 110struct dma_pl330_peri s5p6450_pdma_peri[32] = {
88 .peri = { 111 {
89 [0] = DMACH_UART0_RX, 112 .peri_id = (u8)DMACH_UART0_RX,
90 [1] = DMACH_UART0_TX, 113 .rqtype = DEVTOMEM,
91 [2] = DMACH_UART1_RX, 114 }, {
92 [3] = DMACH_UART1_TX, 115 .peri_id = (u8)DMACH_UART0_TX,
93 [4] = DMACH_UART2_RX, 116 .rqtype = MEMTODEV,
94 [5] = DMACH_UART2_TX, 117 }, {
95 [6] = DMACH_UART3_RX, 118 .peri_id = (u8)DMACH_UART1_RX,
96 [7] = DMACH_UART3_TX, 119 .rqtype = DEVTOMEM,
97 [8] = DMACH_UART4_RX, 120 }, {
98 [9] = DMACH_UART4_TX, 121 .peri_id = (u8)DMACH_UART1_TX,
99 [10] = DMACH_PCM0_TX, 122 .rqtype = MEMTODEV,
100 [11] = DMACH_PCM0_RX, 123 }, {
101 [12] = DMACH_I2S0_TX, 124 .peri_id = (u8)DMACH_UART2_RX,
102 [13] = DMACH_I2S0_RX, 125 .rqtype = DEVTOMEM,
103 [14] = DMACH_SPI0_TX, 126 }, {
104 [15] = DMACH_SPI0_RX, 127 .peri_id = (u8)DMACH_UART2_TX,
105 [16] = DMACH_PCM1_TX, 128 .rqtype = MEMTODEV,
106 [17] = DMACH_PCM1_RX, 129 }, {
107 [18] = DMACH_PCM2_TX, 130 .peri_id = (u8)DMACH_UART3_RX,
108 [19] = DMACH_PCM2_RX, 131 .rqtype = DEVTOMEM,
109 [20] = DMACH_SPI1_TX, 132 }, {
110 [21] = DMACH_SPI1_RX, 133 .peri_id = (u8)DMACH_UART3_TX,
111 [22] = DMACH_USI_TX, 134 .rqtype = MEMTODEV,
112 [23] = DMACH_USI_RX, 135 }, {
113 [24] = DMACH_MAX, 136 .peri_id = (u8)DMACH_UART4_RX,
114 [25] = DMACH_I2S1_TX, 137 .rqtype = DEVTOMEM,
115 [26] = DMACH_I2S1_RX, 138 }, {
116 [27] = DMACH_I2S2_TX, 139 .peri_id = (u8)DMACH_UART4_TX,
117 [28] = DMACH_I2S2_RX, 140 .rqtype = MEMTODEV,
118 [29] = DMACH_PWM, 141 }, {
119 [30] = DMACH_UART5_RX, 142 .peri_id = (u8)DMACH_PCM0_TX,
120 [31] = DMACH_UART5_TX, 143 .rqtype = MEMTODEV,
144 }, {
145 .peri_id = (u8)DMACH_PCM0_RX,
146 .rqtype = DEVTOMEM,
147 }, {
148 .peri_id = (u8)DMACH_I2S0_TX,
149 .rqtype = MEMTODEV,
150 }, {
151 .peri_id = (u8)DMACH_I2S0_RX,
152 .rqtype = DEVTOMEM,
153 }, {
154 .peri_id = (u8)DMACH_SPI0_TX,
155 .rqtype = MEMTODEV,
156 }, {
157 .peri_id = (u8)DMACH_SPI0_RX,
158 .rqtype = DEVTOMEM,
159 }, {
160 .peri_id = (u8)DMACH_PCM1_TX,
161 .rqtype = MEMTODEV,
162 }, {
163 .peri_id = (u8)DMACH_PCM1_RX,
164 .rqtype = DEVTOMEM,
165 }, {
166 .peri_id = (u8)DMACH_PCM2_TX,
167 .rqtype = MEMTODEV,
168 }, {
169 .peri_id = (u8)DMACH_PCM2_RX,
170 .rqtype = DEVTOMEM,
171 }, {
172 .peri_id = (u8)DMACH_SPI1_TX,
173 .rqtype = MEMTODEV,
174 }, {
175 .peri_id = (u8)DMACH_SPI1_RX,
176 .rqtype = DEVTOMEM,
177 }, {
178 .peri_id = (u8)DMACH_USI_TX,
179 .rqtype = MEMTODEV,
180 }, {
181 .peri_id = (u8)DMACH_USI_RX,
182 .rqtype = DEVTOMEM,
183 }, {
184 .peri_id = (u8)DMACH_MAX,
185 }, {
186 .peri_id = (u8)DMACH_I2S1_TX,
187 .rqtype = MEMTODEV,
188 }, {
189 .peri_id = (u8)DMACH_I2S1_RX,
190 .rqtype = DEVTOMEM,
191 }, {
192 .peri_id = (u8)DMACH_I2S2_TX,
193 .rqtype = MEMTODEV,
194 }, {
195 .peri_id = (u8)DMACH_I2S2_RX,
196 .rqtype = DEVTOMEM,
197 }, {
198 .peri_id = (u8)DMACH_PWM,
199 }, {
200 .peri_id = (u8)DMACH_UART5_RX,
201 .rqtype = DEVTOMEM,
202 }, {
203 .peri_id = (u8)DMACH_UART5_TX,
204 .rqtype = MEMTODEV,
121 }, 205 },
122}; 206};
123 207
124static struct platform_device s5p64x0_device_pdma = { 208struct dma_pl330_platdata s5p6450_pdma_pdata = {
125 .name = "s3c-pl330", 209 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
126 .id = -1, 210 .peri = s5p6450_pdma_peri,
127 .num_resources = ARRAY_SIZE(s5p64x0_pdma_resource), 211};
128 .resource = s5p64x0_pdma_resource, 212
129 .dev = { 213struct amba_device s5p64x0_device_pdma = {
214 .dev = {
215 .init_name = "dma-pl330",
130 .dma_mask = &dma_dmamask, 216 .dma_mask = &dma_dmamask,
131 .coherent_dma_mask = DMA_BIT_MASK(32), 217 .coherent_dma_mask = DMA_BIT_MASK(32),
132 }, 218 },
219 .res = {
220 .start = S5P64X0_PA_PDMA,
221 .end = S5P64X0_PA_PDMA + SZ_4K,
222 .flags = IORESOURCE_MEM,
223 },
224 .irq = {IRQ_DMA0, NO_IRQ},
225 .periphid = 0x00041330,
133}; 226};
134 227
135static int __init s5p64x0_dma_init(void) 228static int __init s5p64x0_dma_init(void)
@@ -139,7 +232,7 @@ static int __init s5p64x0_dma_init(void)
139 else 232 else
140 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 233 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
141 234
142 platform_device_register(&s5p64x0_device_pdma); 235 amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
143 236
144 return 0; 237 return 0;
145} 238}
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
index 81209eb1409b..5a622af461d7 100644
--- a/arch/arm/mach-s5p64x0/include/mach/dma.h
+++ b/arch/arm/mach-s5p64x0/include/mach/dma.h
@@ -20,7 +20,7 @@
20#ifndef __MACH_DMA_H 20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H 21#define __MACH_DMA_H
22 22
23/* This platform uses the common S3C DMA API driver for PL330 */ 23/* This platform uses the common common DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h> 24#include <plat/dma-pl330.h>
25 25
26#endif /* __MACH_DMA_H */ 26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 5837a36ece8d..53982db9d259 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -87,6 +87,10 @@
87 87
88#define IRQ_I2S0 IRQ_I2SV40 88#define IRQ_I2S0 IRQ_I2SV40
89 89
90#define IRQ_LCD_FIFO IRQ_DISPCON0
91#define IRQ_LCD_VSYNC IRQ_DISPCON1
92#define IRQ_LCD_SYSTEM IRQ_DISPCON2
93
90/* S5P6450 EINT feature will be added */ 94/* S5P6450 EINT feature will be added */
91 95
92/* 96/*
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 95c91257c7ca..c5ef50c26291 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -47,6 +47,8 @@
47 47
48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
49 49
50#define S5P64X0_PA_FB 0xEE000000
51
50#define S5P64X0_PA_I2S 0xF2000000 52#define S5P64X0_PA_I2S 0xF2000000
51#define S5P6450_PA_I2S1 0xF2800000 53#define S5P6450_PA_I2S1 0xF2800000
52#define S5P6450_PA_I2S2 0xF2900000 54#define S5P6450_PA_I2S2 0xF2900000
@@ -64,6 +66,7 @@
64#define S3C_PA_IIC1 S5P6440_PA_IIC1 66#define S3C_PA_IIC1 S5P6440_PA_IIC1
65#define S3C_PA_RTC S5P64X0_PA_RTC 67#define S3C_PA_RTC S5P64X0_PA_RTC
66#define S3C_PA_WDT S5P64X0_PA_WDT 68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB
67 70
68#define S5P_PA_CHIPID S5P64X0_PA_CHIPID 71#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
69#define S5P_PA_SROMC S5P64X0_PA_SROMC 72#define S5P_PA_SROMC S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 6ce254729f3b..88269ec70a38 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,6 +34,10 @@
34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) 34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) 35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
36 36
37#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
38#define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0)
39#define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0)
40
37/* External interrupt control registers for group0 */ 41/* External interrupt control registers for group0 */
38 42
39#define EINT0CON0_OFFSET (0x900) 43#define EINT0CON0_OFFSET (0x900)
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 340f30f4a3da..b0465d4e84e7 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -23,6 +23,9 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h> 25#include <linux/pwm_backlight.h>
26#include <linux/fb.h>
27
28#include <video/platform_lcd.h>
26 29
27#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 31#include <asm/mach/map.h>
@@ -47,6 +50,8 @@
47#include <plat/ts.h> 50#include <plat/ts.h>
48#include <plat/s5p-time.h> 51#include <plat/s5p-time.h>
49#include <plat/backlight.h> 52#include <plat/backlight.h>
53#include <plat/fb.h>
54#include <plat/regs-fb.h>
50 55
51#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 56#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
52 S3C2410_UCON_RXILEVEL | \ 57 S3C2410_UCON_RXILEVEL | \
@@ -92,6 +97,59 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
92 }, 97 },
93}; 98};
94 99
100/* Frame Buffer */
101static struct s3c_fb_pd_win smdk6440_fb_win0 = {
102 .win_mode = {
103 .left_margin = 8,
104 .right_margin = 13,
105 .upper_margin = 7,
106 .lower_margin = 5,
107 .hsync_len = 3,
108 .vsync_len = 1,
109 .xres = 800,
110 .yres = 480,
111 },
112 .max_bpp = 32,
113 .default_bpp = 24,
114};
115
116static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
117 .win[0] = &smdk6440_fb_win0,
118 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
119 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
120 .setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
121};
122
123/* LCD power controller */
124static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd,
125 unsigned int power)
126{
127 int err;
128
129 if (power) {
130 err = gpio_request(S5P6440_GPN(5), "GPN");
131 if (err) {
132 printk(KERN_ERR "failed to request GPN for lcd reset\n");
133 return;
134 }
135
136 gpio_direction_output(S5P6440_GPN(5), 1);
137 gpio_set_value(S5P6440_GPN(5), 0);
138 gpio_set_value(S5P6440_GPN(5), 1);
139 gpio_free(S5P6440_GPN(5));
140 }
141}
142
143static struct plat_lcd_data smdk6440_lcd_power_data = {
144 .set_power = smdk6440_lte480_reset_power,
145};
146
147static struct platform_device smdk6440_lcd_lte480wv = {
148 .name = "platform-lcd",
149 .dev.parent = &s3c_device_fb.dev,
150 .dev.platform_data = &smdk6440_lcd_power_data,
151};
152
95static struct platform_device *smdk6440_devices[] __initdata = { 153static struct platform_device *smdk6440_devices[] __initdata = {
96 &s3c_device_adc, 154 &s3c_device_adc,
97 &s3c_device_rtc, 155 &s3c_device_rtc,
@@ -101,6 +159,8 @@ static struct platform_device *smdk6440_devices[] __initdata = {
101 &s3c_device_wdt, 159 &s3c_device_wdt,
102 &samsung_asoc_dma, 160 &samsung_asoc_dma,
103 &s5p6440_device_iis, 161 &s5p6440_device_iis,
162 &s3c_device_fb,
163 &smdk6440_lcd_lte480wv,
104}; 164};
105 165
106static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { 166static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -147,6 +207,17 @@ static void __init smdk6440_map_io(void)
147 s5p_set_timer_source(S5P_PWM3, S5P_PWM4); 207 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
148} 208}
149 209
210static void s5p6440_set_lcd_interface(void)
211{
212 unsigned int cfg;
213
214 /* select TFT LCD type (RGB I/F) */
215 cfg = __raw_readl(S5P64X0_SPCON0);
216 cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
217 cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
218 __raw_writel(cfg, S5P64X0_SPCON0);
219}
220
150static void __init smdk6440_machine_init(void) 221static void __init smdk6440_machine_init(void)
151{ 222{
152 s3c24xx_ts_set_platdata(NULL); 223 s3c24xx_ts_set_platdata(NULL);
@@ -160,6 +231,9 @@ static void __init smdk6440_machine_init(void)
160 231
161 samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data); 232 samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
162 233
234 s5p6440_set_lcd_interface();
235 s3c_fb_set_platdata(&smdk6440_lcd_pdata);
236
163 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); 237 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
164} 238}
165 239
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index ee0da14665b6..2a69caa70afd 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -23,6 +23,9 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h> 25#include <linux/pwm_backlight.h>
26#include <linux/fb.h>
27
28#include <video/platform_lcd.h>
26 29
27#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 31#include <asm/mach/map.h>
@@ -47,6 +50,8 @@
47#include <plat/ts.h> 50#include <plat/ts.h>
48#include <plat/s5p-time.h> 51#include <plat/s5p-time.h>
49#include <plat/backlight.h> 52#include <plat/backlight.h>
53#include <plat/fb.h>
54#include <plat/regs-fb.h>
50 55
51#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 56#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
52 S3C2410_UCON_RXILEVEL | \ 57 S3C2410_UCON_RXILEVEL | \
@@ -110,6 +115,59 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
110#endif 115#endif
111}; 116};
112 117
118/* Frame Buffer */
119static struct s3c_fb_pd_win smdk6450_fb_win0 = {
120 .win_mode = {
121 .left_margin = 8,
122 .right_margin = 13,
123 .upper_margin = 7,
124 .lower_margin = 5,
125 .hsync_len = 3,
126 .vsync_len = 1,
127 .xres = 800,
128 .yres = 480,
129 },
130 .max_bpp = 32,
131 .default_bpp = 24,
132};
133
134static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
135 .win[0] = &smdk6450_fb_win0,
136 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
137 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
138 .setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
139};
140
141/* LCD power controller */
142static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd,
143 unsigned int power)
144{
145 int err;
146
147 if (power) {
148 err = gpio_request(S5P6450_GPN(5), "GPN");
149 if (err) {
150 printk(KERN_ERR "failed to request GPN for lcd reset\n");
151 return;
152 }
153
154 gpio_direction_output(S5P6450_GPN(5), 1);
155 gpio_set_value(S5P6450_GPN(5), 0);
156 gpio_set_value(S5P6450_GPN(5), 1);
157 gpio_free(S5P6450_GPN(5));
158 }
159}
160
161static struct plat_lcd_data smdk6450_lcd_power_data = {
162 .set_power = smdk6450_lte480_reset_power,
163};
164
165static struct platform_device smdk6450_lcd_lte480wv = {
166 .name = "platform-lcd",
167 .dev.parent = &s3c_device_fb.dev,
168 .dev.platform_data = &smdk6450_lcd_power_data,
169};
170
113static struct platform_device *smdk6450_devices[] __initdata = { 171static struct platform_device *smdk6450_devices[] __initdata = {
114 &s3c_device_adc, 172 &s3c_device_adc,
115 &s3c_device_rtc, 173 &s3c_device_rtc,
@@ -119,6 +177,9 @@ static struct platform_device *smdk6450_devices[] __initdata = {
119 &s3c_device_wdt, 177 &s3c_device_wdt,
120 &samsung_asoc_dma, 178 &samsung_asoc_dma,
121 &s5p6450_device_iis0, 179 &s5p6450_device_iis0,
180 &s3c_device_fb,
181 &smdk6450_lcd_lte480wv,
182
122 /* s5p6450_device_spi0 will be added */ 183 /* s5p6450_device_spi0 will be added */
123}; 184};
124 185
@@ -166,6 +227,17 @@ static void __init smdk6450_map_io(void)
166 s5p_set_timer_source(S5P_PWM3, S5P_PWM4); 227 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
167} 228}
168 229
230static void s5p6450_set_lcd_interface(void)
231{
232 unsigned int cfg;
233
234 /* select TFT LCD type (RGB I/F) */
235 cfg = __raw_readl(S5P64X0_SPCON0);
236 cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
237 cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
238 __raw_writel(cfg, S5P64X0_SPCON0);
239}
240
169static void __init smdk6450_machine_init(void) 241static void __init smdk6450_machine_init(void)
170{ 242{
171 s3c24xx_ts_set_platdata(NULL); 243 s3c24xx_ts_set_platdata(NULL);
@@ -179,6 +251,9 @@ static void __init smdk6450_machine_init(void)
179 251
180 samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data); 252 samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
181 253
254 s5p6450_set_lcd_interface();
255 s3c_fb_set_platdata(&smdk6450_lcd_pdata);
256
182 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); 257 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
183} 258}
184 259
diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
new file mode 100644
index 000000000000..f346ee4af54d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
@@ -0,0 +1,29 @@
1/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Base S5P64X0 GPIO setup information for LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/fb.h>
14#include <linux/gpio.h>
15
16#include <plat/cpu.h>
17#include <plat/fb.h>
18#include <plat/gpio-cfg.h>
19
20void s5p64x0_fb_gpio_setup_24bpp(void)
21{
22 if (soc_is_s5p6440()) {
23 s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2));
24 s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2));
25 } else if (soc_is_s5p6450()) {
26 s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2));
27 s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2));
28 }
29}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 16:39:35 -0400