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-rw-r--r--arch/arm/mach-s5p64x0/Kconfig31
-rw-r--r--arch/arm/mach-s5p64x0/Makefile3
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c167
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c155
-rw-r--r--arch/arm/mach-s5p64x0/clock.c2
-rw-r--r--arch/arm/mach-s5p64x0/common.c55
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c224
-rw-r--r--arch/arm/mach-s5p64x0/dma.c227
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c25
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c26
-rw-r--r--arch/arm/mach-s5p64x0/pm.c10
-rw-r--r--arch/arm/mach-s5p64x0/setup-sdhci-gpio.c104
-rw-r--r--arch/arm/mach-s5p64x0/setup-spi.c55
15 files changed, 523 insertions, 565 deletions
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 18690c5f99e6..c87f6108eeb1 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -36,6 +36,16 @@ config S5P64X0_SETUP_I2C1
36 help 36 help
37 Common setup code for i2c bus 1. 37 Common setup code for i2c bus 1.
38 38
39config S5P64X0_SETUP_SPI
40 bool
41 help
42 Common setup code for SPI GPIO configurations
43
44config S5P64X0_SETUP_SDHCI_GPIO
45 bool
46 help
47 Common setup code for SDHCI gpio.
48
39# machine support 49# machine support
40 50
41config MACH_SMDK6440 51config MACH_SMDK6440
@@ -45,13 +55,16 @@ config MACH_SMDK6440
45 select S3C_DEV_I2C1 55 select S3C_DEV_I2C1
46 select S3C_DEV_RTC 56 select S3C_DEV_RTC
47 select S3C_DEV_WDT 57 select S3C_DEV_WDT
48 select S3C64XX_DEV_SPI 58 select S3C_DEV_HSMMC
59 select S3C_DEV_HSMMC1
60 select S3C_DEV_HSMMC2
49 select SAMSUNG_DEV_ADC 61 select SAMSUNG_DEV_ADC
50 select SAMSUNG_DEV_BACKLIGHT 62 select SAMSUNG_DEV_BACKLIGHT
51 select SAMSUNG_DEV_PWM 63 select SAMSUNG_DEV_PWM
52 select SAMSUNG_DEV_TS 64 select SAMSUNG_DEV_TS
53 select S5P64X0_SETUP_FB_24BPP 65 select S5P64X0_SETUP_FB_24BPP
54 select S5P64X0_SETUP_I2C1 66 select S5P64X0_SETUP_I2C1
67 select S5P64X0_SETUP_SDHCI_GPIO
55 help 68 help
56 Machine support for the Samsung SMDK6440 69 Machine support for the Samsung SMDK6440
57 70
@@ -62,14 +75,28 @@ config MACH_SMDK6450
62 select S3C_DEV_I2C1 75 select S3C_DEV_I2C1
63 select S3C_DEV_RTC 76 select S3C_DEV_RTC
64 select S3C_DEV_WDT 77 select S3C_DEV_WDT
65 select S3C64XX_DEV_SPI 78 select S3C_DEV_HSMMC
79 select S3C_DEV_HSMMC1
80 select S3C_DEV_HSMMC2
66 select SAMSUNG_DEV_ADC 81 select SAMSUNG_DEV_ADC
67 select SAMSUNG_DEV_BACKLIGHT 82 select SAMSUNG_DEV_BACKLIGHT
68 select SAMSUNG_DEV_PWM 83 select SAMSUNG_DEV_PWM
69 select SAMSUNG_DEV_TS 84 select SAMSUNG_DEV_TS
70 select S5P64X0_SETUP_FB_24BPP 85 select S5P64X0_SETUP_FB_24BPP
71 select S5P64X0_SETUP_I2C1 86 select S5P64X0_SETUP_I2C1
87 select S5P64X0_SETUP_SDHCI_GPIO
72 help 88 help
73 Machine support for the Samsung SMDK6450 89 Machine support for the Samsung SMDK6450
74 90
91menu "Use 8-bit SDHCI bus width"
92
93config S5P64X0_SD_CH1_8BIT
94 bool "SDHCI Channel 1 (Slot 1)"
95 depends on MACH_SMDK6450 || MACH_SMDK6440
96 help
97 Support SDHCI Channel 1 8-bit bus.
98 If selected, Channel 2 is disabled.
99
100endmenu
101
75endif 102endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index d3f7409999f2..12bb951187a4 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -28,8 +28,9 @@ obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
28# device support 28# device support
29 29
30obj-y += dev-audio.o 30obj-y += dev-audio.o
31obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
32 31
33obj-y += setup-i2c0.o 32obj-y += setup-i2c0.o
34obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o 33obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
35obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o 34obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
35obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
36obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index dd2b8daef0cd..ee1e8e7f5631 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -17,7 +17,7 @@
17#include <linux/errno.h> 17#include <linux/errno.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/sysdev.h> 20#include <linux/device.h>
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
@@ -269,18 +269,6 @@ static struct clk init_clocks_off[] = {
269 .enable = s5p64x0_pclk_ctrl, 269 .enable = s5p64x0_pclk_ctrl,
270 .ctrlbit = (1 << 31), 270 .ctrlbit = (1 << 31),
271 }, { 271 }, {
272 .name = "sclk_spi_48",
273 .devname = "s3c64xx-spi.0",
274 .parent = &clk_48m,
275 .enable = s5p64x0_sclk_ctrl,
276 .ctrlbit = (1 << 22),
277 }, {
278 .name = "sclk_spi_48",
279 .devname = "s3c64xx-spi.1",
280 .parent = &clk_48m,
281 .enable = s5p64x0_sclk_ctrl,
282 .ctrlbit = (1 << 23),
283 }, {
284 .name = "mmc_48m", 272 .name = "mmc_48m",
285 .devname = "s3c-sdhci.0", 273 .devname = "s3c-sdhci.0",
286 .parent = &clk_48m, 274 .parent = &clk_48m,
@@ -392,65 +380,6 @@ static struct clksrc_sources clkset_audio = {
392static struct clksrc_clk clksrcs[] = { 380static struct clksrc_clk clksrcs[] = {
393 { 381 {
394 .clk = { 382 .clk = {
395 .name = "sclk_mmc",
396 .devname = "s3c-sdhci.0",
397 .ctrlbit = (1 << 24),
398 .enable = s5p64x0_sclk_ctrl,
399 },
400 .sources = &clkset_group1,
401 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
402 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
403 }, {
404 .clk = {
405 .name = "sclk_mmc",
406 .devname = "s3c-sdhci.1",
407 .ctrlbit = (1 << 25),
408 .enable = s5p64x0_sclk_ctrl,
409 },
410 .sources = &clkset_group1,
411 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
412 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
413 }, {
414 .clk = {
415 .name = "sclk_mmc",
416 .devname = "s3c-sdhci.2",
417 .ctrlbit = (1 << 26),
418 .enable = s5p64x0_sclk_ctrl,
419 },
420 .sources = &clkset_group1,
421 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
422 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
423 }, {
424 .clk = {
425 .name = "uclk1",
426 .ctrlbit = (1 << 5),
427 .enable = s5p64x0_sclk_ctrl,
428 },
429 .sources = &clkset_uart,
430 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
431 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
432 }, {
433 .clk = {
434 .name = "sclk_spi",
435 .devname = "s3c64xx-spi.0",
436 .ctrlbit = (1 << 20),
437 .enable = s5p64x0_sclk_ctrl,
438 },
439 .sources = &clkset_group1,
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
442 }, {
443 .clk = {
444 .name = "sclk_spi",
445 .devname = "s3c64xx-spi.1",
446 .ctrlbit = (1 << 21),
447 .enable = s5p64x0_sclk_ctrl,
448 },
449 .sources = &clkset_group1,
450 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
451 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
452 }, {
453 .clk = {
454 .name = "sclk_post", 383 .name = "sclk_post",
455 .ctrlbit = (1 << 10), 384 .ctrlbit = (1 << 10),
456 .enable = s5p64x0_sclk_ctrl, 385 .enable = s5p64x0_sclk_ctrl,
@@ -488,6 +417,77 @@ static struct clksrc_clk clksrcs[] = {
488 }, 417 },
489}; 418};
490 419
420static struct clksrc_clk clk_sclk_mmc0 = {
421 .clk = {
422 .name = "sclk_mmc",
423 .devname = "s3c-sdhci.0",
424 .ctrlbit = (1 << 24),
425 .enable = s5p64x0_sclk_ctrl,
426 },
427 .sources = &clkset_group1,
428 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
430};
431
432static struct clksrc_clk clk_sclk_mmc1 = {
433 .clk = {
434 .name = "sclk_mmc",
435 .devname = "s3c-sdhci.1",
436 .ctrlbit = (1 << 25),
437 .enable = s5p64x0_sclk_ctrl,
438 },
439 .sources = &clkset_group1,
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
442};
443
444static struct clksrc_clk clk_sclk_mmc2 = {
445 .clk = {
446 .name = "sclk_mmc",
447 .devname = "s3c-sdhci.2",
448 .ctrlbit = (1 << 26),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_group1,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
454};
455
456static struct clksrc_clk clk_sclk_uclk = {
457 .clk = {
458 .name = "uclk1",
459 .ctrlbit = (1 << 5),
460 .enable = s5p64x0_sclk_ctrl,
461 },
462 .sources = &clkset_uart,
463 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
464 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
465};
466
467static struct clksrc_clk clk_sclk_spi0 = {
468 .clk = {
469 .name = "sclk_spi",
470 .devname = "s3c64xx-spi.0",
471 .ctrlbit = (1 << 20),
472 .enable = s5p64x0_sclk_ctrl,
473 },
474 .sources = &clkset_group1,
475 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
476 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
477};
478
479static struct clksrc_clk clk_sclk_spi1 = {
480 .clk = {
481 .name = "sclk_spi",
482 .devname = "s3c64xx-spi.1",
483 .ctrlbit = (1 << 21),
484 .enable = s5p64x0_sclk_ctrl,
485 },
486 .sources = &clkset_group1,
487 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
488 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
489};
490
491/* Clock initialization code */ 491/* Clock initialization code */
492static struct clksrc_clk *sysclks[] = { 492static struct clksrc_clk *sysclks[] = {
493 &clk_mout_apll, 493 &clk_mout_apll,
@@ -506,6 +506,26 @@ static struct clk dummy_apb_pclk = {
506 .id = -1, 506 .id = -1,
507}; 507};
508 508
509static struct clksrc_clk *clksrc_cdev[] = {
510 &clk_sclk_uclk,
511 &clk_sclk_spi0,
512 &clk_sclk_spi1,
513 &clk_sclk_mmc0,
514 &clk_sclk_mmc1,
515 &clk_sclk_mmc2
516};
517
518static struct clk_lookup s5p6440_clk_lookup[] = {
519 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
520 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
521 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
522 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
523 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
524 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
525 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
526 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
527};
528
509void __init_or_cpufreq s5p6440_setup_clocks(void) 529void __init_or_cpufreq s5p6440_setup_clocks(void)
510{ 530{
511 struct clk *xtal_clk; 531 struct clk *xtal_clk;
@@ -584,9 +604,12 @@ void __init s5p6440_register_clocks(void)
584 604
585 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 605 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
586 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 606 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
607 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
608 s3c_register_clksrc(clksrc_cdev[ptr], 1);
587 609
588 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 610 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
589 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 611 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
612 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
590 613
591 s3c24xx_register_clock(&dummy_apb_pclk); 614 s3c24xx_register_clock(&dummy_apb_pclk);
592 615
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 328a224f0075..dae6a13f43bb 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -17,7 +17,7 @@
17#include <linux/errno.h> 17#include <linux/errno.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/sysdev.h> 20#include <linux/device.h>
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
@@ -414,65 +414,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
414static struct clksrc_clk clksrcs[] = { 414static struct clksrc_clk clksrcs[] = {
415 { 415 {
416 .clk = { 416 .clk = {
417 .name = "sclk_mmc",
418 .devname = "s3c-sdhci.0",
419 .ctrlbit = (1 << 24),
420 .enable = s5p64x0_sclk_ctrl,
421 },
422 .sources = &clkset_group2,
423 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
424 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
425 }, {
426 .clk = {
427 .name = "sclk_mmc",
428 .devname = "s3c-sdhci.1",
429 .ctrlbit = (1 << 25),
430 .enable = s5p64x0_sclk_ctrl,
431 },
432 .sources = &clkset_group2,
433 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
434 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
435 }, {
436 .clk = {
437 .name = "sclk_mmc",
438 .devname = "s3c-sdhci.2",
439 .ctrlbit = (1 << 26),
440 .enable = s5p64x0_sclk_ctrl,
441 },
442 .sources = &clkset_group2,
443 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
444 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
445 }, {
446 .clk = {
447 .name = "uclk1",
448 .ctrlbit = (1 << 5),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_uart,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
454 }, {
455 .clk = {
456 .name = "sclk_spi",
457 .devname = "s3c64xx-spi.0",
458 .ctrlbit = (1 << 20),
459 .enable = s5p64x0_sclk_ctrl,
460 },
461 .sources = &clkset_group2,
462 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
463 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
464 }, {
465 .clk = {
466 .name = "sclk_spi",
467 .devname = "s3c64xx-spi.1",
468 .ctrlbit = (1 << 21),
469 .enable = s5p64x0_sclk_ctrl,
470 },
471 .sources = &clkset_group2,
472 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
473 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
474 }, {
475 .clk = {
476 .name = "sclk_fimc", 417 .name = "sclk_fimc",
477 .ctrlbit = (1 << 10), 418 .ctrlbit = (1 << 10),
478 .enable = s5p64x0_sclk_ctrl, 419 .enable = s5p64x0_sclk_ctrl,
@@ -537,6 +478,97 @@ static struct clksrc_clk clksrcs[] = {
537 }, 478 },
538}; 479};
539 480
481static struct clksrc_clk clk_sclk_mmc0 = {
482 .clk = {
483 .name = "sclk_mmc",
484 .devname = "s3c-sdhci.0",
485 .ctrlbit = (1 << 24),
486 .enable = s5p64x0_sclk_ctrl,
487 },
488 .sources = &clkset_group2,
489 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
490 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
491};
492
493static struct clksrc_clk clk_sclk_mmc1 = {
494 .clk = {
495 .name = "sclk_mmc",
496 .devname = "s3c-sdhci.1",
497 .ctrlbit = (1 << 25),
498 .enable = s5p64x0_sclk_ctrl,
499 },
500 .sources = &clkset_group2,
501 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
502 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
503};
504
505static struct clksrc_clk clk_sclk_mmc2 = {
506 .clk = {
507 .name = "sclk_mmc",
508 .devname = "s3c-sdhci.2",
509 .ctrlbit = (1 << 26),
510 .enable = s5p64x0_sclk_ctrl,
511 },
512 .sources = &clkset_group2,
513 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
514 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
515};
516
517static struct clksrc_clk clk_sclk_uclk = {
518 .clk = {
519 .name = "uclk1",
520 .ctrlbit = (1 << 5),
521 .enable = s5p64x0_sclk_ctrl,
522 },
523 .sources = &clkset_uart,
524 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
525 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
526};
527
528static struct clksrc_clk clk_sclk_spi0 = {
529 .clk = {
530 .name = "sclk_spi",
531 .devname = "s3c64xx-spi.0",
532 .ctrlbit = (1 << 20),
533 .enable = s5p64x0_sclk_ctrl,
534 },
535 .sources = &clkset_group2,
536 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
537 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
538};
539
540static struct clksrc_clk clk_sclk_spi1 = {
541 .clk = {
542 .name = "sclk_spi",
543 .devname = "s3c64xx-spi.1",
544 .ctrlbit = (1 << 21),
545 .enable = s5p64x0_sclk_ctrl,
546 },
547 .sources = &clkset_group2,
548 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
549 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
550};
551
552static struct clksrc_clk *clksrc_cdev[] = {
553 &clk_sclk_uclk,
554 &clk_sclk_spi0,
555 &clk_sclk_spi1,
556 &clk_sclk_mmc0,
557 &clk_sclk_mmc1,
558 &clk_sclk_mmc2,
559};
560
561static struct clk_lookup s5p6450_clk_lookup[] = {
562 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
563 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
564 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
565 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
566 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
567 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
568 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
569 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
570};
571
540/* Clock initialization code */ 572/* Clock initialization code */
541static struct clksrc_clk *sysclks[] = { 573static struct clksrc_clk *sysclks[] = {
542 &clk_mout_apll, 574 &clk_mout_apll,
@@ -635,9 +667,12 @@ void __init s5p6450_register_clocks(void)
635 667
636 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 668 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
637 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 669 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
670 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
671 s3c_register_clksrc(clksrc_cdev[ptr], 1);
638 672
639 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 673 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
640 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 674 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
675 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
641 676
642 s3c24xx_register_clock(&dummy_apb_pclk); 677 s3c24xx_register_clock(&dummy_apb_pclk);
643 678
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index b289b726a7d6..241d0e645c85 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -17,7 +17,7 @@
17#include <linux/errno.h> 17#include <linux/errno.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/sysdev.h> 20#include <linux/device.h>
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index b7555a0fb0fb..52b89a376447 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -17,7 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/sysdev.h> 20#include <linux/device.h>
21#include <linux/serial_core.h> 21#include <linux/serial_core.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/sched.h> 23#include <linux/sched.h>
@@ -40,6 +40,7 @@
40#include <plat/clock.h> 40#include <plat/clock.h>
41#include <plat/devs.h> 41#include <plat/devs.h>
42#include <plat/pm.h> 42#include <plat/pm.h>
43#include <plat/sdhci.h>
43#include <plat/adc-core.h> 44#include <plat/adc-core.h>
44#include <plat/fb-core.h> 45#include <plat/fb-core.h>
45#include <plat/gpio-cfg.h> 46#include <plat/gpio-cfg.h>
@@ -181,6 +182,10 @@ void __init s5p6440_map_io(void)
181 s3c_adc_setname("s3c64xx-adc"); 182 s3c_adc_setname("s3c64xx-adc");
182 s3c_fb_setname("s5p64x0-fb"); 183 s3c_fb_setname("s5p64x0-fb");
183 184
185 s5p64x0_default_sdhci0();
186 s5p64x0_default_sdhci1();
187 s5p6440_default_sdhci2();
188
184 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); 189 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
185 init_consistent_dma_size(SZ_8M); 190 init_consistent_dma_size(SZ_8M);
186} 191}
@@ -191,6 +196,10 @@ void __init s5p6450_map_io(void)
191 s3c_adc_setname("s3c64xx-adc"); 196 s3c_adc_setname("s3c64xx-adc");
192 s3c_fb_setname("s5p64x0-fb"); 197 s3c_fb_setname("s5p64x0-fb");
193 198
199 s5p64x0_default_sdhci0();
200 s5p64x0_default_sdhci1();
201 s5p6450_default_sdhci2();
202
194 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); 203 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
195 init_consistent_dma_size(SZ_8M); 204 init_consistent_dma_size(SZ_8M);
196} 205}
@@ -257,17 +266,18 @@ void __init s5p6450_init_irq(void)
257 s5p_init_irq(vic, ARRAY_SIZE(vic)); 266 s5p_init_irq(vic, ARRAY_SIZE(vic));
258} 267}
259 268
260struct sysdev_class s5p64x0_sysclass = { 269struct bus_type s5p64x0_subsys = {
261 .name = "s5p64x0-core", 270 .name = "s5p64x0-core",
271 .dev_name = "s5p64x0-core",
262}; 272};
263 273
264static struct sys_device s5p64x0_sysdev = { 274static struct device s5p64x0_dev = {
265 .cls = &s5p64x0_sysclass, 275 .bus = &s5p64x0_subsys,
266}; 276};
267 277
268static int __init s5p64x0_core_init(void) 278static int __init s5p64x0_core_init(void)
269{ 279{
270 return sysdev_class_register(&s5p64x0_sysclass); 280 return subsys_system_register(&s5p64x0_subsys, NULL);
271} 281}
272core_initcall(s5p64x0_core_init); 282core_initcall(s5p64x0_core_init);
273 283
@@ -278,39 +288,10 @@ int __init s5p64x0_init(void)
278 /* set idle function */ 288 /* set idle function */
279 pm_idle = s5p64x0_idle; 289 pm_idle = s5p64x0_idle;
280 290
281 return sysdev_register(&s5p64x0_sysdev); 291 return device_register(&s5p64x0_dev);
282} 292}
283 293
284static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
285 [0] = {
286 .name = "pclk_low",
287 .divisor = 1,
288 .min_baud = 0,
289 .max_baud = 0,
290 },
291 [1] = {
292 .name = "uclk1",
293 .divisor = 1,
294 .min_baud = 0,
295 .max_baud = 0,
296 },
297};
298
299/* uart registration process */ 294/* uart registration process */
300
301void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
302{
303 struct s3c2410_uartcfg *tcfg = cfg;
304 u32 ucnt;
305
306 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
307 if (!tcfg->clocks) {
308 tcfg->clocks = s5p64x0_serial_clocks;
309 tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
310 }
311 }
312}
313
314void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) 295void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
315{ 296{
316 int uart; 297 int uart;
@@ -320,13 +301,11 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
320 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART; 301 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
321 } 302 }
322 303
323 s5p64x0_common_init_uarts(cfg, no);
324 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); 304 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
325} 305}
326 306
327void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no) 307void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
328{ 308{
329 s5p64x0_common_init_uarts(cfg, no);
330 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); 309 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
331} 310}
332 311
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
deleted file mode 100644
index 1fd9c79c7dbc..000000000000
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dev-spi.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/irqs.h>
21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h>
23
24#include <plat/cpu.h>
25#include <plat/s3c64xx-spi.h>
26#include <plat/gpio-cfg.h>
27
28static char *s5p64x0_spi_src_clks[] = {
29 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
30 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the CS.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S5P6440_GPC(0);
48 break;
49
50 case 1:
51 base = S5P6440_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
66{
67 unsigned int base;
68
69 switch (pdev->id) {
70 case 0:
71 base = S5P6450_GPC(0);
72 break;
73
74 case 1:
75 base = S5P6450_GPC(4);
76 break;
77
78 default:
79 dev_err(&pdev->dev, "Invalid SPI Controller number!");
80 return -EINVAL;
81 }
82
83 s3c_gpio_cfgall_range(base, 3,
84 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
85
86 return 0;
87}
88
89static struct resource s5p64x0_spi0_resource[] = {
90 [0] = {
91 .start = S5P64X0_PA_SPI0,
92 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = DMACH_SPI0_TX,
97 .end = DMACH_SPI0_TX,
98 .flags = IORESOURCE_DMA,
99 },
100 [2] = {
101 .start = DMACH_SPI0_RX,
102 .end = DMACH_SPI0_RX,
103 .flags = IORESOURCE_DMA,
104 },
105 [3] = {
106 .start = IRQ_SPI0,
107 .end = IRQ_SPI0,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
113 .cfg_gpio = s5p6440_spi_cfg_gpio,
114 .fifo_lvl_mask = 0x1ff,
115 .rx_lvl_offset = 15,
116 .tx_st_done = 25,
117};
118
119static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
120 .cfg_gpio = s5p6450_spi_cfg_gpio,
121 .fifo_lvl_mask = 0x1ff,
122 .rx_lvl_offset = 15,
123 .tx_st_done = 25,
124};
125
126static u64 spi_dmamask = DMA_BIT_MASK(32);
127
128struct platform_device s5p64x0_device_spi0 = {
129 .name = "s3c64xx-spi",
130 .id = 0,
131 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
132 .resource = s5p64x0_spi0_resource,
133 .dev = {
134 .dma_mask = &spi_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137};
138
139static struct resource s5p64x0_spi1_resource[] = {
140 [0] = {
141 .start = S5P64X0_PA_SPI1,
142 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = DMACH_SPI1_TX,
147 .end = DMACH_SPI1_TX,
148 .flags = IORESOURCE_DMA,
149 },
150 [2] = {
151 .start = DMACH_SPI1_RX,
152 .end = DMACH_SPI1_RX,
153 .flags = IORESOURCE_DMA,
154 },
155 [3] = {
156 .start = IRQ_SPI1,
157 .end = IRQ_SPI1,
158 .flags = IORESOURCE_IRQ,
159 },
160};
161
162static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
163 .cfg_gpio = s5p6440_spi_cfg_gpio,
164 .fifo_lvl_mask = 0x7f,
165 .rx_lvl_offset = 15,
166 .tx_st_done = 25,
167};
168
169static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
170 .cfg_gpio = s5p6450_spi_cfg_gpio,
171 .fifo_lvl_mask = 0x7f,
172 .rx_lvl_offset = 15,
173 .tx_st_done = 25,
174};
175
176struct platform_device s5p64x0_device_spi1 = {
177 .name = "s3c64xx-spi",
178 .id = 1,
179 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
180 .resource = s5p64x0_spi1_resource,
181 .dev = {
182 .dma_mask = &spi_dmamask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
184 },
185};
186
187void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
188{
189 struct s3c64xx_spi_info *pd;
190
191 /* Reject invalid configuration */
192 if (!num_cs || src_clk_nr < 0
193 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
194 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
195 return;
196 }
197
198 switch (cntrlr) {
199 case 0:
200 if (soc_is_s5p6450())
201 pd = &s5p6450_spi0_pdata;
202 else
203 pd = &s5p6440_spi0_pdata;
204
205 s5p64x0_device_spi0.dev.platform_data = pd;
206 break;
207 case 1:
208 if (soc_is_s5p6450())
209 pd = &s5p6450_spi1_pdata;
210 else
211 pd = &s5p6440_spi1_pdata;
212
213 s5p64x0_device_spi1.dev.platform_data = pd;
214 break;
215 default:
216 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
217 __func__, cntrlr);
218 return;
219 }
220
221 pd->num_cs = num_cs;
222 pd->src_clk_nr = src_clk_nr;
223 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
224}
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 442dd4ad12da..f820c0744405 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,176 +38,74 @@
38 38
39static u64 dma_dmamask = DMA_BIT_MASK(32); 39static u64 dma_dmamask = DMA_BIT_MASK(32);
40 40
41struct dma_pl330_peri s5p6440_pdma_peri[22] = { 41u8 s5p6440_pdma_peri[] = {
42 { 42 DMACH_UART0_RX,
43 .peri_id = (u8)DMACH_UART0_RX, 43 DMACH_UART0_TX,
44 .rqtype = DEVTOMEM, 44 DMACH_UART1_RX,
45 }, { 45 DMACH_UART1_TX,
46 .peri_id = (u8)DMACH_UART0_TX, 46 DMACH_UART2_RX,
47 .rqtype = MEMTODEV, 47 DMACH_UART2_TX,
48 }, { 48 DMACH_UART3_RX,
49 .peri_id = (u8)DMACH_UART1_RX, 49 DMACH_UART3_TX,
50 .rqtype = DEVTOMEM, 50 DMACH_MAX,
51 }, { 51 DMACH_MAX,
52 .peri_id = (u8)DMACH_UART1_TX, 52 DMACH_PCM0_TX,
53 .rqtype = MEMTODEV, 53 DMACH_PCM0_RX,
54 }, { 54 DMACH_I2S0_TX,
55 .peri_id = (u8)DMACH_UART2_RX, 55 DMACH_I2S0_RX,
56 .rqtype = DEVTOMEM, 56 DMACH_SPI0_TX,
57 }, { 57 DMACH_SPI0_RX,
58 .peri_id = (u8)DMACH_UART2_TX, 58 DMACH_MAX,
59 .rqtype = MEMTODEV, 59 DMACH_MAX,
60 }, { 60 DMACH_MAX,
61 .peri_id = (u8)DMACH_UART3_RX, 61 DMACH_MAX,
62 .rqtype = DEVTOMEM, 62 DMACH_SPI1_TX,
63 }, { 63 DMACH_SPI1_RX,
64 .peri_id = (u8)DMACH_UART3_TX,
65 .rqtype = MEMTODEV,
66 }, {
67 .peri_id = DMACH_MAX,
68 }, {
69 .peri_id = DMACH_MAX,
70 }, {
71 .peri_id = (u8)DMACH_PCM0_TX,
72 .rqtype = MEMTODEV,
73 }, {
74 .peri_id = (u8)DMACH_PCM0_RX,
75 .rqtype = DEVTOMEM,
76 }, {
77 .peri_id = (u8)DMACH_I2S0_TX,
78 .rqtype = MEMTODEV,
79 }, {
80 .peri_id = (u8)DMACH_I2S0_RX,
81 .rqtype = DEVTOMEM,
82 }, {
83 .peri_id = (u8)DMACH_SPI0_TX,
84 .rqtype = MEMTODEV,
85 }, {
86 .peri_id = (u8)DMACH_SPI0_RX,
87 .rqtype = DEVTOMEM,
88 }, {
89 .peri_id = (u8)DMACH_MAX,
90 }, {
91 .peri_id = (u8)DMACH_MAX,
92 }, {
93 .peri_id = (u8)DMACH_MAX,
94 }, {
95 .peri_id = (u8)DMACH_MAX,
96 }, {
97 .peri_id = (u8)DMACH_SPI1_TX,
98 .rqtype = MEMTODEV,
99 }, {
100 .peri_id = (u8)DMACH_SPI1_RX,
101 .rqtype = DEVTOMEM,
102 },
103}; 64};
104 65
105struct dma_pl330_platdata s5p6440_pdma_pdata = { 66struct dma_pl330_platdata s5p6440_pdma_pdata = {
106 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), 67 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
107 .peri = s5p6440_pdma_peri, 68 .peri_id = s5p6440_pdma_peri,
108}; 69};
109 70
110struct dma_pl330_peri s5p6450_pdma_peri[32] = { 71u8 s5p6450_pdma_peri[] = {
111 { 72 DMACH_UART0_RX,
112 .peri_id = (u8)DMACH_UART0_RX, 73 DMACH_UART0_TX,
113 .rqtype = DEVTOMEM, 74 DMACH_UART1_RX,
114 }, { 75 DMACH_UART1_TX,
115 .peri_id = (u8)DMACH_UART0_TX, 76 DMACH_UART2_RX,
116 .rqtype = MEMTODEV, 77 DMACH_UART2_TX,
117 }, { 78 DMACH_UART3_RX,
118 .peri_id = (u8)DMACH_UART1_RX, 79 DMACH_UART3_TX,
119 .rqtype = DEVTOMEM, 80 DMACH_UART4_RX,
120 }, { 81 DMACH_UART4_TX,
121 .peri_id = (u8)DMACH_UART1_TX, 82 DMACH_PCM0_TX,
122 .rqtype = MEMTODEV, 83 DMACH_PCM0_RX,
123 }, { 84 DMACH_I2S0_TX,
124 .peri_id = (u8)DMACH_UART2_RX, 85 DMACH_I2S0_RX,
125 .rqtype = DEVTOMEM, 86 DMACH_SPI0_TX,
126 }, { 87 DMACH_SPI0_RX,
127 .peri_id = (u8)DMACH_UART2_TX, 88 DMACH_PCM1_TX,
128 .rqtype = MEMTODEV, 89 DMACH_PCM1_RX,
129 }, { 90 DMACH_PCM2_TX,
130 .peri_id = (u8)DMACH_UART3_RX, 91 DMACH_PCM2_RX,
131 .rqtype = DEVTOMEM, 92 DMACH_SPI1_TX,
132 }, { 93 DMACH_SPI1_RX,
133 .peri_id = (u8)DMACH_UART3_TX, 94 DMACH_USI_TX,
134 .rqtype = MEMTODEV, 95 DMACH_USI_RX,
135 }, { 96 DMACH_MAX,
136 .peri_id = (u8)DMACH_UART4_RX, 97 DMACH_I2S1_TX,
137 .rqtype = DEVTOMEM, 98 DMACH_I2S1_RX,
138 }, { 99 DMACH_I2S2_TX,
139 .peri_id = (u8)DMACH_UART4_TX, 100 DMACH_I2S2_RX,
140 .rqtype = MEMTODEV, 101 DMACH_PWM,
141 }, { 102 DMACH_UART5_RX,
142 .peri_id = (u8)DMACH_PCM0_TX, 103 DMACH_UART5_TX,
143 .rqtype = MEMTODEV,
144 }, {
145 .peri_id = (u8)DMACH_PCM0_RX,
146 .rqtype = DEVTOMEM,
147 }, {
148 .peri_id = (u8)DMACH_I2S0_TX,
149 .rqtype = MEMTODEV,
150 }, {
151 .peri_id = (u8)DMACH_I2S0_RX,
152 .rqtype = DEVTOMEM,
153 }, {
154 .peri_id = (u8)DMACH_SPI0_TX,
155 .rqtype = MEMTODEV,
156 }, {
157 .peri_id = (u8)DMACH_SPI0_RX,
158 .rqtype = DEVTOMEM,
159 }, {
160 .peri_id = (u8)DMACH_PCM1_TX,
161 .rqtype = MEMTODEV,
162 }, {
163 .peri_id = (u8)DMACH_PCM1_RX,
164 .rqtype = DEVTOMEM,
165 }, {
166 .peri_id = (u8)DMACH_PCM2_TX,
167 .rqtype = MEMTODEV,
168 }, {
169 .peri_id = (u8)DMACH_PCM2_RX,
170 .rqtype = DEVTOMEM,
171 }, {
172 .peri_id = (u8)DMACH_SPI1_TX,
173 .rqtype = MEMTODEV,
174 }, {
175 .peri_id = (u8)DMACH_SPI1_RX,
176 .rqtype = DEVTOMEM,
177 }, {
178 .peri_id = (u8)DMACH_USI_TX,
179 .rqtype = MEMTODEV,
180 }, {
181 .peri_id = (u8)DMACH_USI_RX,
182 .rqtype = DEVTOMEM,
183 }, {
184 .peri_id = (u8)DMACH_MAX,
185 }, {
186 .peri_id = (u8)DMACH_I2S1_TX,
187 .rqtype = MEMTODEV,
188 }, {
189 .peri_id = (u8)DMACH_I2S1_RX,
190 .rqtype = DEVTOMEM,
191 }, {
192 .peri_id = (u8)DMACH_I2S2_TX,
193 .rqtype = MEMTODEV,
194 }, {
195 .peri_id = (u8)DMACH_I2S2_RX,
196 .rqtype = DEVTOMEM,
197 }, {
198 .peri_id = (u8)DMACH_PWM,
199 }, {
200 .peri_id = (u8)DMACH_UART5_RX,
201 .rqtype = DEVTOMEM,
202 }, {
203 .peri_id = (u8)DMACH_UART5_TX,
204 .rqtype = MEMTODEV,
205 },
206}; 104};
207 105
208struct dma_pl330_platdata s5p6450_pdma_pdata = { 106struct dma_pl330_platdata s5p6450_pdma_pdata = {
209 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), 107 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
210 .peri = s5p6450_pdma_peri, 108 .peri_id = s5p6450_pdma_peri,
211}; 109};
212 110
213struct amba_device s5p64x0_device_pdma = { 111struct amba_device s5p64x0_device_pdma = {
@@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = {
227 125
228static int __init s5p64x0_dma_init(void) 126static int __init s5p64x0_dma_init(void)
229{ 127{
230 if (soc_is_s5p6450()) 128 if (soc_is_s5p6450()) {
129 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
130 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
231 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; 131 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
232 else 132 } else {
133 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
134 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
233 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 135 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
136 }
234 137
235 amba_device_register(&s5p64x0_device_pdma, &iomem_resource); 138 amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
236 139
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 53982db9d259..5b845e849b30 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -141,6 +141,8 @@
141 141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) 142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143 143
144#define IRQ_TIMER_BASE (11)
145
144/* Set the default NR_IRQS */ 146/* Set the default NR_IRQS */
145 147
146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) 148#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 4d3ac8a3709d..0c0175dbfa34 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -67,6 +67,8 @@
67#define S3C_PA_RTC S5P64X0_PA_RTC 67#define S3C_PA_RTC S5P64X0_PA_RTC
68#define S3C_PA_WDT S5P64X0_PA_WDT 68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB 69#define S3C_PA_FB S5P64X0_PA_FB
70#define S3C_PA_SPI0 S5P64X0_PA_SPI0
71#define S3C_PA_SPI1 S5P64X0_PA_SPI1
70 72
71#define S5P_PA_CHIPID S5P64X0_PA_CHIPID 73#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
72#define S5P_PA_SROMC S5P64X0_PA_SROMC 74#define S5P_PA_SROMC S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 34d98a1dae57..a40e325d62c8 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -24,6 +24,7 @@
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h> 25#include <linux/pwm_backlight.h>
26#include <linux/fb.h> 26#include <linux/fb.h>
27#include <linux/mmc/host.h>
27 28
28#include <video/platform_lcd.h> 29#include <video/platform_lcd.h>
29 30
@@ -52,6 +53,7 @@
52#include <plat/backlight.h> 53#include <plat/backlight.h>
53#include <plat/fb.h> 54#include <plat/fb.h>
54#include <plat/regs-fb.h> 55#include <plat/regs-fb.h>
56#include <plat/sdhci.h>
55 57
56#include "common.h" 58#include "common.h"
57 59
@@ -163,6 +165,25 @@ static struct platform_device *smdk6440_devices[] __initdata = {
163 &s5p6440_device_iis, 165 &s5p6440_device_iis,
164 &s3c_device_fb, 166 &s3c_device_fb,
165 &smdk6440_lcd_lte480wv, 167 &smdk6440_lcd_lte480wv,
168 &s3c_device_hsmmc0,
169 &s3c_device_hsmmc1,
170 &s3c_device_hsmmc2,
171};
172
173static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
174 .cd_type = S3C_SDHCI_CD_NONE,
175};
176
177static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
178 .cd_type = S3C_SDHCI_CD_INTERNAL,
179#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
180 .max_width = 8,
181 .host_caps = MMC_CAP_8_BIT_DATA,
182#endif
183};
184
185static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
186 .cd_type = S3C_SDHCI_CD_NONE,
166}; 187};
167 188
168static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { 189static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -236,6 +257,10 @@ static void __init smdk6440_machine_init(void)
236 s5p6440_set_lcd_interface(); 257 s5p6440_set_lcd_interface();
237 s3c_fb_set_platdata(&smdk6440_lcd_pdata); 258 s3c_fb_set_platdata(&smdk6440_lcd_pdata);
238 259
260 s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
261 s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
262 s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
263
239 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); 264 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
240} 265}
241 266
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 135cf5d84737..efb69e2f2afe 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -24,6 +24,7 @@
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h> 25#include <linux/pwm_backlight.h>
26#include <linux/fb.h> 26#include <linux/fb.h>
27#include <linux/mmc/host.h>
27 28
28#include <video/platform_lcd.h> 29#include <video/platform_lcd.h>
29 30
@@ -52,6 +53,7 @@
52#include <plat/backlight.h> 53#include <plat/backlight.h>
53#include <plat/fb.h> 54#include <plat/fb.h>
54#include <plat/regs-fb.h> 55#include <plat/regs-fb.h>
56#include <plat/sdhci.h>
55 57
56#include "common.h" 58#include "common.h"
57 59
@@ -181,10 +183,28 @@ static struct platform_device *smdk6450_devices[] __initdata = {
181 &s5p6450_device_iis0, 183 &s5p6450_device_iis0,
182 &s3c_device_fb, 184 &s3c_device_fb,
183 &smdk6450_lcd_lte480wv, 185 &smdk6450_lcd_lte480wv,
184 186 &s3c_device_hsmmc0,
187 &s3c_device_hsmmc1,
188 &s3c_device_hsmmc2,
185 /* s5p6450_device_spi0 will be added */ 189 /* s5p6450_device_spi0 will be added */
186}; 190};
187 191
192static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
193 .cd_type = S3C_SDHCI_CD_NONE,
194};
195
196static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
197 .cd_type = S3C_SDHCI_CD_NONE,
198#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
199 .max_width = 8,
200 .host_caps = MMC_CAP_8_BIT_DATA,
201#endif
202};
203
204static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
205 .cd_type = S3C_SDHCI_CD_NONE,
206};
207
188static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = { 208static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
189 .flags = 0, 209 .flags = 0,
190 .slave_addr = 0x10, 210 .slave_addr = 0x10,
@@ -256,6 +276,10 @@ static void __init smdk6450_machine_init(void)
256 s5p6450_set_lcd_interface(); 276 s5p6450_set_lcd_interface();
257 s3c_fb_set_platdata(&smdk6450_lcd_pdata); 277 s3c_fb_set_platdata(&smdk6450_lcd_pdata);
258 278
279 s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
280 s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
281 s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
282
259 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); 283 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
260} 284}
261 285
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 69927243d25f..23f9b22439c9 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void)
160 160
161} 161}
162 162
163static int s5p64x0_pm_add(struct sys_device *sysdev) 163static int s5p64x0_pm_add(struct device *dev)
164{ 164{
165 pm_cpu_prep = s5p64x0_pm_prepare; 165 pm_cpu_prep = s5p64x0_pm_prepare;
166 pm_cpu_sleep = s5p64x0_cpu_suspend; 166 pm_cpu_sleep = s5p64x0_cpu_suspend;
@@ -169,15 +169,17 @@ static int s5p64x0_pm_add(struct sys_device *sysdev)
169 return 0; 169 return 0;
170} 170}
171 171
172static struct sysdev_driver s5p64x0_pm_driver = { 172static struct subsys_interface s5p64x0_pm_interface = {
173 .add = s5p64x0_pm_add, 173 .name = "s5p64x0_pm",
174 .subsys = &s5p64x0_subsys,
175 .add_dev = s5p64x0_pm_add,
174}; 176};
175 177
176static __init int s5p64x0_pm_drvinit(void) 178static __init int s5p64x0_pm_drvinit(void)
177{ 179{
178 s3c_pm_init(); 180 s3c_pm_init();
179 181
180 return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver); 182 return subsys_interface_register(&s5p64x0_pm_interface);
181} 183}
182arch_initcall(s5p64x0_pm_drvinit); 184arch_initcall(s5p64x0_pm_drvinit);
183 185
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..8410af0d12bf
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
@@ -0,0 +1,104 @@
1/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16
17#include <mach/regs-gpio.h>
18#include <mach/regs-clock.h>
19
20#include <plat/gpio-cfg.h>
21#include <plat/sdhci.h>
22#include <plat/cpu.h>
23
24void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
27
28 /* Set all the necessary GPG pins to special-function 2 */
29 if (soc_is_s5p6450())
30 s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
31 S3C_GPIO_SFN(2));
32 else
33 s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
34 S3C_GPIO_SFN(2));
35
36 /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
37 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
38 if (soc_is_s5p6450()) {
39 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
40 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
41 } else {
42 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
43 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
44 }
45 }
46}
47
48void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
49{
50 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
51
52 /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
53 if (soc_is_s5p6450())
54 s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
55 else
56 s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
57
58 switch (width) {
59 case 8:
60 /* Set data pins GPH[6:9] special-function 2 */
61 if (soc_is_s5p6450())
62 s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
63 S3C_GPIO_SFN(2));
64 else
65 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
66 S3C_GPIO_SFN(2));
67 case 4:
68 /* set data pins GPH[2:5] special-function 2 */
69 if (soc_is_s5p6450())
70 s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
71 S3C_GPIO_SFN(2));
72 else
73 s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
74 S3C_GPIO_SFN(2));
75 default:
76 break;
77 }
78
79 /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
80 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
81 if (soc_is_s5p6450()) {
82 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
83 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
84 } else {
85 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
86 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
87 }
88 }
89}
90
91void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
92{
93 /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
94 s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
95
96 /* Set data pins GPH[6:9] pins to special-function 3 */
97 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
98}
99
100void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
101{
102 /* Set all the necessary GPG pins to special-function 3 */
103 s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
104}
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
new file mode 100644
index 000000000000..e9b841240352
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -0,0 +1,55 @@
1/* linux/arch/arm/mach-s5p64x0/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/cpu.h>
17#include <plat/s3c64xx-spi.h>
18
19#ifdef CONFIG_S3C64XX_DEV_SPI0
20struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
21 .fifo_lvl_mask = 0x1ff,
22 .rx_lvl_offset = 15,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{
28 if (soc_is_s5p6450())
29 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
30 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
31 else
32 s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
33 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
34 return 0;
35}
36#endif
37
38#ifdef CONFIG_S3C64XX_DEV_SPI1
39struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
40 .fifo_lvl_mask = 0x7f,
41 .rx_lvl_offset = 15,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{
47 if (soc_is_s5p6450())
48 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
49 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
50 else
51 s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
52 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
53 return 0;
54}
55#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 12:46:55 -0500