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-rw-r--r--arch/arm/mach-s3c64xx/clock.c20
-rw-r--r--arch/arm/mach-s3c64xx/setup-spi.c13
2 files changed, 10 insertions, 23 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 52f079a691cb..28041e83dc82 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
178 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, 178 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
179 }, { 179 }, {
180 .name = "spi", 180 .name = "spi",
181 .devname = "s3c64xx-spi.0", 181 .devname = "s3c6410-spi.0",
182 .parent = &clk_p, 182 .parent = &clk_p,
183 .enable = s3c64xx_pclk_ctrl, 183 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_SPI0, 184 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
185 }, { 185 }, {
186 .name = "spi", 186 .name = "spi",
187 .devname = "s3c64xx-spi.1", 187 .devname = "s3c6410-spi.1",
188 .parent = &clk_p, 188 .parent = &clk_p,
189 .enable = s3c64xx_pclk_ctrl, 189 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 190 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
331 331
332static struct clk clk_48m_spi0 = { 332static struct clk clk_48m_spi0 = {
333 .name = "spi_48m", 333 .name = "spi_48m",
334 .devname = "s3c64xx-spi.0", 334 .devname = "s3c6410-spi.0",
335 .parent = &clk_48m, 335 .parent = &clk_48m,
336 .enable = s3c64xx_sclk_ctrl, 336 .enable = s3c64xx_sclk_ctrl,
337 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, 337 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
339 339
340static struct clk clk_48m_spi1 = { 340static struct clk clk_48m_spi1 = {
341 .name = "spi_48m", 341 .name = "spi_48m",
342 .devname = "s3c64xx-spi.1", 342 .devname = "s3c6410-spi.1",
343 .parent = &clk_48m, 343 .parent = &clk_48m,
344 .enable = s3c64xx_sclk_ctrl, 344 .enable = s3c64xx_sclk_ctrl,
345 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, 345 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
802static struct clksrc_clk clk_sclk_spi0 = { 802static struct clksrc_clk clk_sclk_spi0 = {
803 .clk = { 803 .clk = {
804 .name = "spi-bus", 804 .name = "spi-bus",
805 .devname = "s3c64xx-spi.0", 805 .devname = "s3c6410-spi.0",
806 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 806 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
807 .enable = s3c64xx_sclk_ctrl, 807 .enable = s3c64xx_sclk_ctrl,
808 }, 808 },
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
814static struct clksrc_clk clk_sclk_spi1 = { 814static struct clksrc_clk clk_sclk_spi1 = {
815 .clk = { 815 .clk = {
816 .name = "spi-bus", 816 .name = "spi-bus",
817 .devname = "s3c64xx-spi.1", 817 .devname = "s3c6410-spi.1",
818 .ctrlbit = S3C_CLKCON_SCLK_SPI1, 818 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
819 .enable = s3c64xx_sclk_ctrl, 819 .enable = s3c64xx_sclk_ctrl,
820 }, 820 },
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
860 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 860 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
861 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 861 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
862 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), 862 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
863 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 863 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
864 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), 864 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
865}; 865};
866 866
867#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 867#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index d9592ad7a825..ff999d95b370 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -12,15 +12,8 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13 13
14#include <plat/gpio-cfg.h> 14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16 15
17#ifdef CONFIG_S3C64XX_DEV_SPI0 16#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .tx_st_done = 21,
22};
23
24int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) 17int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
25{ 18{
26 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, 19 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
@@ -30,12 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
30#endif 23#endif
31 24
32#ifdef CONFIG_S3C64XX_DEV_SPI1 25#ifdef CONFIG_S3C64XX_DEV_SPI1
33struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
34 .fifo_lvl_mask = 0x7f,
35 .rx_lvl_offset = 13,
36 .tx_st_done = 21,
37};
38
39int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) 26int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
40{ 27{
41 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, 28 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,