1 files changed, 4 insertions, 59 deletions

diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index b2ef44317368..afe5a762f46e 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -32,25 +32,13 @@
          * code after resume.
          *
          * entry:
-         *      r0 = pointer to the save block
+         *      r1 = v:p offset
         */
 
 ENTRY(s3c_cpu_save)
         stmfd   sp!, { r4 - r12, lr }
-
-        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
-        mrc     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
-        mrc     p15, 0, r8, c2, c0, 2   @ Translation Table Control
-        mrc     p15, 0, r9, c1, c0, 0   @ Control register
-        mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
-        mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
-
-        stmia   r0, { r4 - r13 }        @ Save CP registers and SP
-
-        @@ save our state to ram
-        bl      s3c_pm_cb_flushcache
+        ldr     r3, =resume_with_mmu
+        bl      cpu_suspend
 
         @@ call final suspend code
         ldr     r0, =pm_cpu_sleep
@@ -61,18 +49,6 @@ ENTRY(s3c_cpu_save)
 resume_with_mmu:
         ldmfd   sp!, { r4 - r12, pc }   @ return, from sp from s3c_cpu_save
 
-        .data
-
-        /* the next bit is code, but it requires easy access to the
-         * s3c_sleep_save_phys data before the MMU is switched on, so
-         * we store the code that needs this variable in the .data where
-         * the value can be written to (the .text segment is RO).
-        */
-
-        .global s3c_sleep_save_phys
-s3c_sleep_save_phys:
-        .word   0
-
         /* Sleep magic, the word before the resume entry point so that the
          * bootloader can check for a resumeable image. */
 
@@ -110,35 +86,4 @@ ENTRY(s3c_cpu_resume)
         orr     r0, r0, #1 << 15                        @ GPN15
         str     r0, [ r3, #S3C64XX_GPNDAT ]
 #endif
-
-        /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
-         * are thoroughly cleaned just in case the bootloader didn't do it
-         * for us. */
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
-        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-        mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
-        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
-        @@mcr   p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
-        @@mcr   p15, 0, r0, c7, c7, 0           @ Invalidate I + D caches
-
-        ldr     r0, s3c_sleep_save_phys
-        ldmia   r0, { r4 - r13 }
-
-        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-        mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mcr     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
-        mcr     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
-        mcr     p15, 0, r8, c2, c0, 2   @ Translation Table Control
-        mcr     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
-
-        mov     r0, #0                  @ restore copro access controls
-        mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
-        mcr     p15, 0, r0, c7, c5, 4
-
-        ldr     r2, =resume_with_mmu
-        mcr     p15, 0, r9, c1, c0, 0           /* turn mmu back on */
-        nop
-        mov     pc, r2                          /* jump back */
-
-        .end
+        b       cpu_resume