43 files changed, 2520 insertions, 0 deletions

diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b18ac5266dfc
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
+/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+
+        /* note, for the boot process to work we have to keep the UART
+         * virtual address aligned to an 1MiB boundary for the L1
+         * mapping the head code makes. We keep the UART virtual address
+         * aligned and add in the offset when we load the value here.
+         */
+
+        .macro addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1
+                ldreq   \rx, = S3C_PA_UART
+                ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+#if CONFIG_DEBUG_S3C_UART != 0
+                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+#endif
+        .endm
+
+/* include the reset of the code which will do the work, we're only
+ * compiling for a single cpu processor type so the default of s3c2440
+ * will be fine with us.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
new file mode 100644
index 000000000000..0a5d9268a23e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -0,0 +1,127 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - DMA support
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H __FILE__
+
+#define S3C_DMA_CHANNELS        (16)
+
+/* see mach-s3c2410/dma.h for notes on dma channel numbers */
+
+/* Note, for the S3C64XX architecture we keep the DMACH_
+ * defines in the order they are allocated to [S]DMA0/[S]DMA1
+ * so that is easy to do DHACH_ -> DMA controller conversion
+ */
+enum dma_ch {
+        /* DMA0/SDMA0 */
+        DMACH_UART0 = 0,
+        DMACH_UART0_SRC2,
+        DMACH_UART1,
+        DMACH_UART1_SRC2,
+        DMACH_UART2,
+        DMACH_UART2_SRC2,
+        DMACH_UART3,
+        DMACH_UART3_SRC2,
+        DMACH_PCM0_TX,
+        DMACH_PCM0_RX,
+        DMACH_I2S0_OUT,
+        DMACH_I2S0_IN,
+        DMACH_SPI0_TX,
+        DMACH_SPI0_RX,
+        DMACH_HSI_I2SV40_TX,
+        DMACH_HSI_I2SV40_RX,
+
+        /* DMA1/SDMA1 */
+        DMACH_PCM1_TX = 16,
+        DMACH_PCM1_RX,
+        DMACH_I2S1_OUT,
+        DMACH_I2S1_IN,
+        DMACH_SPI1_TX,
+        DMACH_SPI1_RX,
+        DMACH_AC97_PCMOUT,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_MICIN,
+        DMACH_PWM,
+        DMACH_IRDA,
+        DMACH_EXTERNAL,
+        DMACH_RES1,
+        DMACH_RES2,
+        DMACH_SECURITY_RX,      /* SDMA1 only */
+        DMACH_SECURITY_TX,      /* SDMA1 only */
+        DMACH_MAX               /* the end */
+};
+
+static __inline__ bool s3c_dma_has_circular(void)
+{
+        return true;
+}
+
+#define S3C2410_DMAF_CIRCULAR           (1 << 0)
+
+#include <plat/dma.h>
+
+#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
+
+struct s3c64xx_dma_buff;
+
+/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
+ * @next: Pointer to next buffer in queue or ring.
+ * @pw: Client provided identifier
+ * @lli: Pointer to hardware descriptor this buffer is associated with.
+ * @lli_dma: Hardare address of the descriptor.
+ */
+struct s3c64xx_dma_buff {
+        struct s3c64xx_dma_buff *next;
+
+        void                    *pw;
+        struct pl080s_lli       *lli;
+        dma_addr_t               lli_dma;
+};
+
+struct s3c64xx_dmac;
+
+struct s3c2410_dma_chan {
+        unsigned char            number;      /* number of this dma channel */
+        unsigned char            in_use;      /* channel allocated */
+        unsigned char            bit;         /* bit for enable/disable/etc */
+        unsigned char            hw_width;
+        unsigned char            peripheral;
+
+        unsigned int             flags;
+        enum s3c2410_dmasrc      source;
+
+
+        dma_addr_t              dev_addr;
+
+        struct s3c2410_dma_client *client;
+        struct s3c64xx_dmac     *dmac;          /* pointer to controller */
+
+        void __iomem            *regs;
+
+        /* cdriver callbacks */
+        s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
+        s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
+
+        /* buffer list and information */
+        struct s3c64xx_dma_buff *curr;          /* current dma buffer */
+        struct s3c64xx_dma_buff *next;          /* next buffer to load */
+        struct s3c64xx_dma_buff *end;           /* end of queue */
+
+        /* note, when channel is running in circular mode, curr is the
+         * first buffer enqueued, end is the last and curr is where the
+         * last buffer-done event is set-at. The buffers are not freed
+         * and the last buffer hardware descriptor points back to the
+         * first.
+         */
+};
+
+#include <plat/dma-core.h>
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..dd362604dcce
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Low-level IRQ helper macros for the Samsung S3C64XX series
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
new file mode 100644
index 000000000000..34212e1a7e81
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
@@ -0,0 +1,48 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank A register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPACON                  (S3C64XX_GPA_BASE + 0x00)
+#define S3C64XX_GPADAT                  (S3C64XX_GPA_BASE + 0x04)
+#define S3C64XX_GPAPUD                  (S3C64XX_GPA_BASE + 0x08)
+#define S3C64XX_GPACONSLP               (S3C64XX_GPA_BASE + 0x0c)
+#define S3C64XX_GPAPUDSLP               (S3C64XX_GPA_BASE + 0x10)
+
+#define S3C64XX_GPA_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S3C64XX_GPA_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPA_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPA0_UART_RXD0          (0x02 << 0)
+#define S3C64XX_GPA0_EINT_G1_0          (0x07 << 0)
+
+#define S3C64XX_GPA1_UART_TXD0          (0x02 << 4)
+#define S3C64XX_GPA1_EINT_G1_1          (0x07 << 4)
+
+#define S3C64XX_GPA2_UART_nCTS0         (0x02 << 8)
+#define S3C64XX_GPA2_EINT_G1_2          (0x07 << 8)
+
+#define S3C64XX_GPA3_UART_nRTS0         (0x02 << 12)
+#define S3C64XX_GPA3_EINT_G1_3          (0x07 << 12)
+
+#define S3C64XX_GPA4_UART_RXD1          (0x02 << 16)
+#define S3C64XX_GPA4_EINT_G1_4          (0x07 << 16)
+
+#define S3C64XX_GPA5_UART_TXD1          (0x02 << 20)
+#define S3C64XX_GPA5_EINT_G1_5          (0x07 << 20)
+
+#define S3C64XX_GPA6_UART_nCTS1         (0x02 << 24)
+#define S3C64XX_GPA6_EINT_G1_6          (0x07 << 24)
+
+#define S3C64XX_GPA7_UART_nRTS1         (0x02 << 28)
+#define S3C64XX_GPA7_EINT_G1_7          (0x07 << 28)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
new file mode 100644
index 000000000000..7232c037e642
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
@@ -0,0 +1,60 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank B register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPBCON                  (S3C64XX_GPB_BASE + 0x00)
+#define S3C64XX_GPBDAT                  (S3C64XX_GPB_BASE + 0x04)
+#define S3C64XX_GPBPUD                  (S3C64XX_GPB_BASE + 0x08)
+#define S3C64XX_GPBCONSLP               (S3C64XX_GPB_BASE + 0x0c)
+#define S3C64XX_GPBPUDSLP               (S3C64XX_GPB_BASE + 0x10)
+
+#define S3C64XX_GPB_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S3C64XX_GPB_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPB_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPB0_UART_RXD2          (0x02 << 0)
+#define S3C64XX_GPB0_EXTDMA_REQ         (0x03 << 0)
+#define S3C64XX_GPB0_IrDA_RXD           (0x04 << 0)
+#define S3C64XX_GPB0_ADDR_CF0           (0x05 << 0)
+#define S3C64XX_GPB0_EINT_G1_8          (0x07 << 0)
+
+#define S3C64XX_GPB1_UART_TXD2          (0x02 << 4)
+#define S3C64XX_GPB1_EXTDMA_ACK         (0x03 << 4)
+#define S3C64XX_GPB1_IrDA_TXD           (0x04 << 4)
+#define S3C64XX_GPB1_ADDR_CF1           (0x05 << 4)
+#define S3C64XX_GPB1_EINT_G1_9          (0x07 << 4)
+
+#define S3C64XX_GPB2_UART_RXD3          (0x02 << 8)
+#define S3C64XX_GPB2_IrDA_RXD           (0x03 << 8)
+#define S3C64XX_GPB2_EXTDMA_REQ         (0x04 << 8)
+#define S3C64XX_GPB2_ADDR_CF2           (0x05 << 8)
+#define S3C64XX_GPB2_I2C_SCL1           (0x06 << 8)
+#define S3C64XX_GPB2_EINT_G1_10         (0x07 << 8)
+
+#define S3C64XX_GPB3_UART_TXD3          (0x02 << 12)
+#define S3C64XX_GPB3_IrDA_TXD           (0x03 << 12)
+#define S3C64XX_GPB3_EXTDMA_ACK         (0x04 << 12)
+#define S3C64XX_GPB3_I2C_SDA1           (0x06 << 12)
+#define S3C64XX_GPB3_EINT_G1_11         (0x07 << 12)
+
+#define S3C64XX_GPB4_IrDA_SDBW          (0x02 << 16)
+#define S3C64XX_GPB4_CAM_FIELD          (0x03 << 16)
+#define S3C64XX_GPB4_CF_DATA_DIR        (0x04 << 16)
+#define S3C64XX_GPB4_EINT_G1_12         (0x07 << 16)
+
+#define S3C64XX_GPB5_I2C_SCL0           (0x02 << 20)
+#define S3C64XX_GPB5_EINT_G1_13         (0x07 << 20)
+
+#define S3C64XX_GPB6_I2C_SDA0           (0x02 << 24)
+#define S3C64XX_GPB6_EINT_G1_14         (0x07 << 24)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
new file mode 100644
index 000000000000..db189ab1639a
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank C register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPCCON                  (S3C64XX_GPC_BASE + 0x00)
+#define S3C64XX_GPCDAT                  (S3C64XX_GPC_BASE + 0x04)
+#define S3C64XX_GPCPUD                  (S3C64XX_GPC_BASE + 0x08)
+#define S3C64XX_GPCCONSLP               (S3C64XX_GPC_BASE + 0x0c)
+#define S3C64XX_GPCPUDSLP               (S3C64XX_GPC_BASE + 0x10)
+
+#define S3C64XX_GPC_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S3C64XX_GPC_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPC_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPC0_SPI_MISO0          (0x02 << 0)
+#define S3C64XX_GPC0_EINT_G2_0          (0x07 << 0)
+
+#define S3C64XX_GPC1_SPI_CLKO           (0x02 << 4)
+#define S3C64XX_GPC1_EINT_G2_1          (0x07 << 4)
+
+#define S3C64XX_GPC2_SPI_MOSIO          (0x02 << 8)
+#define S3C64XX_GPC2_EINT_G2_2          (0x07 << 8)
+
+#define S3C64XX_GPC3_SPI_nCSO           (0x02 << 12)
+#define S3C64XX_GPC3_EINT_G2_3          (0x07 << 12)
+
+#define S3C64XX_GPC4_SPI_MISO1          (0x02 << 16)
+#define S3C64XX_GPC4_MMC2_CMD           (0x03 << 16)
+#define S3C64XX_GPC4_I2S_V40_DO0        (0x05 << 16)
+#define S3C64XX_GPC4_EINT_G2_4          (0x07 << 16)
+
+#define S3C64XX_GPC5_SPI_CLK1           (0x02 << 20)
+#define S3C64XX_GPC5_MMC2_CLK           (0x03 << 20)
+#define S3C64XX_GPC5_I2S_V40_DO1        (0x05 << 20)
+#define S3C64XX_GPC5_EINT_G2_5          (0x07 << 20)
+
+#define S3C64XX_GPC6_SPI_MOSI1          (0x02 << 24)
+#define S3C64XX_GPC6_EINT_G2_6          (0x07 << 24)
+
+#define S3C64XX_GPC7_SPI_nCS1           (0x02 << 28)
+#define S3C64XX_GPC7_I2S_V40_DO2        (0x05 << 28)
+#define S3C64XX_GPC7_EINT_G2_7          (0x07 << 28)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
new file mode 100644
index 000000000000..1a01cee7aca3
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
@@ -0,0 +1,49 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank D register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPDCON                  (S3C64XX_GPD_BASE + 0x00)
+#define S3C64XX_GPDDAT                  (S3C64XX_GPD_BASE + 0x04)
+#define S3C64XX_GPDPUD                  (S3C64XX_GPD_BASE + 0x08)
+#define S3C64XX_GPDCONSLP               (S3C64XX_GPD_BASE + 0x0c)
+#define S3C64XX_GPDPUDSLP               (S3C64XX_GPD_BASE + 0x10)
+
+#define S3C64XX_GPD_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S3C64XX_GPD_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPD_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPD0_PCM0_SCLK          (0x02 << 0)
+#define S3C64XX_GPD0_I2S0_CLK           (0x03 << 0)
+#define S3C64XX_GPD0_AC97_BITCLK        (0x04 << 0)
+#define S3C64XX_GPD0_EINT_G3_0          (0x07 << 0)
+
+#define S3C64XX_GPD1_PCM0_EXTCLK        (0x02 << 4)
+#define S3C64XX_GPD1_I2S0_CDCLK         (0x03 << 4)
+#define S3C64XX_GPD1_AC97_nRESET        (0x04 << 4)
+#define S3C64XX_GPD1_EINT_G3_1          (0x07 << 4)
+
+#define S3C64XX_GPD2_PCM0_FSYNC         (0x02 << 8)
+#define S3C64XX_GPD2_I2S0_LRCLK         (0x03 << 8)
+#define S3C64XX_GPD2_AC97_SYNC          (0x04 << 8)
+#define S3C64XX_GPD2_EINT_G3_2          (0x07 << 8)
+
+#define S3C64XX_GPD3_PCM0_SIN           (0x02 << 12)
+#define S3C64XX_GPD3_I2S0_DI            (0x03 << 12)
+#define S3C64XX_GPD3_AC97_SDI           (0x04 << 12)
+#define S3C64XX_GPD3_EINT_G3_3          (0x07 << 12)
+
+#define S3C64XX_GPD4_PCM0_SOUT          (0x02 << 16)
+#define S3C64XX_GPD4_I2S0_D0            (0x03 << 16)
+#define S3C64XX_GPD4_AC97_SDO           (0x04 << 16)
+#define S3C64XX_GPD4_EINT_G3_4          (0x07 << 16)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
new file mode 100644
index 000000000000..f057adb627dd
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
@@ -0,0 +1,44 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank E register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPECON                  (S3C64XX_GPE_BASE + 0x00)
+#define S3C64XX_GPEDAT                  (S3C64XX_GPE_BASE + 0x04)
+#define S3C64XX_GPEPUD                  (S3C64XX_GPE_BASE + 0x08)
+#define S3C64XX_GPECONSLP               (S3C64XX_GPE_BASE + 0x0c)
+#define S3C64XX_GPEPUDSLP               (S3C64XX_GPE_BASE + 0x10)
+
+#define S3C64XX_GPE_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S3C64XX_GPE_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPE_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPE0_PCM1_SCLK          (0x02 << 0)
+#define S3C64XX_GPE0_I2S1_CLK           (0x03 << 0)
+#define S3C64XX_GPE0_AC97_BITCLK        (0x04 << 0)
+
+#define S3C64XX_GPE1_PCM1_EXTCLK        (0x02 << 4)
+#define S3C64XX_GPE1_I2S1_CDCLK         (0x03 << 4)
+#define S3C64XX_GPE1_AC97_nRESET        (0x04 << 4)
+
+#define S3C64XX_GPE2_PCM1_FSYNC         (0x02 << 8)
+#define S3C64XX_GPE2_I2S1_LRCLK         (0x03 << 8)
+#define S3C64XX_GPE2_AC97_SYNC          (0x04 << 8)
+
+#define S3C64XX_GPE3_PCM1_SIN           (0x02 << 12)
+#define S3C64XX_GPE3_I2S1_DI            (0x03 << 12)
+#define S3C64XX_GPE3_AC97_SDI           (0x04 << 12)
+
+#define S3C64XX_GPE4_PCM1_SOUT          (0x02 << 16)
+#define S3C64XX_GPE4_I2S1_D0            (0x03 << 16)
+#define S3C64XX_GPE4_AC97_SDO           (0x04 << 16)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
new file mode 100644
index 000000000000..62ab8f5e7835
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
@@ -0,0 +1,71 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank F register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPFCON                  (S3C64XX_GPF_BASE + 0x00)
+#define S3C64XX_GPFDAT                  (S3C64XX_GPF_BASE + 0x04)
+#define S3C64XX_GPFPUD                  (S3C64XX_GPF_BASE + 0x08)
+#define S3C64XX_GPFCONSLP               (S3C64XX_GPF_BASE + 0x0c)
+#define S3C64XX_GPFPUDSLP               (S3C64XX_GPF_BASE + 0x10)
+
+#define S3C64XX_GPF_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPF_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPF_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPF0_CAMIF_CLK          (0x02 << 0)
+#define S3C64XX_GPF0_EINT_G4_0          (0x03 << 0)
+
+#define S3C64XX_GPF1_CAMIF_HREF         (0x02 << 2)
+#define S3C64XX_GPF1_EINT_G4_1          (0x03 << 2)
+
+#define S3C64XX_GPF2_CAMIF_PCLK         (0x02 << 4)
+#define S3C64XX_GPF2_EINT_G4_2          (0x03 << 4)
+
+#define S3C64XX_GPF3_CAMIF_nRST         (0x02 << 6)
+#define S3C64XX_GPF3_EINT_G4_3          (0x03 << 6)
+
+#define S3C64XX_GPF4_CAMIF_VSYNC        (0x02 << 8)
+#define S3C64XX_GPF4_EINT_G4_4          (0x03 << 8)
+
+#define S3C64XX_GPF5_CAMIF_YDATA0       (0x02 << 10)
+#define S3C64XX_GPF5_EINT_G4_5          (0x03 << 10)
+
+#define S3C64XX_GPF6_CAMIF_YDATA1       (0x02 << 12)
+#define S3C64XX_GPF6_EINT_G4_6          (0x03 << 12)
+
+#define S3C64XX_GPF7_CAMIF_YDATA2       (0x02 << 14)
+#define S3C64XX_GPF7_EINT_G4_7          (0x03 << 14)
+
+#define S3C64XX_GPF8_CAMIF_YDATA3       (0x02 << 16)
+#define S3C64XX_GPF8_EINT_G4_8          (0x03 << 16)
+
+#define S3C64XX_GPF9_CAMIF_YDATA4       (0x02 << 18)
+#define S3C64XX_GPF9_EINT_G4_9          (0x03 << 18)
+
+#define S3C64XX_GPF10_CAMIF_YDATA5      (0x02 << 20)
+#define S3C64XX_GPF10_EINT_G4_10        (0x03 << 20)
+
+#define S3C64XX_GPF11_CAMIF_YDATA6      (0x02 << 22)
+#define S3C64XX_GPF11_EINT_G4_11        (0x03 << 22)
+
+#define S3C64XX_GPF12_CAMIF_YDATA7      (0x02 << 24)
+#define S3C64XX_GPF12_EINT_G4_12        (0x03 << 24)
+
+#define S3C64XX_GPF13_PWM_ECLK          (0x02 << 26)
+#define S3C64XX_GPF13_EINT_G4_13        (0x03 << 26)
+
+#define S3C64XX_GPF14_PWM_TOUT0         (0x02 << 28)
+#define S3C64XX_GPF14_CLKOUT0           (0x03 << 28)
+
+#define S3C64XX_GPF15_PWM_TOUT1         (0x02 << 30)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
new file mode 100644
index 000000000000..b94954af1598
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank G register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPGCON                  (S3C64XX_GPG_BASE + 0x00)
+#define S3C64XX_GPGDAT                  (S3C64XX_GPG_BASE + 0x04)
+#define S3C64XX_GPGPUD                  (S3C64XX_GPG_BASE + 0x08)
+#define S3C64XX_GPGCONSLP               (S3C64XX_GPG_BASE + 0x0c)
+#define S3C64XX_GPGPUDSLP               (S3C64XX_GPG_BASE + 0x10)
+
+#define S3C64XX_GPG_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S3C64XX_GPG_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPG_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPG0_MMC0_CLK           (0x02 << 0)
+#define S3C64XX_GPG0_EINT_G5_0          (0x07 << 0)
+
+#define S3C64XX_GPG1_MMC0_CMD           (0x02 << 4)
+#define S3C64XX_GPG1_EINT_G5_1          (0x07 << 4)
+
+#define S3C64XX_GPG2_MMC0_DATA0         (0x02 << 8)
+#define S3C64XX_GPG2_EINT_G5_2          (0x07 << 8)
+
+#define S3C64XX_GPG3_MMC0_DATA1         (0x02 << 12)
+#define S3C64XX_GPG3_EINT_G5_3          (0x07 << 12)
+
+#define S3C64XX_GPG4_MMC0_DATA2         (0x02 << 16)
+#define S3C64XX_GPG4_EINT_G5_4          (0x07 << 16)
+
+#define S3C64XX_GPG5_MMC0_DATA3         (0x02 << 20)
+#define S3C64XX_GPG5_EINT_G5_5          (0x07 << 20)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
new file mode 100644
index 000000000000..5d75aaad865e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
@@ -0,0 +1,74 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank H register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPHCON0                 (S3C64XX_GPH_BASE + 0x00)
+#define S3C64XX_GPHCON1                 (S3C64XX_GPH_BASE + 0x04)
+#define S3C64XX_GPHDAT                  (S3C64XX_GPH_BASE + 0x08)
+#define S3C64XX_GPHPUD                  (S3C64XX_GPH_BASE + 0x0c)
+#define S3C64XX_GPHCONSLP               (S3C64XX_GPH_BASE + 0x10)
+#define S3C64XX_GPHPUDSLP               (S3C64XX_GPH_BASE + 0x14)
+
+#define S3C64XX_GPH_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S3C64XX_GPH_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPH_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPH0_MMC1_CLK           (0x02 << 0)
+#define S3C64XX_GPH0_KP_COL0            (0x04 << 0)
+#define S3C64XX_GPH0_EINT_G6_0          (0x07 << 0)
+
+#define S3C64XX_GPH1_MMC1_CMD           (0x02 << 4)
+#define S3C64XX_GPH1_KP_COL1            (0x04 << 4)
+#define S3C64XX_GPH1_EINT_G6_1          (0x07 << 4)
+
+#define S3C64XX_GPH2_MMC1_DATA0         (0x02 << 8)
+#define S3C64XX_GPH2_KP_COL2            (0x04 << 8)
+#define S3C64XX_GPH2_EINT_G6_2          (0x07 << 8)
+
+#define S3C64XX_GPH3_MMC1_DATA1         (0x02 << 12)
+#define S3C64XX_GPH3_KP_COL3            (0x04 << 12)
+#define S3C64XX_GPH3_EINT_G6_3          (0x07 << 12)
+
+#define S3C64XX_GPH4_MMC1_DATA2         (0x02 << 16)
+#define S3C64XX_GPH4_KP_COL4            (0x04 << 16)
+#define S3C64XX_GPH4_EINT_G6_4          (0x07 << 16)
+
+#define S3C64XX_GPH5_MMC1_DATA3         (0x02 << 20)
+#define S3C64XX_GPH5_KP_COL5            (0x04 << 20)
+#define S3C64XX_GPH5_EINT_G6_5          (0x07 << 20)
+
+#define S3C64XX_GPH6_MMC1_DATA4         (0x02 << 24)
+#define S3C64XX_GPH6_MMC2_DATA0         (0x03 << 24)
+#define S3C64XX_GPH6_KP_COL6            (0x04 << 24)
+#define S3C64XX_GPH6_I2S_V40_BCLK       (0x05 << 24)
+#define S3C64XX_GPH6_ADDR_CF0           (0x06 << 24)
+#define S3C64XX_GPH6_EINT_G6_6          (0x07 << 24)
+
+#define S3C64XX_GPH7_MMC1_DATA5         (0x02 << 28)
+#define S3C64XX_GPH7_MMC2_DATA1         (0x03 << 28)
+#define S3C64XX_GPH7_KP_COL7            (0x04 << 28)
+#define S3C64XX_GPH7_I2S_V40_CDCLK      (0x05 << 28)
+#define S3C64XX_GPH7_ADDR_CF1           (0x06 << 28)
+#define S3C64XX_GPH7_EINT_G6_7          (0x07 << 28)
+
+#define S3C64XX_GPH8_MMC1_DATA6         (0x02 <<  0)
+#define S3C64XX_GPH8_MMC2_DATA2         (0x03 <<  0)
+#define S3C64XX_GPH8_I2S_V40_LRCLK      (0x05 <<  0)
+#define S3C64XX_GPH8_ADDR_CF2           (0x06 <<  0)
+#define S3C64XX_GPH8_EINT_G6_8          (0x07 <<  0)
+
+#define S3C64XX_GPH9_OUTPUT             (0x01 <<  4)
+#define S3C64XX_GPH9_MMC1_DATA7         (0x02 <<  4)
+#define S3C64XX_GPH9_MMC2_DATA3         (0x03 <<  4)
+#define S3C64XX_GPH9_I2S_V40_DI         (0x05 <<  4)
+#define S3C64XX_GPH9_EINT_G6_9          (0x07 <<  4)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
new file mode 100644
index 000000000000..4ceaa6098bc7
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
@@ -0,0 +1,40 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank I register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPICON                  (S3C64XX_GPI_BASE + 0x00)
+#define S3C64XX_GPIDAT                  (S3C64XX_GPI_BASE + 0x04)
+#define S3C64XX_GPIPUD                  (S3C64XX_GPI_BASE + 0x08)
+#define S3C64XX_GPICONSLP               (S3C64XX_GPI_BASE + 0x0c)
+#define S3C64XX_GPIPUDSLP               (S3C64XX_GPI_BASE + 0x10)
+
+#define S3C64XX_GPI_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPI_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPI_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPI0_VD0                (0x02 << 0)
+#define S3C64XX_GPI1_VD1                (0x02 << 2)
+#define S3C64XX_GPI2_VD2                (0x02 << 4)
+#define S3C64XX_GPI3_VD3                (0x02 << 6)
+#define S3C64XX_GPI4_VD4                (0x02 << 8)
+#define S3C64XX_GPI5_VD5                (0x02 << 10)
+#define S3C64XX_GPI6_VD6                (0x02 << 12)
+#define S3C64XX_GPI7_VD7                (0x02 << 14)
+#define S3C64XX_GPI8_VD8                (0x02 << 16)
+#define S3C64XX_GPI9_VD9                (0x02 << 18)
+#define S3C64XX_GPI10_VD10              (0x02 << 20)
+#define S3C64XX_GPI11_VD11              (0x02 << 22)
+#define S3C64XX_GPI12_VD12              (0x02 << 24)
+#define S3C64XX_GPI13_VD13              (0x02 << 26)
+#define S3C64XX_GPI14_VD14              (0x02 << 28)
+#define S3C64XX_GPI15_VD15              (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
new file mode 100644
index 000000000000..6f25cd079a40
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
@@ -0,0 +1,36 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank J register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPJCON                  (S3C64XX_GPJ_BASE + 0x00)
+#define S3C64XX_GPJDAT                  (S3C64XX_GPJ_BASE + 0x04)
+#define S3C64XX_GPJPUD                  (S3C64XX_GPJ_BASE + 0x08)
+#define S3C64XX_GPJCONSLP               (S3C64XX_GPJ_BASE + 0x0c)
+#define S3C64XX_GPJPUDSLP               (S3C64XX_GPJ_BASE + 0x10)
+
+#define S3C64XX_GPJ_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPJ_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPJ_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPJ0_VD16               (0x02 << 0)
+#define S3C64XX_GPJ1_VD17               (0x02 << 2)
+#define S3C64XX_GPJ2_VD18               (0x02 << 4)
+#define S3C64XX_GPJ3_VD19               (0x02 << 6)
+#define S3C64XX_GPJ4_VD20               (0x02 << 8)
+#define S3C64XX_GPJ5_VD21               (0x02 << 10)
+#define S3C64XX_GPJ6_VD22               (0x02 << 12)
+#define S3C64XX_GPJ7_VD23               (0x02 << 14)
+#define S3C64XX_GPJ8_LCD_HSYNC          (0x02 << 16)
+#define S3C64XX_GPJ9_LCD_VSYNC          (0x02 << 18)
+#define S3C64XX_GPJ10_LCD_VDEN          (0x02 << 20)
+#define S3C64XX_GPJ11_LCD_VCLK          (0x02 << 22)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
new file mode 100644
index 000000000000..d0aeda1cd9de
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
@@ -0,0 +1,54 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank N register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPNCON                  (S3C64XX_GPN_BASE + 0x00)
+#define S3C64XX_GPNDAT                  (S3C64XX_GPN_BASE + 0x04)
+#define S3C64XX_GPNPUD                  (S3C64XX_GPN_BASE + 0x08)
+
+#define S3C64XX_GPN_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPN_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPN_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPN0_EINT0              (0x02 << 0)
+#define S3C64XX_GPN0_KP_ROW0            (0x03 << 0)
+
+#define S3C64XX_GPN1_EINT1              (0x02 << 2)
+#define S3C64XX_GPN1_KP_ROW1            (0x03 << 2)
+
+#define S3C64XX_GPN2_EINT2              (0x02 << 4)
+#define S3C64XX_GPN2_KP_ROW2            (0x03 << 4)
+
+#define S3C64XX_GPN3_EINT3              (0x02 << 6)
+#define S3C64XX_GPN3_KP_ROW3            (0x03 << 6)
+
+#define S3C64XX_GPN4_EINT4              (0x02 << 8)
+#define S3C64XX_GPN4_KP_ROW4            (0x03 << 8)
+
+#define S3C64XX_GPN5_EINT5              (0x02 << 10)
+#define S3C64XX_GPN5_KP_ROW5            (0x03 << 10)
+
+#define S3C64XX_GPN6_EINT6              (0x02 << 12)
+#define S3C64XX_GPN6_KP_ROW6            (0x03 << 12)
+
+#define S3C64XX_GPN7_EINT7              (0x02 << 14)
+#define S3C64XX_GPN7_KP_ROW7            (0x03 << 14)
+
+#define S3C64XX_GPN8_EINT8              (0x02 << 16)
+#define S3C64XX_GPN9_EINT9              (0x02 << 18)
+#define S3C64XX_GPN10_EINT10            (0x02 << 20)
+#define S3C64XX_GPN11_EINT11            (0x02 << 22)
+#define S3C64XX_GPN12_EINT12            (0x02 << 24)
+#define S3C64XX_GPN13_EINT13            (0x02 << 26)
+#define S3C64XX_GPN14_EINT14            (0x02 << 28)
+#define S3C64XX_GPN15_EINT15            (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
new file mode 100644
index 000000000000..21868fa102d0
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank O register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPOCON                  (S3C64XX_GPO_BASE + 0x00)
+#define S3C64XX_GPODAT                  (S3C64XX_GPO_BASE + 0x04)
+#define S3C64XX_GPOPUD                  (S3C64XX_GPO_BASE + 0x08)
+#define S3C64XX_GPOCONSLP               (S3C64XX_GPO_BASE + 0x0c)
+#define S3C64XX_GPOPUDSLP               (S3C64XX_GPO_BASE + 0x10)
+
+#define S3C64XX_GPO_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPO_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPO_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPO0_MEM0_nCS2          (0x02 << 0)
+#define S3C64XX_GPO0_EINT_G7_0          (0x03 << 0)
+
+#define S3C64XX_GPO1_MEM0_nCS3          (0x02 << 2)
+#define S3C64XX_GPO1_EINT_G7_1          (0x03 << 2)
+
+#define S3C64XX_GPO2_MEM0_nCS4          (0x02 << 4)
+#define S3C64XX_GPO2_EINT_G7_2          (0x03 << 4)
+
+#define S3C64XX_GPO3_MEM0_nCS5          (0x02 << 6)
+#define S3C64XX_GPO3_EINT_G7_3          (0x03 << 6)
+
+#define S3C64XX_GPO4_EINT_G7_4          (0x03 << 8)
+
+#define S3C64XX_GPO5_EINT_G7_5          (0x03 << 10)
+
+#define S3C64XX_GPO6_MEM0_ADDR6         (0x02 << 12)
+#define S3C64XX_GPO6_EINT_G7_6          (0x03 << 12)
+
+#define S3C64XX_GPO7_MEM0_ADDR7         (0x02 << 14)
+#define S3C64XX_GPO7_EINT_G7_7          (0x03 << 14)
+
+#define S3C64XX_GPO8_MEM0_ADDR8         (0x02 << 16)
+#define S3C64XX_GPO8_EINT_G7_8          (0x03 << 16)
+
+#define S3C64XX_GPO9_MEM0_ADDR9         (0x02 << 18)
+#define S3C64XX_GPO9_EINT_G7_9          (0x03 << 18)
+
+#define S3C64XX_GPO10_MEM0_ADDR10       (0x02 << 20)
+#define S3C64XX_GPO10_EINT_G7_10        (0x03 << 20)
+
+#define S3C64XX_GPO11_MEM0_ADDR11       (0x02 << 22)
+#define S3C64XX_GPO11_EINT_G7_11        (0x03 << 22)
+
+#define S3C64XX_GPO12_MEM0_ADDR12       (0x02 << 24)
+#define S3C64XX_GPO12_EINT_G7_12        (0x03 << 24)
+
+#define S3C64XX_GPO13_MEM0_ADDR13       (0x02 << 26)
+#define S3C64XX_GPO13_EINT_G7_13        (0x03 << 26)
+
+#define S3C64XX_GPO14_MEM0_ADDR14       (0x02 << 28)
+#define S3C64XX_GPO14_EINT_G7_14        (0x03 << 28)
+
+#define S3C64XX_GPO15_MEM0_ADDR15       (0x02 << 30)
+#define S3C64XX_GPO15_EINT_G7_15        (0x03 << 30)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
new file mode 100644
index 000000000000..46bcfb63b8de
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
@@ -0,0 +1,69 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank P register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPPCON                  (S3C64XX_GPP_BASE + 0x00)
+#define S3C64XX_GPPDAT                  (S3C64XX_GPP_BASE + 0x04)
+#define S3C64XX_GPPPUD                  (S3C64XX_GPP_BASE + 0x08)
+#define S3C64XX_GPPCONSLP               (S3C64XX_GPP_BASE + 0x0c)
+#define S3C64XX_GPPPUDSLP               (S3C64XX_GPP_BASE + 0x10)
+
+#define S3C64XX_GPP_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPP_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPP_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPP0_MEM0_ADDRV         (0x02 << 0)
+#define S3C64XX_GPP0_EINT_G8_0          (0x03 << 0)
+
+#define S3C64XX_GPP1_MEM0_SMCLK         (0x02 << 2)
+#define S3C64XX_GPP1_EINT_G8_1          (0x03 << 2)
+
+#define S3C64XX_GPP2_MEM0_nWAIT         (0x02 << 4)
+#define S3C64XX_GPP2_EINT_G8_2          (0x03 << 4)
+
+#define S3C64XX_GPP3_MEM0_RDY0_ALE      (0x02 << 6)
+#define S3C64XX_GPP3_EINT_G8_3          (0x03 << 6)
+
+#define S3C64XX_GPP4_MEM0_RDY1_CLE      (0x02 << 8)
+#define S3C64XX_GPP4_EINT_G8_4          (0x03 << 8)
+
+#define S3C64XX_GPP5_MEM0_INTsm0_FWE    (0x02 << 10)
+#define S3C64XX_GPP5_EINT_G8_5          (0x03 << 10)
+
+#define S3C64XX_GPP6_MEM0_(null)        (0x02 << 12)
+#define S3C64XX_GPP6_EINT_G8_6          (0x03 << 12)
+
+#define S3C64XX_GPP7_MEM0_INTsm1_FRE    (0x02 << 14)
+#define S3C64XX_GPP7_EINT_G8_7          (0x03 << 14)
+
+#define S3C64XX_GPP8_MEM0_RPn_RnB       (0x02 << 16)
+#define S3C64XX_GPP8_EINT_G8_8          (0x03 << 16)
+
+#define S3C64XX_GPP9_MEM0_ATA_RESET     (0x02 << 18)
+#define S3C64XX_GPP9_EINT_G8_9          (0x03 << 18)
+
+#define S3C64XX_GPP10_MEM0_ATA_INPACK   (0x02 << 20)
+#define S3C64XX_GPP10_EINT_G8_10        (0x03 << 20)
+
+#define S3C64XX_GPP11_MEM0_ATA_REG      (0x02 << 22)
+#define S3C64XX_GPP11_EINT_G8_11        (0x03 << 22)
+
+#define S3C64XX_GPP12_MEM0_ATA_WE       (0x02 << 24)
+#define S3C64XX_GPP12_EINT_G8_12        (0x03 << 24)
+
+#define S3C64XX_GPP13_MEM0_ATA_OE       (0x02 << 26)
+#define S3C64XX_GPP13_EINT_G8_13        (0x03 << 26)
+
+#define S3C64XX_GPP14_MEM0_ATA_CD       (0x02 << 28)
+#define S3C64XX_GPP14_EINT_G8_14        (0x03 << 28)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
new file mode 100644
index 000000000000..1712223487b0
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank Q register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPQCON                  (S3C64XX_GPQ_BASE + 0x00)
+#define S3C64XX_GPQDAT                  (S3C64XX_GPQ_BASE + 0x04)
+#define S3C64XX_GPQPUD                  (S3C64XX_GPQ_BASE + 0x08)
+#define S3C64XX_GPQCONSLP               (S3C64XX_GPQ_BASE + 0x0c)
+#define S3C64XX_GPQPUDSLP               (S3C64XX_GPQ_BASE + 0x10)
+
+#define S3C64XX_GPQ_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPQ_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPQ_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPQ0_MEM0_ADDR18_RAS    (0x02 << 0)
+#define S3C64XX_GPQ0_EINT_G9_0          (0x03 << 0)
+
+#define S3C64XX_GPQ1_MEM0_ADDR19_CAS    (0x02 << 2)
+#define S3C64XX_GPQ1_EINT_G9_1          (0x03 << 2)
+
+#define S3C64XX_GPQ2_EINT_G9_2          (0x03 << 4)
+
+#define S3C64XX_GPQ3_EINT_G9_3          (0x03 << 6)
+
+#define S3C64XX_GPQ4_EINT_G9_4          (0x03 << 8)
+
+#define S3C64XX_GPQ5_EINT_G9_5          (0x03 << 10)
+
+#define S3C64XX_GPQ6_EINT_G9_6          (0x03 << 12)
+
+#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
+#define S3C64XX_GPQ7_EINT_G9_7          (0x03 << 14)
+
+#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC  (0x02 << 16)
+#define S3C64XX_GPQ8_EINT_G9_8          (0x03 << 16)
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h
new file mode 100644
index 000000000000..0d46e994048a
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h
@@ -0,0 +1,100 @@
+/* arch/arm/mach-s3c6400/include/mach/gpio.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C6400 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+/* GPIO bank sizes */
+#define S3C64XX_GPIO_A_NR       (8)
+#define S3C64XX_GPIO_B_NR       (7)
+#define S3C64XX_GPIO_C_NR       (8)
+#define S3C64XX_GPIO_D_NR       (5)
+#define S3C64XX_GPIO_E_NR       (5)
+#define S3C64XX_GPIO_F_NR       (16)
+#define S3C64XX_GPIO_G_NR       (7)
+#define S3C64XX_GPIO_H_NR       (10)
+#define S3C64XX_GPIO_I_NR       (16)
+#define S3C64XX_GPIO_J_NR       (12)
+#define S3C64XX_GPIO_K_NR       (16)
+#define S3C64XX_GPIO_L_NR       (15)
+#define S3C64XX_GPIO_M_NR       (6)
+#define S3C64XX_GPIO_N_NR       (16)
+#define S3C64XX_GPIO_O_NR       (16)
+#define S3C64XX_GPIO_P_NR       (15)
+#define S3C64XX_GPIO_Q_NR       (9)
+
+/* GPIO bank numbes */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S3C64XX_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s3c_gpio_number {
+        S3C64XX_GPIO_A_START = 0,
+        S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
+        S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
+        S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
+        S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
+        S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
+        S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
+        S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
+        S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
+        S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
+        S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
+        S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
+        S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
+        S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
+        S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
+        S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
+        S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
+};
+
+/* S3C64XX GPIO number definitions. */
+
+#define S3C64XX_GPA(_nr)        (S3C64XX_GPIO_A_START + (_nr))
+#define S3C64XX_GPB(_nr)        (S3C64XX_GPIO_B_START + (_nr))
+#define S3C64XX_GPC(_nr)        (S3C64XX_GPIO_C_START + (_nr))
+#define S3C64XX_GPD(_nr)        (S3C64XX_GPIO_D_START + (_nr))
+#define S3C64XX_GPE(_nr)        (S3C64XX_GPIO_E_START + (_nr))
+#define S3C64XX_GPF(_nr)        (S3C64XX_GPIO_F_START + (_nr))
+#define S3C64XX_GPG(_nr)        (S3C64XX_GPIO_G_START + (_nr))
+#define S3C64XX_GPH(_nr)        (S3C64XX_GPIO_H_START + (_nr))
+#define S3C64XX_GPI(_nr)        (S3C64XX_GPIO_I_START + (_nr))
+#define S3C64XX_GPJ(_nr)        (S3C64XX_GPIO_J_START + (_nr))
+#define S3C64XX_GPK(_nr)        (S3C64XX_GPIO_K_START + (_nr))
+#define S3C64XX_GPL(_nr)        (S3C64XX_GPIO_L_START + (_nr))
+#define S3C64XX_GPM(_nr)        (S3C64XX_GPIO_M_START + (_nr))
+#define S3C64XX_GPN(_nr)        (S3C64XX_GPIO_N_START + (_nr))
+#define S3C64XX_GPO(_nr)        (S3C64XX_GPIO_O_START + (_nr))
+#define S3C64XX_GPP(_nr)        (S3C64XX_GPIO_P_START + (_nr))
+#define S3C64XX_GPQ(_nr)        (S3C64XX_GPIO_Q_START + (_nr))
+
+/* the end of the S3C64XX specific gpios */
+#define S3C64XX_GPIO_END        (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
+#define S3C_GPIO_END            S3C64XX_GPIO_END
+
+/* define the number of gpios we need to the one after the GPQ() range */
+#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
+
+#define BOARD_NR_GPIOS 16
+
+#define ARCH_NR_GPIOS   (GPIO_BOARD_START + BOARD_NR_GPIOS)
+
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s3c64xx/include/mach/hardware.h b/arch/arm/mach-s3c64xx/include/mach/hardware.h
new file mode 100644
index 000000000000..862d033e57a4
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/hardware.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - Hardware support
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h
new file mode 100644
index 000000000000..de5716dbbd65
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/io.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s3c64xxinclude/mach/io.h
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben-linux@fluff.org>
+ *
+ * Default IO routines for S3C64XX based
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No current ISA/PCI bus support. */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
new file mode 100644
index 000000000000..e9ab4ac0b9a8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -0,0 +1,216 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - IRQ support
+ */
+
+#ifndef __ASM_MACH_S3C64XX_IRQS_H
+#define __ASM_MACH_S3C64XX_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+
+#define S3C_IRQ_OFFSET  (32)
+
+#define S3C_IRQ(x)      ((x) + S3C_IRQ_OFFSET)
+
+#define IRQ_VIC0_BASE   S3C_IRQ(0)
+#define IRQ_VIC1_BASE   S3C_IRQ(32)
+
+/* UART interrupts, each UART has 4 intterupts per channel so
+ * use the space between the ISA and S3C main interrupts. Note, these
+ * are not in the same order as the S3C24XX series! */
+
+#define IRQ_S3CUART_BASE0       (16)
+#define IRQ_S3CUART_BASE1       (20)
+#define IRQ_S3CUART_BASE2       (24)
+#define IRQ_S3CUART_BASE3       (28)
+
+#define UART_IRQ_RXD            (0)
+#define UART_IRQ_ERR            (1)
+#define UART_IRQ_TXD            (2)
+#define UART_IRQ_MODEM          (3)
+
+#define IRQ_S3CUART_RX0         (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX0         (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR0        (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX1         (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX1         (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR1        (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX2         (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX2         (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR2        (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX3         (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX3         (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR3        (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
+
+/* VIC based IRQs */
+
+#define S3C64XX_IRQ_VIC0(x)     (IRQ_VIC0_BASE + (x))
+#define S3C64XX_IRQ_VIC1(x)     (IRQ_VIC1_BASE + (x))
+
+/* VIC0 */
+
+#define IRQ_EINT0_3             S3C64XX_IRQ_VIC0(0)
+#define IRQ_EINT4_11            S3C64XX_IRQ_VIC0(1)
+#define IRQ_RTC_TIC             S3C64XX_IRQ_VIC0(2)
+#define IRQ_CAMIF_C             S3C64XX_IRQ_VIC0(3)
+#define IRQ_CAMIF_P             S3C64XX_IRQ_VIC0(4)
+#define IRQ_CAMIF_MC            S3C64XX_IRQ_VIC0(5)
+#define IRQ_S3C6410_IIC1        S3C64XX_IRQ_VIC0(5)
+#define IRQ_S3C6410_IIS         S3C64XX_IRQ_VIC0(6)
+#define IRQ_S3C6400_CAMIF_MP    S3C64XX_IRQ_VIC0(6)
+#define IRQ_CAMIF_WE_C          S3C64XX_IRQ_VIC0(7)
+#define IRQ_S3C6410_G3D         S3C64XX_IRQ_VIC0(8)
+#define IRQ_S3C6400_CAMIF_WE_P  S3C64XX_IRQ_VIC0(8)
+#define IRQ_POST0               S3C64XX_IRQ_VIC0(9)
+#define IRQ_ROTATOR             S3C64XX_IRQ_VIC0(10)
+#define IRQ_2D                  S3C64XX_IRQ_VIC0(11)
+#define IRQ_TVENC               S3C64XX_IRQ_VIC0(12)
+#define IRQ_SCALER              S3C64XX_IRQ_VIC0(13)
+#define IRQ_BATF                S3C64XX_IRQ_VIC0(14)
+#define IRQ_JPEG                S3C64XX_IRQ_VIC0(15)
+#define IRQ_MFC                 S3C64XX_IRQ_VIC0(16)
+#define IRQ_SDMA0               S3C64XX_IRQ_VIC0(17)
+#define IRQ_SDMA1               S3C64XX_IRQ_VIC0(18)
+#define IRQ_ARM_DMAERR          S3C64XX_IRQ_VIC0(19)
+#define IRQ_ARM_DMA             S3C64XX_IRQ_VIC0(20)
+#define IRQ_ARM_DMAS            S3C64XX_IRQ_VIC0(21)
+#define IRQ_KEYPAD              S3C64XX_IRQ_VIC0(22)
+#define IRQ_TIMER0_VIC          S3C64XX_IRQ_VIC0(23)
+#define IRQ_TIMER1_VIC          S3C64XX_IRQ_VIC0(24)
+#define IRQ_TIMER2_VIC          S3C64XX_IRQ_VIC0(25)
+#define IRQ_WDT                 S3C64XX_IRQ_VIC0(26)
+#define IRQ_TIMER3_VIC          S3C64XX_IRQ_VIC0(27)
+#define IRQ_TIMER4_VIC          S3C64XX_IRQ_VIC0(28)
+#define IRQ_LCD_FIFO            S3C64XX_IRQ_VIC0(29)
+#define IRQ_LCD_VSYNC           S3C64XX_IRQ_VIC0(30)
+#define IRQ_LCD_SYSTEM          S3C64XX_IRQ_VIC0(31)
+
+/* VIC1 */
+
+#define IRQ_EINT12_19           S3C64XX_IRQ_VIC1(0)
+#define IRQ_EINT20_27           S3C64XX_IRQ_VIC1(1)
+#define IRQ_PCM0                S3C64XX_IRQ_VIC1(2)
+#define IRQ_PCM1                S3C64XX_IRQ_VIC1(3)
+#define IRQ_AC97                S3C64XX_IRQ_VIC1(4)
+#define IRQ_UART0               S3C64XX_IRQ_VIC1(5)
+#define IRQ_UART1               S3C64XX_IRQ_VIC1(6)
+#define IRQ_UART2               S3C64XX_IRQ_VIC1(7)
+#define IRQ_UART3               S3C64XX_IRQ_VIC1(8)
+#define IRQ_DMA0                S3C64XX_IRQ_VIC1(9)
+#define IRQ_DMA1                S3C64XX_IRQ_VIC1(10)
+#define IRQ_ONENAND0            S3C64XX_IRQ_VIC1(11)
+#define IRQ_ONENAND1            S3C64XX_IRQ_VIC1(12)
+#define IRQ_NFC                 S3C64XX_IRQ_VIC1(13)
+#define IRQ_CFCON               S3C64XX_IRQ_VIC1(14)
+#define IRQ_USBH                S3C64XX_IRQ_VIC1(15)
+#define IRQ_SPI0                S3C64XX_IRQ_VIC1(16)
+#define IRQ_SPI1                S3C64XX_IRQ_VIC1(17)
+#define IRQ_IIC                 S3C64XX_IRQ_VIC1(18)
+#define IRQ_HSItx               S3C64XX_IRQ_VIC1(19)
+#define IRQ_HSIrx               S3C64XX_IRQ_VIC1(20)
+#define IRQ_RESERVED            S3C64XX_IRQ_VIC1(21)
+#define IRQ_MSM                 S3C64XX_IRQ_VIC1(22)
+#define IRQ_HOSTIF              S3C64XX_IRQ_VIC1(23)
+#define IRQ_HSMMC0              S3C64XX_IRQ_VIC1(24)
+#define IRQ_HSMMC1              S3C64XX_IRQ_VIC1(25)
+#define IRQ_HSMMC2              IRQ_SPI1        /* shared with SPI1 */
+#define IRQ_OTG                 S3C64XX_IRQ_VIC1(26)
+#define IRQ_IRDA                S3C64XX_IRQ_VIC1(27)
+#define IRQ_RTC_ALARM           S3C64XX_IRQ_VIC1(28)
+#define IRQ_SEC                 S3C64XX_IRQ_VIC1(29)
+#define IRQ_PENDN               S3C64XX_IRQ_VIC1(30)
+#define IRQ_TC                  IRQ_PENDN
+#define IRQ_ADC                 S3C64XX_IRQ_VIC1(31)
+
+#define S3C64XX_TIMER_IRQ(x)    S3C_IRQ(64 + (x))
+
+#define IRQ_TIMER0              S3C64XX_TIMER_IRQ(0)
+#define IRQ_TIMER1              S3C64XX_TIMER_IRQ(1)
+#define IRQ_TIMER2              S3C64XX_TIMER_IRQ(2)
+#define IRQ_TIMER3              S3C64XX_TIMER_IRQ(3)
+#define IRQ_TIMER4              S3C64XX_TIMER_IRQ(4)
+
+/* compatibility for device defines */
+
+#define IRQ_IIC1                IRQ_S3C6410_IIC1
+
+/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
+ * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
+ * which we place after the pair of VICs. */
+
+#define S3C_IRQ_EINT_BASE       S3C_IRQ(64+5)
+
+#define S3C_EINT(x)             ((x) + S3C_IRQ_EINT_BASE)
+#define IRQ_EINT(x)             S3C_EINT(x)
+#define IRQ_EINT_BIT(x)         ((x) - S3C_EINT(0))
+
+/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
+ * that they are sourced from the GPIO pins but with a different scheme for
+ * priority and source indication.
+ *
+ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
+ * interrupts, but for historical reasons they are kept apart from these
+ * next interrupts.
+ *
+ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
+ * machine specific support files.
+ */
+
+#define IRQ_EINT_GROUP1_NR      (15)
+#define IRQ_EINT_GROUP2_NR      (8)
+#define IRQ_EINT_GROUP3_NR      (5)
+#define IRQ_EINT_GROUP4_NR      (14)
+#define IRQ_EINT_GROUP5_NR      (7)
+#define IRQ_EINT_GROUP6_NR      (10)
+#define IRQ_EINT_GROUP7_NR      (16)
+#define IRQ_EINT_GROUP8_NR      (15)
+#define IRQ_EINT_GROUP9_NR      (9)
+
+#define IRQ_EINT_GROUP_BASE     S3C_EINT(28)
+#define IRQ_EINT_GROUP1_BASE    (IRQ_EINT_GROUP_BASE + 0x00)
+#define IRQ_EINT_GROUP2_BASE    (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
+#define IRQ_EINT_GROUP3_BASE    (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
+#define IRQ_EINT_GROUP4_BASE    (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
+#define IRQ_EINT_GROUP5_BASE    (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
+#define IRQ_EINT_GROUP6_BASE    (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
+#define IRQ_EINT_GROUP7_BASE    (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
+#define IRQ_EINT_GROUP8_BASE    (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
+#define IRQ_EINT_GROUP9_BASE    (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
+
+#define IRQ_EINT_GROUP(group, no)       (IRQ_EINT_GROUP##group##_BASE + (no))
+
+/* Define a group of interrupts for board-specific use (eg, for MFD
+ * interrupt controllers). */
+#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
+
+#ifdef CONFIG_SMDK6410_WM1190_EV1
+#define IRQ_BOARD_NR 64
+#elif defined(CONFIG_SMDK6410_WM1192_EV1)
+#define IRQ_BOARD_NR 64
+#else
+#define IRQ_BOARD_NR 16
+#endif
+
+#define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR)
+
+/* Set the default NR_IRQS */
+
+#define NR_IRQS (IRQ_BOARD_END + 1)
+
+#endif /* __ASM_MACH_S3C64XX_IRQS_H */
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
new file mode 100644
index 000000000000..801c1c0f3a95
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -0,0 +1,107 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/map.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/*
+ * Post-mux Chip Select Regions Xm0CSn_
+ * These may be used by SROM, NAND or CF depending on settings
+ */
+
+#define S3C64XX_PA_XM0CSN0 (0x10000000)
+#define S3C64XX_PA_XM0CSN1 (0x18000000)
+#define S3C64XX_PA_XM0CSN2 (0x20000000)
+#define S3C64XX_PA_XM0CSN3 (0x28000000)
+#define S3C64XX_PA_XM0CSN4 (0x30000000)
+#define S3C64XX_PA_XM0CSN5 (0x38000000)
+
+/* HSMMC units */
+#define S3C64XX_PA_HSMMC(x)     (0x7C200000 + ((x) * 0x100000))
+#define S3C64XX_PA_HSMMC0       S3C64XX_PA_HSMMC(0)
+#define S3C64XX_PA_HSMMC1       S3C64XX_PA_HSMMC(1)
+#define S3C64XX_PA_HSMMC2       S3C64XX_PA_HSMMC(2)
+
+#define S3C_PA_UART             (0x7F005000)
+#define S3C_PA_UART0            (S3C_PA_UART + 0x00)
+#define S3C_PA_UART1            (S3C_PA_UART + 0x400)
+#define S3C_PA_UART2            (S3C_PA_UART + 0x800)
+#define S3C_PA_UART3            (S3C_PA_UART + 0xC00)
+#define S3C_UART_OFFSET         (0x400)
+
+/* See notes on UART VA mapping in debug-macro.S */
+#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
+
+#define S3C_VA_UART0            S3C_VA_UARTx(0)
+#define S3C_VA_UART1            S3C_VA_UARTx(1)
+#define S3C_VA_UART2            S3C_VA_UARTx(2)
+#define S3C_VA_UART3            S3C_VA_UARTx(3)
+
+#define S3C64XX_PA_SROM         (0x70000000)
+
+#define S3C64XX_PA_NAND         (0x70200000)
+#define S3C64XX_PA_FB           (0x77100000)
+#define S3C64XX_PA_USB_HSOTG    (0x7C000000)
+#define S3C64XX_PA_WATCHDOG     (0x7E004000)
+#define S3C64XX_PA_RTC          (0x7E005000)
+#define S3C64XX_PA_ADC          (0x7E00B000)
+#define S3C64XX_PA_SYSCON       (0x7E00F000)
+#define S3C64XX_PA_AC97         (0x7F001000)
+#define S3C64XX_PA_IIS0         (0x7F002000)
+#define S3C64XX_PA_IIS1         (0x7F003000)
+#define S3C64XX_PA_TIMER        (0x7F006000)
+#define S3C64XX_PA_IIC0         (0x7F004000)
+#define S3C64XX_PA_SPI0         (0x7F00B000)
+#define S3C64XX_PA_SPI1         (0x7F00C000)
+#define S3C64XX_PA_PCM0         (0x7F009000)
+#define S3C64XX_PA_PCM1         (0x7F00A000)
+#define S3C64XX_PA_IISV4        (0x7F00D000)
+#define S3C64XX_PA_IIC1         (0x7F00F000)
+
+#define S3C64XX_PA_GPIO         (0x7F008000)
+#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
+#define S3C64XX_SZ_GPIO         SZ_4K
+
+#define S3C64XX_PA_SDRAM        (0x50000000)
+#define S3C64XX_PA_VIC0         (0x71200000)
+#define S3C64XX_PA_VIC1         (0x71300000)
+
+#define S3C64XX_PA_MODEM        (0x74108000)
+#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
+
+#define S3C64XX_PA_USBHOST      (0x74300000)
+
+#define S3C64XX_PA_USB_HSPHY    (0x7C100000)
+#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
+
+/* place VICs close together */
+#define VA_VIC0                 (S3C_VA_IRQ + 0x00)
+#define VA_VIC1                 (S3C_VA_IRQ + 0x10000)
+
+/* compatibiltiy defines. */
+#define S3C_PA_TIMER            S3C64XX_PA_TIMER
+#define S3C_PA_HSMMC0           S3C64XX_PA_HSMMC0
+#define S3C_PA_HSMMC1           S3C64XX_PA_HSMMC1
+#define S3C_PA_HSMMC2           S3C64XX_PA_HSMMC2
+#define S3C_PA_IIC              S3C64XX_PA_IIC0
+#define S3C_PA_IIC1             S3C64XX_PA_IIC1
+#define S3C_PA_NAND             S3C64XX_PA_NAND
+#define S3C_PA_FB               S3C64XX_PA_FB
+#define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
+#define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
+#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
+
+#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h
new file mode 100644
index 000000000000..a3ac84a65480
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/memory.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s3c6400/include/mach/memory.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x50000000)
+
+#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
new file mode 100644
index 000000000000..90bbd72fdc4e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pll.h
@@ -0,0 +1,74 @@
+/* arch/arm/plat-s3c64xx/include/plat/pll.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX PLL code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C6400_PLL_MDIV_MASK   ((1 << (25-16+1)) - 1)
+#define S3C6400_PLL_PDIV_MASK   ((1 << (13-8+1)) - 1)
+#define S3C6400_PLL_SDIV_MASK   ((1 << (2-0+1)) - 1)
+#define S3C6400_PLL_MDIV_SHIFT  (16)
+#define S3C6400_PLL_PDIV_SHIFT  (8)
+#define S3C6400_PLL_SDIV_SHIFT  (0)
+
+#include <asm/div64.h>
+
+static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
+                                            u32 pllcon)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
+        pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
+        sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+#define S3C6400_EPLL_MDIV_MASK  ((1 << (23-16)) - 1)
+#define S3C6400_EPLL_PDIV_MASK  ((1 << (13-8)) - 1)
+#define S3C6400_EPLL_SDIV_MASK  ((1 << (2-0)) - 1)
+#define S3C6400_EPLL_MDIV_SHIFT (16)
+#define S3C6400_EPLL_PDIV_SHIFT (8)
+#define S3C6400_EPLL_SDIV_SHIFT (0)
+#define S3C6400_EPLL_KDIV_MASK  (0xffff)
+
+static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
+{
+        unsigned long result;
+        u32 epll0 = __raw_readl(S3C_EPLL_CON0);
+        u32 epll1 = __raw_readl(S3C_EPLL_CON1);
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
+        pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
+        sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
+        kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
+
+        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
+         * which is in 2^16ths, so shift mdiv up (does not overflow) and
+         * add kdiv before multiplying. The use of tmp is to avoid any
+         * overflows before shifting bac down into result when multipling
+         * by the mdiv and kdiv pair.
+         */
+
+        tmp = baseclk;
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
new file mode 100644
index 000000000000..1e9f20f0bb7b
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -0,0 +1,98 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+        u32 tmp = __raw_readl(S3C_PCLK_GATE);
+
+        /* As a note, since the S3C64XX UARTs generally have multiple
+         * clock sources, we simply enable PCLK at the moment and hope
+         * that the resume settings for the UART are suitable for the
+         * use with PCLK.
+         */
+
+        tmp |= S3C_CLKCON_PCLK_UART0;
+        tmp |= S3C_CLKCON_PCLK_UART1;
+        tmp |= S3C_CLKCON_PCLK_UART2;
+        tmp |= S3C_CLKCON_PCLK_UART3;
+
+        __raw_writel(tmp, S3C_PCLK_GATE);
+        udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        /* VIC should have already been taken care of */
+
+        /* clear any pending EINT0 interrupts */
+        __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+}
+
+/* make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on */
+
+#define s3c_irqwake_eintallow   ((1 << 28) - 1)
+#define s3c_irqwake_intallow    (0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                           struct pm_uart_save *save)
+{
+        u32 ucon = __raw_readl(regs + S3C2410_UCON);
+        u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+        u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+        u32 new_ucon;
+        u32 delta;
+
+        /* S3C64XX UART blocks only support level interrupts, so ensure that
+         * when we restore unused UART blocks we force the level interrupt
+         * settigs. */
+        save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+        /* We have a constraint on changing the clock type of the UART
+         * between UCLKx and PCLK, so ensure that when we restore UCON
+         * that the CLK field is correctly modified if the bootloader
+         * has changed anything.
+         */
+        if (ucon_clk != save_clk) {
+                new_ucon = save->ucon;
+                delta = ucon_clk ^ save_clk;
+
+                /* change from UCLKx => wrong PCLK,
+                 * either UCLK can be tested for by a bit-test
+                 * with UCLK0 */
+                if (ucon_clk & S3C6400_UCON_UCLK0 &&
+                    !(save_clk & S3C6400_UCON_UCLK0) &&
+                    delta & S3C6400_UCON_PCLK2) {
+                        new_ucon &= ~S3C6400_UCON_UCLK0;
+                } else if (delta == S3C6400_UCON_PCLK2) {
+                        /* as an precaution, don't change from
+                         * PCLK2 => PCLK or vice-versa */
+                        new_ucon ^= S3C6400_UCON_PCLK2;
+                }
+
+                S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+                          ucon, new_ucon, save->ucon);
+                save->ucon = new_ucon;
+        }
+}
diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
new file mode 100644
index 000000000000..b25bedee0d52
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
@@ -0,0 +1,56 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64xx - pwm clock and timer support
+ */
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+        return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+        return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+        return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+        return ilog2(div);
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
new file mode 100644
index 000000000000..3ef62741e5d1
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -0,0 +1,156 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_CLOCK_H
+#define __PLAT_REGS_CLOCK_H __FILE__
+
+#define S3C_CLKREG(x)           (S3C_VA_SYS + (x))
+
+#define S3C_APLL_LOCK           S3C_CLKREG(0x00)
+#define S3C_MPLL_LOCK           S3C_CLKREG(0x04)
+#define S3C_EPLL_LOCK           S3C_CLKREG(0x08)
+#define S3C_APLL_CON            S3C_CLKREG(0x0C)
+#define S3C_MPLL_CON            S3C_CLKREG(0x10)
+#define S3C_EPLL_CON0           S3C_CLKREG(0x14)
+#define S3C_EPLL_CON1           S3C_CLKREG(0x18)
+#define S3C_CLK_SRC             S3C_CLKREG(0x1C)
+#define S3C_CLK_DIV0            S3C_CLKREG(0x20)
+#define S3C_CLK_DIV1            S3C_CLKREG(0x24)
+#define S3C_CLK_DIV2            S3C_CLKREG(0x28)
+#define S3C_CLK_OUT             S3C_CLKREG(0x2C)
+#define S3C_HCLK_GATE           S3C_CLKREG(0x30)
+#define S3C_PCLK_GATE           S3C_CLKREG(0x34)
+#define S3C_SCLK_GATE           S3C_CLKREG(0x38)
+#define S3C_MEM0_GATE           S3C_CLKREG(0x3C)
+
+/* CLKDIV0 */
+#define S3C6400_CLKDIV0_PCLK_MASK       (0xf << 12)
+#define S3C6400_CLKDIV0_PCLK_SHIFT      (12)
+#define S3C6400_CLKDIV0_HCLK2_MASK      (0x7 << 9)
+#define S3C6400_CLKDIV0_HCLK2_SHIFT     (9)
+#define S3C6400_CLKDIV0_HCLK_MASK       (0x1 << 8)
+#define S3C6400_CLKDIV0_HCLK_SHIFT      (8)
+#define S3C6400_CLKDIV0_MPLL_MASK       (0x1 << 4)
+#define S3C6400_CLKDIV0_MPLL_SHIFT      (4)
+
+#define S3C6400_CLKDIV0_ARM_MASK        (0x7 << 0)
+#define S3C6410_CLKDIV0_ARM_MASK        (0xf << 0)
+#define S3C6400_CLKDIV0_ARM_SHIFT       (0)
+
+/* HCLK GATE Registers */
+#define S3C_CLKCON_HCLK_3DSE    (1<<31)
+#define S3C_CLKCON_HCLK_UHOST   (1<<29)
+#define S3C_CLKCON_HCLK_SECUR   (1<<28)
+#define S3C_CLKCON_HCLK_SDMA1   (1<<27)
+#define S3C_CLKCON_HCLK_SDMA0   (1<<26)
+#define S3C_CLKCON_HCLK_IROM    (1<<25)
+#define S3C_CLKCON_HCLK_DDR1    (1<<24)
+#define S3C_CLKCON_HCLK_DDR0    (1<<23)
+#define S3C_CLKCON_HCLK_MEM1    (1<<22)
+#define S3C_CLKCON_HCLK_MEM0    (1<<21)
+#define S3C_CLKCON_HCLK_USB     (1<<20)
+#define S3C_CLKCON_HCLK_HSMMC2  (1<<19)
+#define S3C_CLKCON_HCLK_HSMMC1  (1<<18)
+#define S3C_CLKCON_HCLK_HSMMC0  (1<<17)
+#define S3C_CLKCON_HCLK_MDP     (1<<16)
+#define S3C_CLKCON_HCLK_DHOST   (1<<15)
+#define S3C_CLKCON_HCLK_IHOST   (1<<14)
+#define S3C_CLKCON_HCLK_DMA1    (1<<13)
+#define S3C_CLKCON_HCLK_DMA0    (1<<12)
+#define S3C_CLKCON_HCLK_JPEG    (1<<11)
+#define S3C_CLKCON_HCLK_CAMIF   (1<<10)
+#define S3C_CLKCON_HCLK_SCALER  (1<<9)
+#define S3C_CLKCON_HCLK_2D      (1<<8)
+#define S3C_CLKCON_HCLK_TV      (1<<7)
+#define S3C_CLKCON_HCLK_POST0   (1<<5)
+#define S3C_CLKCON_HCLK_ROT     (1<<4)
+#define S3C_CLKCON_HCLK_LCD     (1<<3)
+#define S3C_CLKCON_HCLK_TZIC    (1<<2)
+#define S3C_CLKCON_HCLK_INTC    (1<<1)
+#define S3C_CLKCON_HCLK_MFC     (1<<0)
+
+/* PCLK GATE Registers */
+#define S3C6410_CLKCON_PCLK_I2C1        (1<<27)
+#define S3C6410_CLKCON_PCLK_IIS2        (1<<26)
+#define S3C_CLKCON_PCLK_SKEY            (1<<24)
+#define S3C_CLKCON_PCLK_CHIPID          (1<<23)
+#define S3C_CLKCON_PCLK_SPI1            (1<<22)
+#define S3C_CLKCON_PCLK_SPI0            (1<<21)
+#define S3C_CLKCON_PCLK_HSIRX           (1<<20)
+#define S3C_CLKCON_PCLK_HSITX           (1<<19)
+#define S3C_CLKCON_PCLK_GPIO            (1<<18)
+#define S3C_CLKCON_PCLK_IIC             (1<<17)
+#define S3C_CLKCON_PCLK_IIS1            (1<<16)
+#define S3C_CLKCON_PCLK_IIS0            (1<<15)
+#define S3C_CLKCON_PCLK_AC97            (1<<14)
+#define S3C_CLKCON_PCLK_TZPC            (1<<13)
+#define S3C_CLKCON_PCLK_TSADC           (1<<12)
+#define S3C_CLKCON_PCLK_KEYPAD          (1<<11)
+#define S3C_CLKCON_PCLK_IRDA            (1<<10)
+#define S3C_CLKCON_PCLK_PCM1            (1<<9)
+#define S3C_CLKCON_PCLK_PCM0            (1<<8)
+#define S3C_CLKCON_PCLK_PWM             (1<<7)
+#define S3C_CLKCON_PCLK_RTC             (1<<6)
+#define S3C_CLKCON_PCLK_WDT             (1<<5)
+#define S3C_CLKCON_PCLK_UART3           (1<<4)
+#define S3C_CLKCON_PCLK_UART2           (1<<3)
+#define S3C_CLKCON_PCLK_UART1           (1<<2)
+#define S3C_CLKCON_PCLK_UART0           (1<<1)
+#define S3C_CLKCON_PCLK_MFC             (1<<0)
+
+/* SCLK GATE Registers */
+#define S3C_CLKCON_SCLK_UHOST           (1<<30)
+#define S3C_CLKCON_SCLK_MMC2_48         (1<<29)
+#define S3C_CLKCON_SCLK_MMC1_48         (1<<28)
+#define S3C_CLKCON_SCLK_MMC0_48         (1<<27)
+#define S3C_CLKCON_SCLK_MMC2            (1<<26)
+#define S3C_CLKCON_SCLK_MMC1            (1<<25)
+#define S3C_CLKCON_SCLK_MMC0            (1<<24)
+#define S3C_CLKCON_SCLK_SPI1_48         (1<<23)
+#define S3C_CLKCON_SCLK_SPI0_48         (1<<22)
+#define S3C_CLKCON_SCLK_SPI1            (1<<21)
+#define S3C_CLKCON_SCLK_SPI0            (1<<20)
+#define S3C_CLKCON_SCLK_DAC27           (1<<19)
+#define S3C_CLKCON_SCLK_TV27            (1<<18)
+#define S3C_CLKCON_SCLK_SCALER27        (1<<17)
+#define S3C_CLKCON_SCLK_SCALER          (1<<16)
+#define S3C_CLKCON_SCLK_LCD27           (1<<15)
+#define S3C_CLKCON_SCLK_LCD             (1<<14)
+#define S3C6400_CLKCON_SCLK_POST1_27    (1<<13)
+#define S3C6410_CLKCON_FIMC             (1<<13)
+#define S3C_CLKCON_SCLK_POST0_27        (1<<12)
+#define S3C6400_CLKCON_SCLK_POST1       (1<<11)
+#define S3C6410_CLKCON_SCLK_AUDIO2      (1<<11)
+#define S3C_CLKCON_SCLK_POST0           (1<<10)
+#define S3C_CLKCON_SCLK_AUDIO1          (1<<9)
+#define S3C_CLKCON_SCLK_AUDIO0          (1<<8)
+#define S3C_CLKCON_SCLK_SECUR           (1<<7)
+#define S3C_CLKCON_SCLK_IRDA            (1<<6)
+#define S3C_CLKCON_SCLK_UART            (1<<5)
+#define S3C_CLKCON_SCLK_ONENAND         (1<<4)
+#define S3C_CLKCON_SCLK_MFC             (1<<3)
+#define S3C_CLKCON_SCLK_CAM             (1<<2)
+#define S3C_CLKCON_SCLK_JPEG            (1<<1)
+
+/* CLKSRC */
+
+#define S3C6400_CLKSRC_APLL_MOUT        (1 << 0)
+#define S3C6400_CLKSRC_MPLL_MOUT        (1 << 1)
+#define S3C6400_CLKSRC_EPLL_MOUT        (1 << 2)
+#define S3C6400_CLKSRC_APLL_MOUT_SHIFT  (0)
+#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT  (1)
+#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT  (2)
+#define S3C6400_CLKSRC_MFC              (1 << 4)
+
+#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
new file mode 100644
index 000000000000..f56611526c63
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * Pawel Osciak <p.osciak@samsung.com>
+ * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
+ *
+ * Framebuffer register definitions for Samsung S3C64xx.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
+
+#include <plat/regs-fb-v4.h>
+
+/* Palette registers */
+#define WIN2_PAL(_entry)                        (0x300 + ((_entry) * 2))
+#define WIN3_PAL(_entry)                        (0x320 + ((_entry) * 2))
+#define WIN4_PAL(_entry)                        (0x340 + ((_entry) * 2))
+#define WIN0_PAL(_entry)                        (0x400 + ((_entry) * 4))
+#define WIN1_PAL(_entry)                        (0x800 + ((_entry) * 4))
+
+static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
+{
+        switch (window) {
+        case 0: return WIN0_PAL(reg);
+        case 1: return WIN1_PAL(reg);
+        case 2: return WIN2_PAL(reg);
+        case 3: return WIN3_PAL(reg);
+        case 4: return WIN4_PAL(reg);
+        }
+
+        BUG();
+}
+
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
new file mode 100644
index 000000000000..82342f6fd27d
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIO memory port register definitions
+ */
+
+#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
+#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
+
+#define S3C64XX_MEM0CONSTOP     S3C64XX_GPIOREG(0x1B0)
+#define S3C64XX_MEM1CONSTOP     S3C64XX_GPIOREG(0x1B4)
+
+#define S3C64XX_MEM0CONSLP0     S3C64XX_GPIOREG(0x1C0)
+#define S3C64XX_MEM0CONSLP1     S3C64XX_GPIOREG(0x1C4)
+#define S3C64XX_MEM1CONSLP      S3C64XX_GPIOREG(0x1C8)
+
+#define S3C64XX_MEM0DRVCON      S3C64XX_GPIOREG(0x1D0)
+#define S3C64XX_MEM1DRVCON      S3C64XX_GPIOREG(0x1D4)
+
+#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..81f7f6e6832e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
@@ -0,0 +1,187 @@
+/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIO register definitions
+ */
+
+#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
+#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
+
+/* Base addresses for each of the banks */
+
+#define S3C64XX_GPIOREG(reg)    (S3C64XX_VA_GPIO + (reg))
+
+#define S3C64XX_GPA_BASE        S3C64XX_GPIOREG(0x0000)
+#define S3C64XX_GPB_BASE        S3C64XX_GPIOREG(0x0020)
+#define S3C64XX_GPC_BASE        S3C64XX_GPIOREG(0x0040)
+#define S3C64XX_GPD_BASE        S3C64XX_GPIOREG(0x0060)
+#define S3C64XX_GPE_BASE        S3C64XX_GPIOREG(0x0080)
+#define S3C64XX_GPF_BASE        S3C64XX_GPIOREG(0x00A0)
+#define S3C64XX_GPG_BASE        S3C64XX_GPIOREG(0x00C0)
+#define S3C64XX_GPH_BASE        S3C64XX_GPIOREG(0x00E0)
+#define S3C64XX_GPI_BASE        S3C64XX_GPIOREG(0x0100)
+#define S3C64XX_GPJ_BASE        S3C64XX_GPIOREG(0x0120)
+#define S3C64XX_GPK_BASE        S3C64XX_GPIOREG(0x0800)
+#define S3C64XX_GPL_BASE        S3C64XX_GPIOREG(0x0810)
+#define S3C64XX_GPM_BASE        S3C64XX_GPIOREG(0x0820)
+#define S3C64XX_GPN_BASE        S3C64XX_GPIOREG(0x0830)
+#define S3C64XX_GPO_BASE        S3C64XX_GPIOREG(0x0140)
+#define S3C64XX_GPP_BASE        S3C64XX_GPIOREG(0x0160)
+#define S3C64XX_GPQ_BASE        S3C64XX_GPIOREG(0x0180)
+
+/* SPCON */
+
+#define S3C64XX_SPCON           S3C64XX_GPIOREG(0x1A0)
+
+#define S3C64XX_SPCON_DRVCON_CAM_MASK           (0x3 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_SHIFT          (30)
+#define S3C64XX_SPCON_DRVCON_CAM_2mA            (0x0 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_4mA            (0x1 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_7mA            (0x2 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_9mA            (0x3 << 30)
+
+#define S3C64XX_SPCON_DRVCON_HSSPI_MASK         (0x3 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT        (28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_2mA          (0x0 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_4mA          (0x1 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_7mA          (0x2 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_9mA          (0x3 << 28)
+
+#define S3C64XX_SPCON_DRVCON_HSMMC_MASK         (0x3 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT        (26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_2mA          (0x0 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_4mA          (0x1 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_7mA          (0x2 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_9mA          (0x3 << 26)
+
+#define S3C64XX_SPCON_DRVCON_LCD_MASK           (0x3 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_SHIFT          (24)
+#define S3C64XX_SPCON_DRVCON_LCD_2mA            (0x0 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_4mA            (0x1 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_7mA            (0x2 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_9mA            (0x3 << 24)
+
+#define S3C64XX_SPCON_DRVCON_MODEM_MASK         (0x3 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT        (22)
+#define S3C64XX_SPCON_DRVCON_MODEM_2mA          (0x0 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_4mA          (0x1 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_7mA          (0x2 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_9mA          (0x3 << 22)
+
+#define S3C64XX_SPCON_nRSTOUT_OEN               (1 << 21)
+
+#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK       (0x3 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT      (18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA        (0x0 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA        (0x1 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA        (0x2 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA        (0x3 << 18)
+
+#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK         (0x3 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT        (16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED     (0x0 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN         (0x1 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_UP           (0x2 << 16)
+
+#define S3C64XX_SPCON_MEM1_D_PUD1_MASK          (0x3 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT         (14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED      (0x0 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN          (0x1 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_UP            (0x2 << 14)
+
+#define S3C64XX_SPCON_MEM1_D_PUD0_MASK          (0x3 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT         (12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED      (0x0 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN          (0x1 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_UP            (0x2 << 12)
+
+#define S3C64XX_SPCON_MEM0_D_PUD_MASK           (0x3 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT          (8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED       (0x0 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DOWN           (0x1 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_UP             (0x2 << 8)
+
+#define S3C64XX_SPCON_USBH_DMPD                 (1 << 7)
+#define S3C64XX_SPCON_USBH_DPPD                 (1 << 6)
+#define S3C64XX_SPCON_USBH_PUSW2                (1 << 5)
+#define S3C64XX_SPCON_USBH_PUSW1                (1 << 4)
+#define S3C64XX_SPCON_USBH_SUSPND               (1 << 3)
+
+#define S3C64XX_SPCON_LCD_SEL_MASK              (0x3 << 0)
+#define S3C64XX_SPCON_LCD_SEL_SHIFT             (0)
+#define S3C64XX_SPCON_LCD_SEL_HOST              (0x0 << 0)
+#define S3C64XX_SPCON_LCD_SEL_RGB               (0x1 << 0)
+#define S3C64XX_SPCON_LCD_SEL_606_656           (0x2 << 0)
+
+
+/* External interrupt registers */
+
+#define S3C64XX_EINT12CON       S3C64XX_GPIOREG(0x200)
+#define S3C64XX_EINT34CON       S3C64XX_GPIOREG(0x204)
+#define S3C64XX_EINT56CON       S3C64XX_GPIOREG(0x208)
+#define S3C64XX_EINT78CON       S3C64XX_GPIOREG(0x20C)
+#define S3C64XX_EINT9CON        S3C64XX_GPIOREG(0x210)
+
+#define S3C64XX_EINT12FLTCON    S3C64XX_GPIOREG(0x220)
+#define S3C64XX_EINT34FLTCON    S3C64XX_GPIOREG(0x224)
+#define S3C64XX_EINT56FLTCON    S3C64XX_GPIOREG(0x228)
+#define S3C64XX_EINT78FLTCON    S3C64XX_GPIOREG(0x22C)
+#define S3C64XX_EINT9FLTCON     S3C64XX_GPIOREG(0x230)
+
+#define S3C64XX_EINT12MASK      S3C64XX_GPIOREG(0x240)
+#define S3C64XX_EINT34MASK      S3C64XX_GPIOREG(0x244)
+#define S3C64XX_EINT56MASK      S3C64XX_GPIOREG(0x248)
+#define S3C64XX_EINT78MASK      S3C64XX_GPIOREG(0x24C)
+#define S3C64XX_EINT9MASK       S3C64XX_GPIOREG(0x250)
+
+#define S3C64XX_EINT12PEND      S3C64XX_GPIOREG(0x260)
+#define S3C64XX_EINT34PEND      S3C64XX_GPIOREG(0x264)
+#define S3C64XX_EINT56PEND      S3C64XX_GPIOREG(0x268)
+#define S3C64XX_EINT78PEND      S3C64XX_GPIOREG(0x26C)
+#define S3C64XX_EINT9PEND       S3C64XX_GPIOREG(0x270)
+
+#define S3C64XX_PRIORITY        S3C64XX_GPIOREG(0x280)
+#define S3C64XX_PRIORITY_ARB(x) (1 << (x))
+
+#define S3C64XX_SERVICE         S3C64XX_GPIOREG(0x284)
+#define S3C64XX_SERVICEPEND     S3C64XX_GPIOREG(0x288)
+
+#define S3C64XX_EINT0CON0       S3C64XX_GPIOREG(0x900)
+#define S3C64XX_EINT0CON1       S3C64XX_GPIOREG(0x904)
+#define S3C64XX_EINT0FLTCON0    S3C64XX_GPIOREG(0x910)
+#define S3C64XX_EINT0FLTCON1    S3C64XX_GPIOREG(0x914)
+#define S3C64XX_EINT0FLTCON2    S3C64XX_GPIOREG(0x918)
+#define S3C64XX_EINT0FLTCON3    S3C64XX_GPIOREG(0x91C)
+
+#define S3C64XX_EINT0MASK       S3C64XX_GPIOREG(0x920)
+#define S3C64XX_EINT0PEND       S3C64XX_GPIOREG(0x924)
+
+/* GPIO sleep configuration */
+
+#define S3C64XX_SPCONSLP        S3C64XX_GPIOREG(0x880)
+
+#define S3C64XX_SPCONSLP_TDO_PULLDOWN   (1 << 14)
+#define S3C64XX_SPCONSLP_CKE1INIT       (1 << 5)
+
+#define S3C64XX_SPCONSLP_RSTOUT_MASK    (0x3 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT0    (0x0 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT1    (0x1 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_HIZ     (0x2 << 12)
+
+#define S3C64XX_SPCONSLP_KPCOL_MASK     (0x3 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT0     (0x0 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT1     (0x1 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_INP      (0x2 << 0)
+
+
+#define S3C64XX_SLPEN           S3C64XX_GPIOREG(0x930)
+
+#define S3C64XX_SLPEN_USE_xSLP          (1 << 0)
+#define S3C64XX_SLPEN_CFG_BYSLPEN       (1 << 1)
+
+#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
new file mode 100644
index 000000000000..bcce68a0bb75
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <asm/hardware/vic.h>
+
+#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h b/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
new file mode 100644
index 000000000000..49f7759dedfa
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
@@ -0,0 +1,31 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - modem block registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_MODEM_H
+#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
+
+#define S3C64XX_MODEMREG(x)     (S3C64XX_VA_MODEM + (x))
+
+#define S3C64XX_MODEM_INT2AP                    S3C64XX_MODEMREG(0x0)
+#define S3C64XX_MODEM_INT2MODEM                 S3C64XX_MODEMREG(0x4)
+#define S3C64XX_MODEM_MIFCON                    S3C64XX_MODEMREG(0x8)
+#define S3C64XX_MODEM_MIFPCON                   S3C64XX_MODEMREG(0xC)
+#define S3C64XX_MODEM_INTCLR                    S3C64XX_MODEMREG(0x10)
+#define S3C64XX_MODEM_DMA_TXADDR                S3C64XX_MODEMREG(0x14)
+#define S3C64XX_MODEM_DMA_RXADDR                S3C64XX_MODEMREG(0x18)
+
+#define MIFPCON_INT2M_LEVEL                     (1 << 4)
+#define MIFPCON_LCD_BYPASS                      (1 << 3)
+
+#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h b/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
new file mode 100644
index 000000000000..756731b36297
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
@@ -0,0 +1,59 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
+ *
+ * Copyright 2009 Andy Green <andy@warmcat.com>
+ *
+ * S3C64XX SROM definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_SROM_H
+#define __PLAT_REGS_SROM_H __FILE__
+
+#define S3C64XX_SROMREG(x)      (S3C_VA_MEM + (x))
+
+#define S3C64XX_SROM_BW         S3C64XX_SROMREG(0)
+#define S3C64XX_SROM_BC0        S3C64XX_SROMREG(4)
+#define S3C64XX_SROM_BC1        S3C64XX_SROMREG(8)
+#define S3C64XX_SROM_BC2        S3C64XX_SROMREG(0xc)
+#define S3C64XX_SROM_BC3        S3C64XX_SROMREG(0x10)
+#define S3C64XX_SROM_BC4        S3C64XX_SROMREG(0x14)
+#define S3C64XX_SROM_BC5        S3C64XX_SROMREG(0x18)
+
+/*
+ * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
+ */
+
+#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT       0
+#define S3C64XX_SROM_BW__WAITENABLE__SHIFT      2
+#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT      3
+#define S3C64XX_SROM_BW__CS_MASK 0xf
+
+#define S3C64XX_SROM_BW__NCS0__SHIFT    0
+#define S3C64XX_SROM_BW__NCS1__SHIFT    4
+#define S3C64XX_SROM_BW__NCS2__SHIFT    8
+#define S3C64XX_SROM_BW__NCS3__SHIFT    0xc
+#define S3C64XX_SROM_BW__NCS4__SHIFT    0x10
+
+/*
+ * applies to same to BCS0 - BCS4
+ */
+
+#define S3C64XX_SROM_BCX__PMC__SHIFT    0
+#define S3C64XX_SROM_BCX__PMC__MASK     3
+#define S3C64XX_SROM_BCX__TACP__SHIFT   4
+#define S3C64XX_SROM_BCX__TACP__MASK    0xf
+#define S3C64XX_SROM_BCX__TCAH__SHIFT   8
+#define S3C64XX_SROM_BCX__TCAH__MASK    0xf
+#define S3C64XX_SROM_BCX__TCOH__SHIFT   12
+#define S3C64XX_SROM_BCX__TCOH__MASK    0xf
+#define S3C64XX_SROM_BCX__TACC__SHIFT   16
+#define S3C64XX_SROM_BCX__TACC__MASK    0x1f
+#define S3C64XX_SROM_BCX__TCOS__SHIFT   24
+#define S3C64XX_SROM_BCX__TCOS__MASK    0xf
+#define S3C64XX_SROM_BCX__TACS__SHIFT   28
+#define S3C64XX_SROM_BCX__TACS__MASK    0xf
+
+#endif /* _PLAT_REGS_SROM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
new file mode 100644
index 000000000000..69b78d9f83b8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
@@ -0,0 +1,28 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX system register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_SYS_H
+#define __PLAT_REGS_SYS_H __FILE__
+
+#define S3C_SYSREG(x)           (S3C_VA_SYS + (x))
+
+#define S3C64XX_AHB_CON0        S3C_SYSREG(0x100)
+#define S3C64XX_AHB_CON1        S3C_SYSREG(0x104)
+#define S3C64XX_AHB_CON2        S3C_SYSREG(0x108)
+
+#define S3C64XX_OTHERS          S3C_SYSREG(0x900)
+
+#define S3C64XX_OTHERS_USBMASK  (1 << 16)
+
+#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h b/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
new file mode 100644
index 000000000000..270d96ac9705
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
@@ -0,0 +1,116 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - syscon power and sleep control registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
+#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
+
+#define S3C64XX_PWR_CFG                         S3C_SYSREG(0x804)
+
+#define S3C64XX_PWRCFG_OSC_OTG_DISABLE          (1 << 17)
+#define S3C64XX_PWRCFG_MMC2_DISABLE             (1 << 16)
+#define S3C64XX_PWRCFG_MMC1_DISABLE             (1 << 15)
+#define S3C64XX_PWRCFG_MMC0_DISABLE             (1 << 14)
+#define S3C64XX_PWRCFG_HSI_DISABLE              (1 << 13)
+#define S3C64XX_PWRCFG_TS_DISABLE               (1 << 12)
+#define S3C64XX_PWRCFG_RTC_TICK_DISABLE         (1 << 11)
+#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE        (1 << 10)
+#define S3C64XX_PWRCFG_MSM_DISABLE              (1 << 9)
+#define S3C64XX_PWRCFG_KEY_DISABLE              (1 << 8)
+#define S3C64XX_PWRCFG_BATF_DISABLE             (1 << 7)
+
+#define S3C64XX_PWRCFG_CFG_WFI_MASK             (0x3 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SHIFT            (5)
+#define S3C64XX_PWRCFG_CFG_WFI_IGNORE           (0x0 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_IDLE             (0x1 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_STOP             (0x2 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SLEEP            (0x3 << 5)
+
+#define S3C64XX_PWRCFG_CFG_BATFLT_MASK          (0x3 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT         (3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE        (0x0 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ           (0x1 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP         (0x3 << 3)
+
+#define S3C64XX_PWRCFG_CFG_BAT_WAKE             (1 << 2)
+#define S3C64XX_PWRCFG_OSC27_EN                 (1 << 0)
+
+#define S3C64XX_EINT_MASK                       S3C_SYSREG(0x808)
+
+#define S3C64XX_NORMAL_CFG                      S3C_SYSREG(0x810)
+
+#define S3C64XX_NORMALCFG_IROM_ON               (1 << 30)
+#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON         (1 << 16)
+#define S3C64XX_NORMALCFG_DOMAIN_S_ON           (1 << 15)
+#define S3C64XX_NORMALCFG_DOMAIN_F_ON           (1 << 14)
+#define S3C64XX_NORMALCFG_DOMAIN_P_ON           (1 << 13)
+#define S3C64XX_NORMALCFG_DOMAIN_I_ON           (1 << 12)
+#define S3C64XX_NORMALCFG_DOMAIN_G_ON           (1 << 10)
+#define S3C64XX_NORMALCFG_DOMAIN_V_ON           (1 << 9)
+
+#define S3C64XX_STOP_CFG                        S3C_SYSREG(0x814)
+
+#define S3C64XX_STOPCFG_MEMORY_ARM_ON           (1 << 29)
+#define S3C64XX_STOPCFG_TOP_MEMORY_ON           (1 << 20)
+#define S3C64XX_STOPCFG_ARM_LOGIC_ON            (1 << 17)
+#define S3C64XX_STOPCFG_TOP_LOGIC_ON            (1 << 8)
+#define S3C64XX_STOPCFG_OSC_EN                  (1 << 0)
+
+#define S3C64XX_SLEEP_CFG                       S3C_SYSREG(0x818)
+
+#define S3C64XX_SLEEPCFG_OSC_EN                 (1 << 0)
+
+#define S3C64XX_STOP_MEM_CFG                    S3C_SYSREG(0x81c)
+
+#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN       (1 << 6)
+#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN        (1 << 5)
+#define S3C64XX_STOPMEMCFG_OTG_RETAIN           (1 << 4)
+#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN         (1 << 3)
+#define S3C64XX_STOPMEMCFG_IROM_RETAIN          (1 << 2)
+#define S3C64XX_STOPMEMCFG_IRDA_RETAIN          (1 << 1)
+#define S3C64XX_STOPMEMCFG_NFCON_RETAIN         (1 << 0)
+
+#define S3C64XX_OSC_STABLE                      S3C_SYSREG(0x824)
+#define S3C64XX_PWR_STABLE                      S3C_SYSREG(0x828)
+
+#define S3C64XX_WAKEUP_STAT                     S3C_SYSREG(0x908)
+
+#define S3C64XX_WAKEUPSTAT_MMC2                 (1 << 11)
+#define S3C64XX_WAKEUPSTAT_MMC1                 (1 << 10)
+#define S3C64XX_WAKEUPSTAT_MMC0                 (1 << 9)
+#define S3C64XX_WAKEUPSTAT_HSI                  (1 << 8)
+#define S3C64XX_WAKEUPSTAT_BATFLT               (1 << 6)
+#define S3C64XX_WAKEUPSTAT_MSM                  (1 << 5)
+#define S3C64XX_WAKEUPSTAT_KEY                  (1 << 4)
+#define S3C64XX_WAKEUPSTAT_TS                   (1 << 3)
+#define S3C64XX_WAKEUPSTAT_RTC_TICK             (1 << 2)
+#define S3C64XX_WAKEUPSTAT_RTC_ALARM            (1 << 1)
+#define S3C64XX_WAKEUPSTAT_EINT                 (1 << 0)
+
+#define S3C64XX_BLK_PWR_STAT                    S3C_SYSREG(0x90c)
+
+#define S3C64XX_BLKPWRSTAT_G                    (1 << 7)
+#define S3C64XX_BLKPWRSTAT_ETM                  (1 << 6)
+#define S3C64XX_BLKPWRSTAT_S                    (1 << 5)
+#define S3C64XX_BLKPWRSTAT_F                    (1 << 4)
+#define S3C64XX_BLKPWRSTAT_P                    (1 << 3)
+#define S3C64XX_BLKPWRSTAT_I                    (1 << 2)
+#define S3C64XX_BLKPWRSTAT_V                    (1 << 1)
+#define S3C64XX_BLKPWRSTAT_TOP                  (1 << 0)
+
+#define S3C64XX_INFORM0                         S3C_SYSREG(0xA00)
+#define S3C64XX_INFORM1                         S3C_SYSREG(0xA04)
+#define S3C64XX_INFORM2                         S3C_SYSREG(0xA08)
+#define S3C64XX_INFORM3                         S3C_SYSREG(0xA0C)
+
+#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
new file mode 100644
index 000000000000..f86958d05352
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
@@ -0,0 +1,36 @@
+/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Header file for s3c6400 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S3C6400 related SoCs */
+
+extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c6400_setup_clocks(void);
+
+extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
+
+#ifdef CONFIG_CPU_S3C6400
+
+extern  int s3c6400_init(void);
+extern void s3c6400_init_irq(void);
+extern void s3c6400_map_io(void);
+extern void s3c6400_init_clocks(int xtal);
+
+#define s3c6400_init_uarts s3c6400_common_init_uarts
+
+#else
+#define s3c6400_init_clocks NULL
+#define s3c6400_init_uarts NULL
+#define s3c6400_map_io NULL
+#define s3c6400_init NULL
+#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
new file mode 100644
index 000000000000..24f1141ffcb7
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
@@ -0,0 +1,29 @@
+/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h
+ *
+ * Copyright 2008 Openmoko,  Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Header file for s3c6410 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifdef CONFIG_CPU_S3C6410
+
+extern  int s3c6410_init(void);
+extern void s3c6410_init_irq(void);
+extern void s3c6410_map_io(void);
+extern void s3c6410_init_clocks(int xtal);
+
+#define s3c6410_init_uarts s3c6400_common_init_uarts
+
+#else
+#define s3c6410_init_clocks NULL
+#define s3c6410_init_uarts NULL
+#define s3c6410_map_io NULL
+#define s3c6410_init NULL
+#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..9d0c43b4b687
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2009 Samsung Electronics Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S3C64XX_PLAT_SPI_CLKS_H
+#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__
+
+#define S3C64XX_SPI_SRCCLK_PCLK         0
+#define S3C64XX_SPI_SRCCLK_SPIBUS       1
+#define S3C64XX_SPI_SRCCLK_48M          2
+
+#endif /* __S3C64XX_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
new file mode 100644
index 000000000000..2e58cb7a7147
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/system.h
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/system.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - system implementation
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <plat/watchdog-reset.h>
+
+static void arch_idle(void)
+{
+        /* nothing here yet */
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+        if (mode != 's')
+                arch_wdt_reset();
+
+        /* if all else fails, or mode was for soft, jump to 0 */
+        cpu_reset(0);
+}
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/tick.h b/arch/arm/mach-s3c64xx/include/mach/tick.h
new file mode 100644
index 000000000000..ebe18a9469b8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/tick.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - Timer tick support definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TICK_H
+#define __ASM_ARCH_TICK_H __FILE__
+
+/* note, the timer interrutps turn up in 2 places, the vic and then
+ * the timer block. We take the VIC as the base at the moment.
+ */
+static inline u32 s3c24xx_ostimer_pending(void)
+{
+        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
+        return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
+}
+
+#define TICK_MAX        (0xffffffff)
+
+#endif /* __ASM_ARCH_6400_TICK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/timex.h b/arch/arm/mach-s3c64xx/include/mach/timex.h
new file mode 100644
index 000000000000..fb2e8cd40829
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/timex.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-s3c64xx/include/mach/timex.h
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C6400 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c6a82a20bf2a
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-s3c6400/include/mach/uncompress.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C6400 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/map.h>
+#include <plat/uncompress.h>
+
+static void arch_detect_cpu(void)
+{
+        /* we do not need to do any cpu detection here at the moment. */
+        fifo_mask = S3C2440_UFSTAT_TXMASK;
+        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..7411ef3711a6
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+ *
+ * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C6400 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END       (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */