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-rw-r--r--arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h25
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/anubis-irq.h21
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/anubis-map.h38
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/bast-cpld.h53
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/bast-irq.h29
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/bast-map.h146
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/bast-pmu.h40
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/debug-macro.S101
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/dma.h210
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/entry-macro.S70
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/fb.h1
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/gpio-fns.h1
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h118
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/gpio-track.h33
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/gpio.h35
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/gta02.h84
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/h1940-latch.h43
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/h1940.h24
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/hardware.h42
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/idle.h24
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/io.h216
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/irqs.h202
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/leds-gpio.h28
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/map.h165
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h30
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/osiris-map.h42
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/otom-map.h30
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/pm-core.h67
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-clock.h166
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-dsc.h220
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-gpio.h602
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h70
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-irq.h53
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-lcd.h162
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-mem.h202
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-power.h40
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h48
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h23
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h30
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h24
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h194
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-sdi.h127
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/tick.h15
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/timex.h24
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/uncompress.h54
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h18
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h26
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/vr1000-map.h110
48 files changed, 4126 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
new file mode 100644
index 000000000000..1b614d5a81f3
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
@@ -0,0 +1,25 @@
1/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * ANUBIS - CPLD control constants
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_ANUBISCPLD_H
15#define __ASM_ARCH_ANUBISCPLD_H
16
17/* CTRL2 - NAND WP control, IDE Reset assert/check */
18
19#define ANUBIS_CTRL1_NANDSEL (0x3)
20
21/* IDREG - revision */
22
23#define ANUBIS_IDREG_REVMASK (0x7)
24
25#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
new file mode 100644
index 000000000000..a2a328134e34
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
@@ -0,0 +1,21 @@
1/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * ANUBIS - IRQ Number definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_ANUBISIRQ_H
15#define __ASM_ARCH_ANUBISIRQ_H
16
17#define IRQ_IDE0 IRQ_EINT2
18#define IRQ_IDE1 IRQ_EINT3
19#define IRQ_ASIX IRQ_EINT1
20
21#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
new file mode 100644
index 000000000000..c9deb3a5b2c3
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
@@ -0,0 +1,38 @@
1/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * ANUBIS - Memory map definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* needs arch/map.h including with this */
15
16#ifndef __ASM_ARCH_ANUBISMAP_H
17#define __ASM_ARCH_ANUBISMAP_H
18
19/* start peripherals off after the S3C2410 */
20
21#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
22
23#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
24
25/* we put the CPLD registers next, to get them out of the way */
26
27#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */
28#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
29
30#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */
31#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23))
32
33#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
34#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
35#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
36#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
37
38#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
new file mode 100644
index 000000000000..bee2a7a932a0
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
@@ -0,0 +1,53 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * BAST - CPLD control constants
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_BASTCPLD_H
14#define __ASM_ARCH_BASTCPLD_H
15
16/* CTRL1 - Audio LR routing */
17
18#define BAST_CPLD_CTRL1_LRCOFF (0x00)
19#define BAST_CPLD_CTRL1_LRCADC (0x01)
20#define BAST_CPLD_CTRL1_LRCDAC (0x02)
21#define BAST_CPLD_CTRL1_LRCARM (0x03)
22#define BAST_CPLD_CTRL1_LRMASK (0x03)
23
24/* CTRL2 - NAND WP control, IDE Reset assert/check */
25
26#define BAST_CPLD_CTRL2_WNAND (0x04)
27#define BAST_CPLD_CTLR2_IDERST (0x08)
28
29/* CTRL3 - rom write control, CPLD identity */
30
31#define BAST_CPLD_CTRL3_IDMASK (0x0e)
32#define BAST_CPLD_CTRL3_ROMWEN (0x01)
33
34/* CTRL4 - 8bit LCD interface control/status */
35
36#define BAST_CPLD_CTRL4_LLAT (0x01)
37#define BAST_CPLD_CTRL4_LCDRW (0x02)
38#define BAST_CPLD_CTRL4_LCDCMD (0x04)
39#define BAST_CPLD_CTRL4_LCDE2 (0x01)
40
41/* CTRL5 - DMA routing */
42
43#define BAST_CPLD_DMA0_PRIIDE (0<<0)
44#define BAST_CPLD_DMA0_SECIDE (1<<0)
45#define BAST_CPLD_DMA0_ISA15 (2<<0)
46#define BAST_CPLD_DMA0_ISA36 (3<<0)
47
48#define BAST_CPLD_DMA1_PRIIDE (0<<2)
49#define BAST_CPLD_DMA1_SECIDE (1<<2)
50#define BAST_CPLD_DMA1_ISA15 (2<<2)
51#define BAST_CPLD_DMA1_ISA36 (3<<2)
52
53#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
new file mode 100644
index 000000000000..cac428c42e7f
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
@@ -0,0 +1,29 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine BAST - IRQ Number definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_BASTIRQ_H
14#define __ASM_ARCH_BASTIRQ_H
15
16/* irq numbers to onboard peripherals */
17
18#define IRQ_USBOC IRQ_EINT18
19#define IRQ_IDE0 IRQ_EINT16
20#define IRQ_IDE1 IRQ_EINT17
21#define IRQ_PCSERIAL1 IRQ_EINT15
22#define IRQ_PCSERIAL2 IRQ_EINT14
23#define IRQ_PCPARALLEL IRQ_EINT13
24#define IRQ_ASIX IRQ_EINT11
25#define IRQ_DM9000 IRQ_EINT10
26#define IRQ_ISA IRQ_EINT9
27#define IRQ_SMALERT IRQ_EINT8
28
29#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
new file mode 100644
index 000000000000..6e7dc9d0cf0e
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
@@ -0,0 +1,146 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-map.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine BAST - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x13000000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space. We also have the board's CPLD to find register space
18 * for.
19 */
20
21#ifndef __ASM_ARCH_BASTMAP_H
22#define __ASM_ARCH_BASTMAP_H
23
24#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
25
26/* we put the CPLD registers next, to get them out of the way */
27
28#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */
29#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
30
31#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */
32#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
33
34#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */
35#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
36
37#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */
38#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
39
40/* next, we have the PC104 ISA interrupt registers */
41
42#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
43#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
44
45#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
46#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
47
48#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
49#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
50
51#define BAST_PA_LCD_RCMD1 (0x8800000)
52#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
53
54#define BAST_PA_LCD_WCMD1 (0x8000000)
55#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
56
57#define BAST_PA_LCD_RDATA1 (0x9800000)
58#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
59
60#define BAST_PA_LCD_WDATA1 (0x9000000)
61#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
62
63#define BAST_PA_LCD_RCMD2 (0xA800000)
64#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
65
66#define BAST_PA_LCD_WCMD2 (0xA000000)
67#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
68
69#define BAST_PA_LCD_RDATA2 (0xB800000)
70#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
71
72#define BAST_PA_LCD_WDATA2 (0xB000000)
73#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
74
75
76/* 0xE0000000 contains the IO space that is split by speed and
77 * wether the access is for 8 or 16bit IO... this ensures that
78 * the correct access is made
79 *
80 * 0x10000000 of space, partitioned as so:
81 *
82 * 0x00000000 to 0x04000000 8bit, slow
83 * 0x04000000 to 0x08000000 16bit, slow
84 * 0x08000000 to 0x0C000000 16bit, net
85 * 0x0C000000 to 0x10000000 16bit, fast
86 *
87 * each of these spaces has the following in:
88 *
89 * 0x00000000 to 0x01000000 16MB ISA IO space
90 * 0x01000000 to 0x02000000 16MB ISA memory space
91 * 0x02000000 to 0x02100000 1MB IDE primary channel
92 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
93 * 0x02200000 to 0x02400000 1MB IDE secondary channel
94 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
95 * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
96 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
97 * 0x02600000 to 0x02700000 1MB PC SuperIO controller
98 *
99 * the phyiscal layout of the zones are:
100 * nGCS2 - 8bit, slow
101 * nGCS3 - 16bit, slow
102 * nGCS4 - 16bit, net
103 * nGCS5 - 16bit, fast
104 */
105
106#define BAST_VA_MULTISPACE (0xE0000000)
107
108#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
109#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
110#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
111#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
112#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
113#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
114#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
115#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
116#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
117
118#define BAST_VA_MULTISPACE (0xE0000000)
119
120#define BAST_VAM_CS2 (0x00000000)
121#define BAST_VAM_CS3 (0x04000000)
122#define BAST_VAM_CS4 (0x08000000)
123#define BAST_VAM_CS5 (0x0C000000)
124
125/* physical offset addresses for the peripherals */
126
127#define BAST_PA_ISAIO (0x00000000)
128#define BAST_PA_ASIXNET (0x01000000)
129#define BAST_PA_SUPERIO (0x01800000)
130#define BAST_PA_IDEPRI (0x02000000)
131#define BAST_PA_IDEPRIAUX (0x02800000)
132#define BAST_PA_IDESEC (0x03000000)
133#define BAST_PA_IDESECAUX (0x03800000)
134#define BAST_PA_ISAMEM (0x04000000)
135#define BAST_PA_DM9000 (0x05000000)
136
137/* some configurations for the peripherals */
138
139#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
140/* */
141
142#define BAST_ASIXNET_CS BAST_VAM_CS5
143#define BAST_IDE_CS BAST_VAM_CS5
144#define BAST_DM9000_CS BAST_VAM_CS4
145
146#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
new file mode 100644
index 000000000000..4c38b39b741d
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
@@ -0,0 +1,40 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * Machine BAST - Power Management chip
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_BASTPMU_H
15#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
16
17#define BASTPMU_REG_IDENT (0x00)
18#define BASTPMU_REG_VERSION (0x01)
19#define BASTPMU_REG_DDCCTRL (0x02)
20#define BASTPMU_REG_POWER (0x03)
21#define BASTPMU_REG_RESET (0x04)
22#define BASTPMU_REG_GWO (0x05)
23#define BASTPMU_REG_WOL (0x06)
24#define BASTPMU_REG_WOR (0x07)
25#define BASTPMU_REG_UID (0x09)
26
27#define BASTPMU_EEPROM (0xC0)
28
29#define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0)
30#define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8)
31#define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9)
32
33#define BASTPMU_IDENT_0 0x53
34#define BASTPMU_IDENT_1 0x42
35#define BASTPMU_IDENT_2 0x50
36#define BASTPMU_IDENT_3 0x4d
37
38#define BASTPMU_RESET_GUARD (0x55)
39
40#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..4135de87d1f7
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -0,0 +1,101 @@
1/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Copyright (C) 2005 Simtec Electronics
7 *
8 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <mach/map.h>
16#include <mach/regs-gpio.h>
17#include <plat/regs-serial.h>
18
19#define S3C2410_UART1_OFF (0x4000)
20#define SHIFT_2440TXF (14-9)
21
22 .macro addruart, rp, rv, tmp
23 ldr \rp, = S3C24XX_PA_UART
24 ldr \rv, = S3C24XX_VA_UART
25#if CONFIG_DEBUG_S3C_UART != 0
26 add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
27 add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
28#endif
29 .endm
30
31 .macro fifo_full_s3c24xx rd, rx
32 @ check for arm920 vs arm926. currently assume all arm926
33 @ devices have an 64 byte FIFO identical to the s3c2440
34 mrc p15, 0, \rd, c0, c0
35 and \rd, \rd, #0xff0
36 teq \rd, #0x260
37 beq 1004f
38 mrc p15, 0, \rd, c1, c0
39 tst \rd, #1
40 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
41 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
42 bic \rd, \rd, #0xff000
43 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
44 and \rd, \rd, #0x00ff0000
45 teq \rd, #0x00440000 @ is it 2440?
461004:
47 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
48 moveq \rd, \rd, lsr #SHIFT_2440TXF
49 tst \rd, #S3C2410_UFSTAT_TXFULL
50 .endm
51
52 .macro fifo_full_s3c2410 rd, rx
53 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
54 tst \rd, #S3C2410_UFSTAT_TXFULL
55 .endm
56
57/* fifo level reading */
58
59 .macro fifo_level_s3c24xx rd, rx
60 @ check for arm920 vs arm926. currently assume all arm926
61 @ devices have an 64 byte FIFO identical to the s3c2440
62 mrc p15, 0, \rd, c0, c0
63 and \rd, \rd, #0xff0
64 teq \rd, #0x260
65 beq 10000f
66 mrc p15, 0, \rd, c1, c0
67 tst \rd, #1
68 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
69 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
70 bic \rd, \rd, #0xff000
71 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
72 and \rd, \rd, #0x00ff0000
73 teq \rd, #0x00440000 @ is it 2440?
74
7510000:
76 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
77 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
78 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
79 .endm
80
81 .macro fifo_level_s3c2410 rd, rx
82 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
83 and \rd, \rd, #S3C2410_UFSTAT_TXMASK
84 .endm
85
86/* Select the correct implementation depending on the configuration. The
87 * S3C2440 will get selected by default, as these are the most widely
88 * used variants of these
89*/
90
91#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
92#define fifo_full fifo_full_s3c2410
93#define fifo_level fifo_level_s3c2410
94#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
95#define fifo_full fifo_full_s3c24xx
96#define fifo_level fifo_level_s3c24xx
97#endif
98
99/* include the reset of the code which will do the work */
100
101#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
new file mode 100644
index 000000000000..acbdfecd4186
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -0,0 +1,210 @@
1/* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H __FILE__
15
16#include <linux/device.h>
17
18#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
19
20/* We use `virtual` dma channels to hide the fact we have only a limited
21 * number of DMA channels, and not of all of them (dependent on the device)
22 * can be attached to any DMA source. We therefore let the DMA core handle
23 * the allocation of hardware channels to clients.
24*/
25
26enum dma_ch {
27 DMACH_XD0,
28 DMACH_XD1,
29 DMACH_SDI,
30 DMACH_SPI0,
31 DMACH_SPI1,
32 DMACH_UART0,
33 DMACH_UART1,
34 DMACH_UART2,
35 DMACH_TIMER,
36 DMACH_I2S_IN,
37 DMACH_I2S_OUT,
38 DMACH_PCM_IN,
39 DMACH_PCM_OUT,
40 DMACH_MIC_IN,
41 DMACH_USB_EP1,
42 DMACH_USB_EP2,
43 DMACH_USB_EP3,
44 DMACH_USB_EP4,
45 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
46 DMACH_UART1_SRC2,
47 DMACH_UART2_SRC2,
48 DMACH_UART3, /* s3c2443 has extra uart */
49 DMACH_UART3_SRC2,
50 DMACH_MAX, /* the end entry */
51};
52
53static inline bool samsung_dma_has_circular(void)
54{
55 return false;
56}
57
58static inline bool samsung_dma_is_dmadev(void)
59{
60 return false;
61}
62
63#include <plat/dma.h>
64
65#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
66
67/* we have 4 dma channels */
68#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
69#define S3C_DMA_CHANNELS (4)
70#else
71#define S3C_DMA_CHANNELS (6)
72#endif
73
74/* types */
75
76enum s3c2410_dma_state {
77 S3C2410_DMA_IDLE,
78 S3C2410_DMA_RUNNING,
79 S3C2410_DMA_PAUSED
80};
81
82/* enum s3c2410_dma_loadst
83 *
84 * This represents the state of the DMA engine, wrt to the loaded / running
85 * transfers. Since we don't have any way of knowing exactly the state of
86 * the DMA transfers, we need to know the state to make decisions on wether
87 * we can
88 *
89 * S3C2410_DMA_NONE
90 *
91 * There are no buffers loaded (the channel should be inactive)
92 *
93 * S3C2410_DMA_1LOADED
94 *
95 * There is one buffer loaded, however it has not been confirmed to be
96 * loaded by the DMA engine. This may be because the channel is not
97 * yet running, or the DMA driver decided that it was too costly to
98 * sit and wait for it to happen.
99 *
100 * S3C2410_DMA_1RUNNING
101 *
102 * The buffer has been confirmed running, and not finisged
103 *
104 * S3C2410_DMA_1LOADED_1RUNNING
105 *
106 * There is a buffer waiting to be loaded by the DMA engine, and one
107 * currently running.
108*/
109
110enum s3c2410_dma_loadst {
111 S3C2410_DMALOAD_NONE,
112 S3C2410_DMALOAD_1LOADED,
113 S3C2410_DMALOAD_1RUNNING,
114 S3C2410_DMALOAD_1LOADED_1RUNNING,
115};
116
117
118/* flags */
119
120#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
121 * waiting for reloads */
122#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
123
124#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
125
126/* dma buffer */
127
128struct s3c2410_dma_buf;
129
130/* s3c2410_dma_buf
131 *
132 * internally used buffer structure to describe a queued or running
133 * buffer.
134*/
135
136struct s3c2410_dma_buf {
137 struct s3c2410_dma_buf *next;
138 int magic; /* magic */
139 int size; /* buffer size in bytes */
140 dma_addr_t data; /* start of DMA data */
141 dma_addr_t ptr; /* where the DMA got to [1] */
142 void *id; /* client's id */
143};
144
145/* [1] is this updated for both recv/send modes? */
146
147struct s3c2410_dma_stats {
148 unsigned long loads;
149 unsigned long timeout_longest;
150 unsigned long timeout_shortest;
151 unsigned long timeout_avg;
152 unsigned long timeout_failed;
153};
154
155struct s3c2410_dma_map;
156
157/* struct s3c2410_dma_chan
158 *
159 * full state information for each DMA channel
160*/
161
162struct s3c2410_dma_chan {
163 /* channel state flags and information */
164 unsigned char number; /* number of this dma channel */
165 unsigned char in_use; /* channel allocated */
166 unsigned char irq_claimed; /* irq claimed for channel */
167 unsigned char irq_enabled; /* irq enabled for channel */
168 unsigned char xfer_unit; /* size of an transfer */
169
170 /* channel state */
171
172 enum s3c2410_dma_state state;
173 enum s3c2410_dma_loadst load_state;
174 struct s3c2410_dma_client *client;
175
176 /* channel configuration */
177 enum dma_data_direction source;
178 enum dma_ch req_ch;
179 unsigned long dev_addr;
180 unsigned long load_timeout;
181 unsigned int flags; /* channel flags */
182
183 struct s3c24xx_dma_map *map; /* channel hw maps */
184
185 /* channel's hardware position and configuration */
186 void __iomem *regs; /* channels registers */
187 void __iomem *addr_reg; /* data address register */
188 unsigned int irq; /* channel irq */
189 unsigned long dcon; /* default value of DCON */
190
191 /* driver handles */
192 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
193 s3c2410_dma_opfn_t op_fn; /* channel op callback */
194
195 /* stats gathering */
196 struct s3c2410_dma_stats *stats;
197 struct s3c2410_dma_stats stats_store;
198
199 /* buffer list and information */
200 struct s3c2410_dma_buf *curr; /* current dma buffer */
201 struct s3c2410_dma_buf *next; /* next buffer to load */
202 struct s3c2410_dma_buf *end; /* end of queue */
203
204 /* system device */
205 struct device dev;
206};
207
208typedef unsigned long dma_device_t;
209
210#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..7615a14773fa
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
@@ -0,0 +1,70 @@
1/*
2 * arch/arm/mach-s3c2410/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for S3C2410-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9*/
10
11/* We have a problem that the INTOFFSET register does not always
12 * show one interrupt. Occasionally we get two interrupts through
13 * the prioritiser, and this causes the INTOFFSET register to show
14 * what looks like the logical-or of the two interrupt numbers.
15 *
16 * Thanks to Klaus, Shannon, et al for helping to debug this problem
17*/
18
19#define INTPND (0x10)
20#define INTOFFSET (0x14)
21
22#include <mach/hardware.h>
23#include <asm/irq.h>
24
25 .macro get_irqnr_preamble, base, tmp
26 .endm
27
28 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
29
30 mov \base, #S3C24XX_VA_IRQ
31
32 @@ try the interrupt offset register, since it is there
33
34 ldr \irqstat, [ \base, #INTPND ]
35 teq \irqstat, #0
36 beq 1002f
37 ldr \irqnr, [ \base, #INTOFFSET ]
38 mov \tmp, #1
39 tst \irqstat, \tmp, lsl \irqnr
40 bne 1001f
41
42 @@ the number specified is not a valid irq, so try
43 @@ and work it out for ourselves
44
45 mov \irqnr, #0 @@ start here
46
47 @@ work out which irq (if any) we got
48
49 movs \tmp, \irqstat, lsl#16
50 addeq \irqnr, \irqnr, #16
51 moveq \irqstat, \irqstat, lsr#16
52 tst \irqstat, #0xff
53 addeq \irqnr, \irqnr, #8
54 moveq \irqstat, \irqstat, lsr#8
55 tst \irqstat, #0xf
56 addeq \irqnr, \irqnr, #4
57 moveq \irqstat, \irqstat, lsr#4
58 tst \irqstat, #0x3
59 addeq \irqnr, \irqnr, #2
60 moveq \irqstat, \irqstat, lsr#2
61 tst \irqstat, #0x1
62 addeq \irqnr, \irqnr, #1
63
64 @@ we have the value
651001:
66 adds \irqnr, \irqnr, #IRQ_EINT0
671002:
68 @@ exit here, Z flag unset if IRQ
69
70 .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/fb.h b/arch/arm/mach-s3c24xx/include/mach/fb.h
new file mode 100644
index 000000000000..a957bc8ed44f
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/fb.h
@@ -0,0 +1 @@
#include <plat/fb-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
new file mode 100644
index 000000000000..c53ad34c6579
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
@@ -0,0 +1 @@
#include <plat/gpio-fns.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
new file mode 100644
index 000000000000..019ea86057f6
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
@@ -0,0 +1,118 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 - GPIO bank numbering
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __MACH_GPIONRS_H
15#define __MACH_GPIONRS_H
16
17#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
18
19#define S3C2410_GPIO_BANKG (32*6)
20#define S3C2410_GPIO_BANKH (32*7)
21
22/* GPIO sizes for various SoCs:
23 *
24 * 2442
25 * 2410 2412 2440 2443 2416
26 * ---- ---- ---- ---- ----
27 * A 23 22 25 16 25
28 * B 11 11 11 11 9
29 * C 16 15 16 16 16
30 * D 16 16 16 16 16
31 * E 16 16 16 16 16
32 * F 8 8 8 8 8
33 * G 16 16 16 16 8
34 * H 11 11 9 15 15
35 * J -- -- 13 16 --
36 * K -- -- -- -- 16
37 * L -- -- -- 15 7
38 * M -- -- -- 2 2
39 */
40
41/* GPIO bank sizes */
42#define S3C2410_GPIO_A_NR (32)
43#define S3C2410_GPIO_B_NR (32)
44#define S3C2410_GPIO_C_NR (32)
45#define S3C2410_GPIO_D_NR (32)
46#define S3C2410_GPIO_E_NR (32)
47#define S3C2410_GPIO_F_NR (32)
48#define S3C2410_GPIO_G_NR (32)
49#define S3C2410_GPIO_H_NR (32)
50#define S3C2410_GPIO_J_NR (32) /* technically 16. */
51#define S3C2410_GPIO_K_NR (32) /* technically 16. */
52#define S3C2410_GPIO_L_NR (32) /* technically 15. */
53#define S3C2410_GPIO_M_NR (32) /* technically 2. */
54
55#if CONFIG_S3C_GPIO_SPACE != 0
56#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
57#endif
58
59#define S3C2410_GPIO_NEXT(__gpio) \
60 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
61
62#ifndef __ASSEMBLY__
63
64enum s3c_gpio_number {
65 S3C2410_GPIO_A_START = 0,
66 S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
67 S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
68 S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
69 S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
70 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
71 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
72 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
73 S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
74 S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
75 S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
76 S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
77};
78
79#endif /* __ASSEMBLY__ */
80
81/* S3C2410 GPIO number definitions. */
82
83#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
84#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
85#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
86#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
87#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
88#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
89#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
90#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
91#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
92#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
93#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
94#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
95
96/* compatibility until drivers can be modified */
97
98#define S3C2410_GPA0 S3C2410_GPA(0)
99#define S3C2410_GPA1 S3C2410_GPA(1)
100#define S3C2410_GPA3 S3C2410_GPA(3)
101#define S3C2410_GPA7 S3C2410_GPA(7)
102
103#define S3C2410_GPE0 S3C2410_GPE(0)
104#define S3C2410_GPE1 S3C2410_GPE(1)
105#define S3C2410_GPE2 S3C2410_GPE(2)
106#define S3C2410_GPE3 S3C2410_GPE(3)
107#define S3C2410_GPE4 S3C2410_GPE(4)
108#define S3C2410_GPE5 S3C2410_GPE(5)
109#define S3C2410_GPE6 S3C2410_GPE(6)
110#define S3C2410_GPE7 S3C2410_GPE(7)
111#define S3C2410_GPE8 S3C2410_GPE(8)
112#define S3C2410_GPE9 S3C2410_GPE(9)
113#define S3C2410_GPE10 S3C2410_GPE(10)
114
115#define S3C2410_GPH10 S3C2410_GPH(10)
116
117#endif /* __MACH_GPIONRS_H */
118
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
new file mode 100644
index 000000000000..c410a078622c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
@@ -0,0 +1,33 @@
1/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C2410 - GPIO core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_GPIO_CORE_H
16#define __ASM_ARCH_GPIO_CORE_H __FILE__
17
18#include <mach/regs-gpio.h>
19
20extern struct samsung_gpio_chip s3c24xx_gpios[];
21
22static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
23{
24 struct samsung_gpio_chip *chip;
25
26 if (pin > S3C_GPIO_END)
27 return NULL;
28
29 chip = &s3c24xx_gpios[pin/32];
30 return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
31}
32
33#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
new file mode 100644
index 000000000000..6fac70f3484e
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h
@@ -0,0 +1,35 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 - GPIO lib support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* some boards require extra gpio capacity to support external
15 * devices that need GPIO.
16 */
17
18#ifdef CONFIG_CPU_S3C244X
19#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
20#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
21#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
22#else
23#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
24#endif
25
26#include <mach/gpio-nrs.h>
27#include <mach/gpio-fns.h>
28
29#ifdef CONFIG_CPU_S3C244X
30#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
31#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
32#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
33#else
34#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
35#endif
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/include/mach/gta02.h
new file mode 100644
index 000000000000..3a56a229cac6
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/gta02.h
@@ -0,0 +1,84 @@
1#ifndef _GTA02_H
2#define _GTA02_H
3
4#include <mach/regs-gpio.h>
5
6/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
7#define GTA02v1_SYSTEM_REV 0x00000310
8#define GTA02v2_SYSTEM_REV 0x00000320
9#define GTA02v3_SYSTEM_REV 0x00000330
10#define GTA02v4_SYSTEM_REV 0x00000340
11#define GTA02v5_SYSTEM_REV 0x00000350
12/* since A7 is basically same as A6, we use A6 PCB ID */
13#define GTA02v6_SYSTEM_REV 0x00000360
14
15#define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */
16
17#define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0)
18#define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1)
19#define GTA02_GPIO_AUX_LED S3C2410_GPB(2)
20#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3)
21#define GTA02_GPIO_MODEM_RST S3C2410_GPB(5)
22#define GTA02_GPIO_BT_EN S3C2410_GPB(6)
23#define GTA02_GPIO_MODEM_ON S3C2410_GPB(7)
24#define GTA02_GPIO_EXTINT8 S3C2410_GPB(8)
25#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9)
26
27#define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */
28
29#define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */
30#define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */
31#define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */
32
33#define GTA02_GPIO_nG1_INT S3C2410_GPF(0)
34#define GTA02_GPIO_IO1 S3C2410_GPF(1)
35#define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */
36#define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4)
37#define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */
38#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6)
39#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7)
40
41#define GTA02_GPIO_3D_IRQ S3C2410_GPG(4)
42#define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */
43#define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */
44#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */
45#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */
46
47#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
48#define GTA02v1_GPIO_WLAN_GPIO10 S3C2410_GPJ(2)
49#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
50#define GTA02_GPIO_INT0 S3C2410_GPJ(3) /* v2 + v3 + v4 only */
51#define GTA02_GPIO_nGSM_EN S3C2410_GPJ(4)
52#define GTA02_GPIO_3D_RESET S3C2410_GPJ(5)
53#define GTA02_GPIO_nDL_GSM S3C2410_GPJ(6) /* v4 + v5 only */
54#define GTA02_GPIO_WLAN_GPIO0 S3C2410_GPJ(7)
55#define GTA02v1_GPIO_BAT_ID S3C2410_GPJ(8)
56#define GTA02_GPIO_KEEPACT S3C2410_GPJ(8)
57#define GTA02v1_GPIO_HP_IN S3C2410_GPJ(10)
58#define GTA02_CHIP_PWD S3C2410_GPJ(11) /* v2 + v3 + v4 only */
59#define GTA02_GPIO_nWLAN_RESET S3C2410_GPJ(12) /* v2 + v3 + v4 only */
60
61#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0
62#define GTA02_IRQ_MODEM IRQ_EINT1
63#define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */
64#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4
65#define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5
66#define GTA02_IRQ_AUX IRQ_EINT6
67#define GTA02_IRQ_nHOLD IRQ_EINT7
68#define GTA02_IRQ_PCF50633 IRQ_EINT9
69#define GTA02_IRQ_3D IRQ_EINT12
70#define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */
71#define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */
72#define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */
73#define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */
74
75/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
76#define GTA02_PCB_ID1_0 S3C2410_GPC(13)
77#define GTA02_PCB_ID1_1 S3C2410_GPC(15)
78#define GTA02_PCB_ID1_2 S3C2410_GPD(0)
79#define GTA02_PCB_ID2_0 S3C2410_GPD(3)
80#define GTA02_PCB_ID2_1 S3C2410_GPD(4)
81
82int gta02_get_pcb_revision(void);
83
84#endif /* _GTA02_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h b/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
new file mode 100644
index 000000000000..fc897d3a056c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
@@ -0,0 +1,43 @@
1/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * iPAQ H1940 series - latch definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_H1940_LATCH_H
15#define __ASM_ARCH_H1940_LATCH_H
16
17#include <asm/gpio.h>
18
19#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
20
21/* SD layer latch */
22
23#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0)
24#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1)
25#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2)
26#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3)
27#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4)
28#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5)
29#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6)
30#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7)
31
32/* CPU layer latch */
33
34#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8)
35#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9)
36#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10)
37#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11)
38#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12)
39#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13)
40#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
41#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
42
43#endif /* __ASM_ARCH_H1940_LATCH_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940.h b/arch/arm/mach-s3c24xx/include/mach/h1940.h
new file mode 100644
index 000000000000..2aa683c8d3d6
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/h1940.h
@@ -0,0 +1,24 @@
1/* arch/arm/mach-s3c2410/include/mach/h1940.h
2 *
3 * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_H1940_H
13#define __ASM_ARCH_H1940_H
14
15#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
16#define H1940_SUSPEND_RESUMEAT (0x30081000)
17#define H1940_SUSPEND_CHECK (0x30080000)
18
19extern void h1940_pm_return(void);
20extern int h1940_led_blink_set(unsigned gpio, int state,
21 unsigned long *delay_on, unsigned long *delay_off);
22
23
24#endif /* __ASM_ARCH_H1940_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
new file mode 100644
index 000000000000..aef5631eac58
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
@@ -0,0 +1,42 @@
1/* arch/arm/mach-s3c2410/include/mach/hardware.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - hardware
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H
15
16#ifndef __ASSEMBLY__
17
18extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
19
20#ifdef CONFIG_CPU_S3C2440
21
22extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
23
24#endif /* CONFIG_CPU_S3C2440 */
25
26#ifdef CONFIG_CPU_S3C2412
27
28extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
29
30#endif /* CONFIG_CPU_S3C2412 */
31
32#endif /* __ASSEMBLY__ */
33
34#include <asm/sizes.h>
35#include <mach/map.h>
36
37/* machine specific hardware definitions should go after this */
38
39/* currently here until moved into config (todo) */
40#define CONFIG_NO_MULTIWORD_IO
41
42#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/idle.h b/arch/arm/mach-s3c24xx/include/mach/idle.h
new file mode 100644
index 000000000000..e9ddd706b16e
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/idle.h
@@ -0,0 +1,24 @@
1/* arch/arm/mach-s3c2410/include/mach/idle.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 CPU Idle controls
11*/
12
13#ifndef __ASM_ARCH_IDLE_H
14#define __ASM_ARCH_IDLE_H __FILE__
15
16/* This allows the over-ride of the default idle code, in case there
17 * is any other things to be done over idle (like DVS)
18*/
19
20extern void (*s3c24xx_idle)(void);
21
22extern void s3c24xx_default_idle(void);
23
24#endif /* __ASM_ARCH_IDLE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/io.h b/arch/arm/mach-s3c24xx/include/mach/io.h
new file mode 100644
index 000000000000..118749f37c4c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/io.h
@@ -0,0 +1,216 @@
1/*
2 * arch/arm/mach-s3c2410/include/mach/io.h
3 * from arch/arm/mach-rpc/include/mach/io.h
4 *
5 * Copyright (C) 1997 Russell King
6 * (C) 2003 Simtec Electronics
7*/
8
9#ifndef __ASM_ARM_ARCH_IO_H
10#define __ASM_ARM_ARCH_IO_H
11
12#include <mach/hardware.h>
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16/*
17 * We use two different types of addressing - PC style addresses, and ARM
18 * addresses. PC style accesses the PC hardware with the normal PC IO
19 * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
20 * and are translated to the start of IO. Note that all addresses are
21 * not shifted left!
22 */
23
24#define __PORT_PCIO(x) ((x) < (1<<28))
25
26#define PCIO_BASE (S3C24XX_VA_ISA_WORD)
27#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE)
28#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD)
29#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD)
30/*
31 * Dynamic IO functions - let the compiler
32 * optimize the expressions
33 */
34
35#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
36static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
37{ \
38 unsigned long temp; \
39 __asm__ __volatile__( \
40 "cmp %2, #(1<<28)\n\t" \
41 "mov %0, %2\n\t" \
42 "addcc %0, %0, %3\n\t" \
43 "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
44 : "=&r" (temp) \
45 : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
46 : "cc"); \
47}
48
49
50#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
51static inline unsigned sz __in##fnsuffix (unsigned int port) \
52{ \
53 unsigned long temp, value; \
54 __asm__ __volatile__( \
55 "cmp %2, #(1<<28)\n\t" \
56 "mov %0, %2\n\t" \
57 "addcc %0, %0, %3\n\t" \
58 "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
59 : "=&r" (temp), "=r" (value) \
60 : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
61 : "cc"); \
62 return (unsigned sz)value; \
63}
64
65static inline void __iomem *__ioaddr (unsigned long port)
66{
67 return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
68}
69
70#define DECLARE_IO(sz,fnsuffix,instr) \
71 DECLARE_DYN_IN(sz,fnsuffix,instr) \
72 DECLARE_DYN_OUT(sz,fnsuffix,instr)
73
74DECLARE_IO(char,b,"b")
75DECLARE_IO(short,w,"h")
76DECLARE_IO(int,l,"")
77
78#undef DECLARE_IO
79#undef DECLARE_DYN_IN
80
81/*
82 * Constant address IO functions
83 *
84 * These have to be macros for the 'J' constraint to work -
85 * +/-4096 immediate operand.
86 */
87#define __outbc(value,port) \
88({ \
89 if (__PORT_PCIO((port))) \
90 __asm__ __volatile__( \
91 "strb %0, [%1, %2] @ outbc" \
92 : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
93 else \
94 __asm__ __volatile__( \
95 "strb %0, [%1, #0] @ outbc" \
96 : : "r" (value), "r" ((port))); \
97})
98
99#define __inbc(port) \
100({ \
101 unsigned char result; \
102 if (__PORT_PCIO((port))) \
103 __asm__ __volatile__( \
104 "ldrb %0, [%1, %2] @ inbc" \
105 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
106 else \
107 __asm__ __volatile__( \
108 "ldrb %0, [%1, #0] @ inbc" \
109 : "=r" (result) : "r" ((port))); \
110 result; \
111})
112
113#define __outwc(value,port) \
114({ \
115 unsigned long v = value; \
116 if (__PORT_PCIO((port))) { \
117 if ((port) < 256 && (port) > -256) \
118 __asm__ __volatile__( \
119 "strh %0, [%1, %2] @ outwc" \
120 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
121 else if ((port) > 0) \
122 __asm__ __volatile__( \
123 "strh %0, [%1, %2] @ outwc" \
124 : : "r" (v), \
125 "r" (PCIO_BASE + ((port) & ~0xff)), \
126 "Jr" (((port) & 0xff))); \
127 else \
128 __asm__ __volatile__( \
129 "strh %0, [%1, #0] @ outwc" \
130 : : "r" (v), \
131 "r" (PCIO_BASE + (port))); \
132 } else \
133 __asm__ __volatile__( \
134 "strh %0, [%1, #0] @ outwc" \
135 : : "r" (v), "r" ((port))); \
136})
137
138#define __inwc(port) \
139({ \
140 unsigned short result; \
141 if (__PORT_PCIO((port))) { \
142 if ((port) < 256 && (port) > -256 ) \
143 __asm__ __volatile__( \
144 "ldrh %0, [%1, %2] @ inwc" \
145 : "=r" (result) \
146 : "r" (PCIO_BASE), \
147 "Jr" ((port))); \
148 else if ((port) > 0) \
149 __asm__ __volatile__( \
150 "ldrh %0, [%1, %2] @ inwc" \
151 : "=r" (result) \
152 : "r" (PCIO_BASE + ((port) & ~0xff)), \
153 "Jr" (((port) & 0xff))); \
154 else \
155 __asm__ __volatile__( \
156 "ldrh %0, [%1, #0] @ inwc" \
157 : "=r" (result) \
158 : "r" (PCIO_BASE + ((port)))); \
159 } else \
160 __asm__ __volatile__( \
161 "ldrh %0, [%1, #0] @ inwc" \
162 : "=r" (result) : "r" ((port))); \
163 result; \
164})
165
166#define __outlc(value,port) \
167({ \
168 unsigned long v = value; \
169 if (__PORT_PCIO((port))) \
170 __asm__ __volatile__( \
171 "str %0, [%1, %2] @ outlc" \
172 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
173 else \
174 __asm__ __volatile__( \
175 "str %0, [%1, #0] @ outlc" \
176 : : "r" (v), "r" ((port))); \
177})
178
179#define __inlc(port) \
180({ \
181 unsigned long result; \
182 if (__PORT_PCIO((port))) \
183 __asm__ __volatile__( \
184 "ldr %0, [%1, %2] @ inlc" \
185 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
186 else \
187 __asm__ __volatile__( \
188 "ldr %0, [%1, #0] @ inlc" \
189 : "=r" (result) : "r" ((port))); \
190 result; \
191})
192
193#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
194
195#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
196#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
197#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
198#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
199#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
200#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
201#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
202
203#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
204#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
205#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
206
207#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
208#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
209#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
210
211/*
212 * 1:1 mapping for ioremapped regions.
213 */
214#define __mem_pci(x) (x)
215
216#endif
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
new file mode 100644
index 000000000000..e53b2177319e
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -0,0 +1,202 @@
1/* arch/arm/mach-s3c2410/include/mach/irqs.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef __ASM_ARCH_IRQS_H
13#define __ASM_ARCH_IRQS_H __FILE__
14
15/* we keep the first set of CPU IRQs out of the range of
16 * the ISA space, so that the PC104 has them to itself
17 * and we don't end up having to do horrible things to the
18 * standard ISA drivers....
19 */
20
21#define S3C2410_CPUIRQ_OFFSET (16)
22
23#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
24
25/* main cpu interrupts */
26#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
27#define IRQ_EINT1 S3C2410_IRQ(1)
28#define IRQ_EINT2 S3C2410_IRQ(2)
29#define IRQ_EINT3 S3C2410_IRQ(3)
30#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
31#define IRQ_EINT8t23 S3C2410_IRQ(5)
32#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
33#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
34#define IRQ_BATT_FLT S3C2410_IRQ(7)
35#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
36#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
37#define IRQ_TIMER0 S3C2410_IRQ(10)
38#define IRQ_TIMER1 S3C2410_IRQ(11)
39#define IRQ_TIMER2 S3C2410_IRQ(12)
40#define IRQ_TIMER3 S3C2410_IRQ(13)
41#define IRQ_TIMER4 S3C2410_IRQ(14)
42#define IRQ_UART2 S3C2410_IRQ(15)
43#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
44#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
45#define IRQ_DMA1 S3C2410_IRQ(18)
46#define IRQ_DMA2 S3C2410_IRQ(19)
47#define IRQ_DMA3 S3C2410_IRQ(20)
48#define IRQ_SDI S3C2410_IRQ(21)
49#define IRQ_SPI0 S3C2410_IRQ(22)
50#define IRQ_UART1 S3C2410_IRQ(23)
51#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
52#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
53#define IRQ_USBD S3C2410_IRQ(25)
54#define IRQ_USBH S3C2410_IRQ(26)
55#define IRQ_IIC S3C2410_IRQ(27)
56#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
57#define IRQ_SPI1 S3C2410_IRQ(29)
58#define IRQ_RTC S3C2410_IRQ(30)
59#define IRQ_ADCPARENT S3C2410_IRQ(31)
60
61/* interrupts generated from the external interrupts sources */
62#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
63#define IRQ_EINT5 S3C2410_IRQ(33)
64#define IRQ_EINT6 S3C2410_IRQ(34)
65#define IRQ_EINT7 S3C2410_IRQ(35)
66#define IRQ_EINT8 S3C2410_IRQ(36)
67#define IRQ_EINT9 S3C2410_IRQ(37)
68#define IRQ_EINT10 S3C2410_IRQ(38)
69#define IRQ_EINT11 S3C2410_IRQ(39)
70#define IRQ_EINT12 S3C2410_IRQ(40)
71#define IRQ_EINT13 S3C2410_IRQ(41)
72#define IRQ_EINT14 S3C2410_IRQ(42)
73#define IRQ_EINT15 S3C2410_IRQ(43)
74#define IRQ_EINT16 S3C2410_IRQ(44)
75#define IRQ_EINT17 S3C2410_IRQ(45)
76#define IRQ_EINT18 S3C2410_IRQ(46)
77#define IRQ_EINT19 S3C2410_IRQ(47)
78#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
79#define IRQ_EINT21 S3C2410_IRQ(49)
80#define IRQ_EINT22 S3C2410_IRQ(50)
81#define IRQ_EINT23 S3C2410_IRQ(51)
82
83#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
85
86#define IRQ_LCD_FIFO S3C2410_IRQ(52)
87#define IRQ_LCD_FRAME S3C2410_IRQ(53)
88
89/* IRQs for the interal UARTs, and ADC
90 * these need to be ordered in number of appearance in the
91 * SUBSRC mask register
92*/
93
94#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54)
95
96#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */
97#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
98#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
99
100#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */
101#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
102#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
103
104#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */
105#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
106#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
107
108#define IRQ_TC S3C2410_IRQSUB(9)
109#define IRQ_ADC S3C2410_IRQSUB(10)
110
111/* extra irqs for s3c2412 */
112
113#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
114
115#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
116#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
117
118
119#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
120#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
121#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
122#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
123#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
124
125#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
126#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
127#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
128#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
129#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
130#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
131#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
132#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
133#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
134#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
135#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
136
137
138/* extra irqs for s3c2440 */
139
140#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
141#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
142#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
143#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
144
145/* irqs for s3c2443 */
146
147#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
148#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
149#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
150#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
151#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
152
153#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
154
155#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0
156#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC
157
158#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
159#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
160#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
161#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
162
163#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
164#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
165#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
166#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
167#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
168#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
169
170/* UART3 */
171#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
172#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
173#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
174
175#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
176#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
177
178#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
179#define NR_IRQS (IRQ_S3C2443_AC97+1)
180#else
181#define NR_IRQS (IRQ_S3C2440_AC97+1)
182#endif
183
184/* compatibility define. */
185#define IRQ_UART3 IRQ_S3C2443_UART3
186#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
187#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
188#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
189
190#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
191#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
192
193#ifdef CONFIG_CPU_S3C2440
194#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
195#else
196#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
197#endif
198
199/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
200#define FIQ_START IRQ_EINT0
201
202#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h b/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
new file mode 100644
index 000000000000..d8a7672519b6
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
@@ -0,0 +1,28 @@
1/* arch/arm/mach-s3c2410/include/mach/leds-gpio.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX - LEDs GPIO connector
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_LEDSGPIO_H
15#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h"
16
17#define S3C24XX_LEDF_ACTLOW (1<<0) /* LED is on when GPIO low */
18#define S3C24XX_LEDF_TRISTATE (1<<1) /* tristate to turn off */
19
20struct s3c24xx_led_platdata {
21 unsigned int gpio;
22 unsigned int flags;
23
24 char *name;
25 char *def_trigger;
26};
27
28#endif /* __ASM_ARCH_LEDSGPIO_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
new file mode 100644
index 000000000000..78ae807f1281
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -0,0 +1,165 @@
1/* arch/arm/mach-s3c2410/include/mach/map.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H
15
16#include <plat/map-base.h>
17
18/*
19 * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x4000)
23
24#include <plat/map-s3c.h>
25
26/*
27 * interrupt controller is the first thing we put in, to make
28 * the assembly code for the irq detection easier
29 */
30#define S3C2410_PA_IRQ (0x4A000000)
31#define S3C24XX_SZ_IRQ SZ_1M
32
33/* memory controller registers */
34#define S3C2410_PA_MEMCTRL (0x48000000)
35#define S3C24XX_SZ_MEMCTRL SZ_1M
36
37/* UARTs */
38#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
39
40/* Timers */
41#define S3C2410_PA_TIMER (0x51000000)
42#define S3C24XX_SZ_TIMER SZ_1M
43
44/* Clock and Power management */
45#define S3C24XX_SZ_CLKPWR SZ_1M
46
47/* USB Device port */
48#define S3C2410_PA_USBDEV (0x52000000)
49#define S3C24XX_SZ_USBDEV SZ_1M
50
51/* Watchdog */
52#define S3C2410_PA_WATCHDOG (0x53000000)
53#define S3C24XX_SZ_WATCHDOG SZ_1M
54
55/* Standard size definitions for peripheral blocks. */
56
57#define S3C24XX_SZ_UART SZ_1M
58#define S3C24XX_SZ_IIS SZ_1M
59#define S3C24XX_SZ_ADC SZ_1M
60#define S3C24XX_SZ_SPI SZ_1M
61#define S3C24XX_SZ_SDI SZ_1M
62#define S3C24XX_SZ_NAND SZ_1M
63#define S3C24XX_SZ_GPIO SZ_1M
64
65/* USB host controller */
66#define S3C2410_PA_USBHOST (0x49000000)
67
68/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */
69#define S3C2416_PA_HSUDC (0x49800000)
70#define S3C2416_SZ_HSUDC (SZ_4K)
71
72/* DMA controller */
73#define S3C2410_PA_DMA (0x4B000000)
74#define S3C24XX_SZ_DMA SZ_1M
75
76/* Clock and Power management */
77#define S3C2410_PA_CLKPWR (0x4C000000)
78
79/* LCD controller */
80#define S3C2410_PA_LCD (0x4D000000)
81#define S3C24XX_SZ_LCD SZ_1M
82
83/* NAND flash controller */
84#define S3C2410_PA_NAND (0x4E000000)
85
86/* IIC hardware controller */
87#define S3C2410_PA_IIC (0x54000000)
88
89/* IIS controller */
90#define S3C2410_PA_IIS (0x55000000)
91
92/* RTC */
93#define S3C2410_PA_RTC (0x57000000)
94#define S3C24XX_SZ_RTC SZ_1M
95
96/* ADC */
97#define S3C2410_PA_ADC (0x58000000)
98
99/* SPI */
100#define S3C2410_PA_SPI (0x59000000)
101
102/* SDI */
103#define S3C2410_PA_SDI (0x5A000000)
104
105/* CAMIF */
106#define S3C2440_PA_CAMIF (0x4F000000)
107#define S3C2440_SZ_CAMIF SZ_1M
108
109/* AC97 */
110
111#define S3C2440_PA_AC97 (0x5B000000)
112#define S3C2440_SZ_AC97 SZ_1M
113
114/* S3C2443/S3C2416 High-speed SD/MMC */
115#define S3C2443_PA_HSMMC (0x4A800000)
116#define S3C2416_PA_HSMMC0 (0x4AC00000)
117
118#define S3C2443_PA_FB (0x4C800000)
119
120/* S3C2412 memory and IO controls */
121#define S3C2412_PA_SSMC (0x4F000000)
122
123#define S3C2412_PA_EBI (0x48800000)
124
125/* physical addresses of all the chip-select areas */
126
127#define S3C2410_CS0 (0x00000000)
128#define S3C2410_CS1 (0x08000000)
129#define S3C2410_CS2 (0x10000000)
130#define S3C2410_CS3 (0x18000000)
131#define S3C2410_CS4 (0x20000000)
132#define S3C2410_CS5 (0x28000000)
133#define S3C2410_CS6 (0x30000000)
134#define S3C2410_CS7 (0x38000000)
135
136#define S3C2410_SDRAM_PA (S3C2410_CS6)
137
138/* Use a single interface for common resources between S3C24XX cpus */
139
140#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
141#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
142#define S3C24XX_PA_DMA S3C2410_PA_DMA
143#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
144#define S3C24XX_PA_LCD S3C2410_PA_LCD
145#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
146#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
147#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
148#define S3C24XX_PA_IIS S3C2410_PA_IIS
149#define S3C24XX_PA_RTC S3C2410_PA_RTC
150#define S3C24XX_PA_ADC S3C2410_PA_ADC
151#define S3C24XX_PA_SPI S3C2410_PA_SPI
152#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1)
153#define S3C24XX_PA_SDI S3C2410_PA_SDI
154#define S3C24XX_PA_NAND S3C2410_PA_NAND
155
156#define S3C_PA_FB S3C2443_PA_FB
157#define S3C_PA_IIC S3C2410_PA_IIC
158#define S3C_PA_UART S3C24XX_PA_UART
159#define S3C_PA_USBHOST S3C2410_PA_USBHOST
160#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
161#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
162#define S3C_PA_WDT S3C2410_PA_WATCHDOG
163#define S3C_PA_NAND S3C24XX_PA_NAND
164
165#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
new file mode 100644
index 000000000000..e9e36b0abbac
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
@@ -0,0 +1,30 @@
1/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
2 *
3 * Copyright 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * OSIRIS - CPLD control constants
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_OSIRISCPLD_H
15#define __ASM_ARCH_OSIRISCPLD_H
16
17/* CTRL0 - NAND WP control */
18
19#define OSIRIS_CTRL0_NANDSEL (0x3)
20#define OSIRIS_CTRL0_BOOT_INT (1<<3)
21#define OSIRIS_CTRL0_PCMCIA (1<<4)
22#define OSIRIS_CTRL0_FIX8 (1<<5)
23#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6)
24#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7)
25
26#define OSIRIS_CTRL1_FIX8 (1<<0)
27
28#define OSIRIS_ID_REVMASK (0x7)
29
30#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h b/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
new file mode 100644
index 000000000000..17380f848428
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
@@ -0,0 +1,42 @@
1/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
2 *
3 * Copyright 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * OSIRIS - Memory map definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* needs arch/map.h including with this */
15
16#ifndef __ASM_ARCH_OSIRISMAP_H
17#define __ASM_ARCH_OSIRISMAP_H
18
19/* start peripherals off after the S3C2410 */
20
21#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000))
22
23#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26))
24
25/* we put the CPLD registers next, to get them out of the way */
26
27#define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000)
28#define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD)
29
30#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000)
31#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23))
32
33#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000)
34#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23))
35
36#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000)
37#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
38
39#define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000)
40#define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23))
41
42#endif /* __ASM_ARCH_OSIRISMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/otom-map.h b/arch/arm/mach-s3c24xx/include/mach/otom-map.h
new file mode 100644
index 000000000000..f9277a52c145
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/otom-map.h
@@ -0,0 +1,30 @@
1/* arch/arm/mach-s3c2410/include/mach/otom-map.h
2 *
3 * (c) 2005 Guillaume GOURAT / NexVision
4 * guillaume.gourat@nexvision.fr
5 *
6 * NexVision OTOM board memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x01300000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space.
18 */
19
20#ifndef __ASM_ARCH_OTOMMAP_H
21#define __ASM_ARCH_OTOMMAP_H
22
23#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */
24#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */
25
26/* physical offset addresses for the peripherals */
27
28#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */
29
30#endif /* __ASM_ARCH_OTOMMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/pm-core.h b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
new file mode 100644
index 000000000000..2eef7e6f7675
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
@@ -0,0 +1,67 @@
1/* linux/arch/arm/mach-s3c2410/include/pm-core.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14static inline void s3c_pm_debug_init_uart(void)
15{
16 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
17
18 /* re-start uart clocks */
19 tmp |= S3C2410_CLKCON_UART0;
20 tmp |= S3C2410_CLKCON_UART1;
21 tmp |= S3C2410_CLKCON_UART2;
22
23 __raw_writel(tmp, S3C2410_CLKCON);
24 udelay(10);
25}
26
27static inline void s3c_pm_arch_prepare_irqs(void)
28{
29 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
30 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
31
32 /* ack any outstanding external interrupts before we go to sleep */
33
34 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
35 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
36 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
37
38}
39
40static inline void s3c_pm_arch_stop_clocks(void)
41{
42 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
43}
44
45static void s3c_pm_show_resume_irqs(int start, unsigned long which,
46 unsigned long mask);
47
48static inline void s3c_pm_arch_show_resume_irqs(void)
49{
50 S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
51 __raw_readl(S3C2410_SRCPND),
52 __raw_readl(S3C2410_EINTPEND));
53
54 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
55 s3c_irqwake_intmask);
56
57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
58 s3c_irqwake_eintmask);
59}
60
61static inline void s3c_pm_arch_update_uart(void __iomem *regs,
62 struct pm_uart_save *save)
63{
64}
65
66static inline void s3c_pm_restored_gpios(void) { }
67static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
new file mode 100644
index 000000000000..3415b60082d7
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
@@ -0,0 +1,166 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 clock register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_CLOCK
14#define __ASM_ARM_REGS_CLOCK
15
16#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
19
20#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
21#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
22#define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
23#define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
24#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
25#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
26
27#define S3C2410_CLKCON_IDLE (1<<2)
28#define S3C2410_CLKCON_POWER (1<<3)
29#define S3C2410_CLKCON_NAND (1<<4)
30#define S3C2410_CLKCON_LCDC (1<<5)
31#define S3C2410_CLKCON_USBH (1<<6)
32#define S3C2410_CLKCON_USBD (1<<7)
33#define S3C2410_CLKCON_PWMT (1<<8)
34#define S3C2410_CLKCON_SDI (1<<9)
35#define S3C2410_CLKCON_UART0 (1<<10)
36#define S3C2410_CLKCON_UART1 (1<<11)
37#define S3C2410_CLKCON_UART2 (1<<12)
38#define S3C2410_CLKCON_GPIO (1<<13)
39#define S3C2410_CLKCON_RTC (1<<14)
40#define S3C2410_CLKCON_ADC (1<<15)
41#define S3C2410_CLKCON_IIC (1<<16)
42#define S3C2410_CLKCON_IIS (1<<17)
43#define S3C2410_CLKCON_SPI (1<<18)
44
45/* DCLKCON register addresses in gpio.h */
46
47#define S3C2410_DCLKCON_DCLK0EN (1<<0)
48#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
49#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
50#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
51#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
52#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
53#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
54
55#define S3C2410_DCLKCON_DCLK1EN (1<<16)
56#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
57#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
58#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
59#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
60#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
61#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
62
63#define S3C2410_CLKDIVN_PDIVN (1<<0)
64#define S3C2410_CLKDIVN_HDIVN (1<<1)
65
66#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
67#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
68#define S3C2410_CLKSLOW_SLOW (1<<4)
69#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
70#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
71
72#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
73
74/* extra registers */
75#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
76
77#define S3C2440_CLKCON_CAMERA (1<<19)
78#define S3C2440_CLKCON_AC97 (1<<20)
79
80#define S3C2440_CLKDIVN_PDIVN (1<<0)
81#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
82#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
83#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
84#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
85#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
86#define S3C2440_CLKDIVN_UCLK (1<<3)
87
88#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
89#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
90#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
91#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
92#define S3C2440_CAMDIVN_DVSEN (1<<12)
93
94#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
95
96#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
97
98#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
99
100#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
101#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
102
103#define S3C2412_PLLCON_OFF (1<<20)
104
105#define S3C2412_CLKDIVN_PDIVN (1<<2)
106#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
107#define S3C2412_CLKDIVN_ARMDIVN (1<<3)
108#define S3C2412_CLKDIVN_DVSEN (1<<4)
109#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
110#define S3C2412_CLKDIVN_USB48DIV (1<<6)
111#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
112#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
113#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
114#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
115#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
116#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
117
118#define S3C2412_CLKCON_WDT (1<<28)
119#define S3C2412_CLKCON_SPI (1<<27)
120#define S3C2412_CLKCON_IIS (1<<26)
121#define S3C2412_CLKCON_IIC (1<<25)
122#define S3C2412_CLKCON_ADC (1<<24)
123#define S3C2412_CLKCON_RTC (1<<23)
124#define S3C2412_CLKCON_GPIO (1<<22)
125#define S3C2412_CLKCON_UART2 (1<<21)
126#define S3C2412_CLKCON_UART1 (1<<20)
127#define S3C2412_CLKCON_UART0 (1<<19)
128#define S3C2412_CLKCON_SDI (1<<18)
129#define S3C2412_CLKCON_PWMT (1<<17)
130#define S3C2412_CLKCON_USBD (1<<16)
131#define S3C2412_CLKCON_CAMCLK (1<<15)
132#define S3C2412_CLKCON_UARTCLK (1<<14)
133/* missing 13 */
134#define S3C2412_CLKCON_USB_HOST48 (1<<12)
135#define S3C2412_CLKCON_USB_DEV48 (1<<11)
136#define S3C2412_CLKCON_HCLKdiv2 (1<<10)
137#define S3C2412_CLKCON_HCLKx2 (1<<9)
138#define S3C2412_CLKCON_SDRAM (1<<8)
139/* missing 7 */
140#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
141#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
142#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
143#define S3C2412_CLKCON_DMA3 (1<<3)
144#define S3C2412_CLKCON_DMA2 (1<<2)
145#define S3C2412_CLKCON_DMA1 (1<<1)
146#define S3C2412_CLKCON_DMA0 (1<<0)
147
148/* clock sourec controls */
149
150#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
151#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
152#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
153#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
154#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
155#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
156#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
157#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
158#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
159#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
160#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
161
162#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
163
164#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
165
166#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h b/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
new file mode 100644
index 000000000000..98fd4a05587c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
@@ -0,0 +1,220 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440/S3C2412 Signal Drive Strength Control
11*/
12
13
14#ifndef __ASM_ARCH_REGS_DSC_H
15#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
16
17#if defined(CONFIG_CPU_S3C2412)
18#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
19#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
20#endif
21
22#if defined(CONFIG_CPU_S3C2416)
23#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0)
24#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4)
25#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8)
26#define S3C2416_DSC3 S3C2410_GPIOREG(0x110)
27
28#define S3C2416_SELECT_DSC0 (0 << 30)
29#define S3C2416_SELECT_DSC1 (1 << 30)
30#define S3C2416_SELECT_DSC2 (2 << 30)
31#define S3C2416_SELECT_DSC3 (3 << 30)
32
33#define S3C2416_DSC_GETSHIFT(x) (x & 30)
34
35#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28)
36#define S3C2416_DSC0_CF_5mA (0 << 28)
37#define S3C2416_DSC0_CF_10mA (1 << 28)
38#define S3C2416_DSC0_CF_15mA (2 << 28)
39#define S3C2416_DSC0_CF_21mA (3 << 28)
40#define S3C2416_DSC0_CF_MASK (3 << 28)
41
42#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26)
43#define S3C2416_DSC0_nRBE_5mA (0 << 26)
44#define S3C2416_DSC0_nRBE_10mA (1 << 26)
45#define S3C2416_DSC0_nRBE_15mA (2 << 26)
46#define S3C2416_DSC0_nRBE_21mA (3 << 26)
47#define S3C2416_DSC0_nRBE_MASK (3 << 26)
48
49#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24)
50#define S3C2416_DSC0_nROE_5mA (0 << 24)
51#define S3C2416_DSC0_nROE_10mA (1 << 24)
52#define S3C2416_DSC0_nROE_15mA (2 << 24)
53#define S3C2416_DSC0_nROE_21mA (3 << 24)
54#define S3C2416_DSC0_nROE_MASK (3 << 24)
55
56#endif
57
58#if defined(CONFIG_CPU_S3C244X)
59
60#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
61#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
62
63#define S3C2440_SELECT_DSC0 (0)
64#define S3C2440_SELECT_DSC1 (1<<31)
65
66#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
67
68#define S3C2440_DSC0_DISABLE (1<<31)
69
70#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8)
71#define S3C2440_DSC0_ADDR_12mA (0<<8)
72#define S3C2440_DSC0_ADDR_10mA (1<<8)
73#define S3C2440_DSC0_ADDR_8mA (2<<8)
74#define S3C2440_DSC0_ADDR_6mA (3<<8)
75#define S3C2440_DSC0_ADDR_MASK (3<<8)
76
77/* D24..D31 */
78#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6)
79#define S3C2440_DSC0_DATA3_12mA (0<<6)
80#define S3C2440_DSC0_DATA3_10mA (1<<6)
81#define S3C2440_DSC0_DATA3_8mA (2<<6)
82#define S3C2440_DSC0_DATA3_6mA (3<<6)
83#define S3C2440_DSC0_DATA3_MASK (3<<6)
84
85/* D16..D23 */
86#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4)
87#define S3C2440_DSC0_DATA2_12mA (0<<4)
88#define S3C2440_DSC0_DATA2_10mA (1<<4)
89#define S3C2440_DSC0_DATA2_8mA (2<<4)
90#define S3C2440_DSC0_DATA2_6mA (3<<4)
91#define S3C2440_DSC0_DATA2_MASK (3<<4)
92
93/* D8..D15 */
94#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2)
95#define S3C2440_DSC0_DATA1_12mA (0<<2)
96#define S3C2440_DSC0_DATA1_10mA (1<<2)
97#define S3C2440_DSC0_DATA1_8mA (2<<2)
98#define S3C2440_DSC0_DATA1_6mA (3<<2)
99#define S3C2440_DSC0_DATA1_MASK (3<<2)
100
101/* D0..D7 */
102#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0)
103#define S3C2440_DSC0_DATA0_12mA (0<<0)
104#define S3C2440_DSC0_DATA0_10mA (1<<0)
105#define S3C2440_DSC0_DATA0_8mA (2<<0)
106#define S3C2440_DSC0_DATA0_6mA (3<<0)
107#define S3C2440_DSC0_DATA0_MASK (3<<0)
108
109#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28)
110#define S3C2440_DSC1_SCK1_12mA (0<<28)
111#define S3C2440_DSC1_SCK1_10mA (1<<28)
112#define S3C2440_DSC1_SCK1_8mA (2<<28)
113#define S3C2440_DSC1_SCK1_6mA (3<<28)
114#define S3C2440_DSC1_SCK1_MASK (3<<28)
115
116#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26)
117#define S3C2440_DSC1_SCK0_12mA (0<<26)
118#define S3C2440_DSC1_SCK0_10mA (1<<26)
119#define S3C2440_DSC1_SCK0_8mA (2<<26)
120#define S3C2440_DSC1_SCK0_6mA (3<<26)
121#define S3C2440_DSC1_SCK0_MASK (3<<26)
122
123#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24)
124#define S3C2440_DSC1_SCKE_10mA (0<<24)
125#define S3C2440_DSC1_SCKE_8mA (1<<24)
126#define S3C2440_DSC1_SCKE_6mA (2<<24)
127#define S3C2440_DSC1_SCKE_4mA (3<<24)
128#define S3C2440_DSC1_SCKE_MASK (3<<24)
129
130/* SDRAM nRAS/nCAS */
131#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22)
132#define S3C2440_DSC1_SDR_10mA (0<<22)
133#define S3C2440_DSC1_SDR_8mA (1<<22)
134#define S3C2440_DSC1_SDR_6mA (2<<22)
135#define S3C2440_DSC1_SDR_4mA (3<<22)
136#define S3C2440_DSC1_SDR_MASK (3<<22)
137
138/* NAND Flash Controller */
139#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20)
140#define S3C2440_DSC1_NFC_10mA (0<<20)
141#define S3C2440_DSC1_NFC_8mA (1<<20)
142#define S3C2440_DSC1_NFC_6mA (2<<20)
143#define S3C2440_DSC1_NFC_4mA (3<<20)
144#define S3C2440_DSC1_NFC_MASK (3<<20)
145
146/* nBE[0..3] */
147#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18)
148#define S3C2440_DSC1_nBE_10mA (0<<18)
149#define S3C2440_DSC1_nBE_8mA (1<<18)
150#define S3C2440_DSC1_nBE_6mA (2<<18)
151#define S3C2440_DSC1_nBE_4mA (3<<18)
152#define S3C2440_DSC1_nBE_MASK (3<<18)
153
154#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16)
155#define S3C2440_DSC1_WOE_10mA (0<<16)
156#define S3C2440_DSC1_WOE_8mA (1<<16)
157#define S3C2440_DSC1_WOE_6mA (2<<16)
158#define S3C2440_DSC1_WOE_4mA (3<<16)
159#define S3C2440_DSC1_WOE_MASK (3<<16)
160
161#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14)
162#define S3C2440_DSC1_CS7_10mA (0<<14)
163#define S3C2440_DSC1_CS7_8mA (1<<14)
164#define S3C2440_DSC1_CS7_6mA (2<<14)
165#define S3C2440_DSC1_CS7_4mA (3<<14)
166#define S3C2440_DSC1_CS7_MASK (3<<14)
167
168#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12)
169#define S3C2440_DSC1_CS6_10mA (0<<12)
170#define S3C2440_DSC1_CS6_8mA (1<<12)
171#define S3C2440_DSC1_CS6_6mA (2<<12)
172#define S3C2440_DSC1_CS6_4mA (3<<12)
173#define S3C2440_DSC1_CS6_MASK (3<<12)
174
175#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10)
176#define S3C2440_DSC1_CS5_10mA (0<<10)
177#define S3C2440_DSC1_CS5_8mA (1<<10)
178#define S3C2440_DSC1_CS5_6mA (2<<10)
179#define S3C2440_DSC1_CS5_4mA (3<<10)
180#define S3C2440_DSC1_CS5_MASK (3<<10)
181
182#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8)
183#define S3C2440_DSC1_CS4_10mA (0<<8)
184#define S3C2440_DSC1_CS4_8mA (1<<8)
185#define S3C2440_DSC1_CS4_6mA (2<<8)
186#define S3C2440_DSC1_CS4_4mA (3<<8)
187#define S3C2440_DSC1_CS4_MASK (3<<8)
188
189#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6)
190#define S3C2440_DSC1_CS3_10mA (0<<6)
191#define S3C2440_DSC1_CS3_8mA (1<<6)
192#define S3C2440_DSC1_CS3_6mA (2<<6)
193#define S3C2440_DSC1_CS3_4mA (3<<6)
194#define S3C2440_DSC1_CS3_MASK (3<<6)
195
196#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4)
197#define S3C2440_DSC1_CS2_10mA (0<<4)
198#define S3C2440_DSC1_CS2_8mA (1<<4)
199#define S3C2440_DSC1_CS2_6mA (2<<4)
200#define S3C2440_DSC1_CS2_4mA (3<<4)
201#define S3C2440_DSC1_CS2_MASK (3<<4)
202
203#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2)
204#define S3C2440_DSC1_CS1_10mA (0<<2)
205#define S3C2440_DSC1_CS1_8mA (1<<2)
206#define S3C2440_DSC1_CS1_6mA (2<<2)
207#define S3C2440_DSC1_CS1_4mA (3<<2)
208#define S3C2440_DSC1_CS1_MASK (3<<2)
209
210#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0)
211#define S3C2440_DSC1_CS0_10mA (0<<0)
212#define S3C2440_DSC1_CS0_8mA (1<<0)
213#define S3C2440_DSC1_CS0_6mA (2<<0)
214#define S3C2440_DSC1_CS0_4mA (3<<0)
215#define S3C2440_DSC1_CS0_MASK (3<<0)
216
217#endif /* CONFIG_CPU_S3C2440 */
218
219#endif /* __ASM_ARCH_REGS_DSC_H */
220
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..cac1ad6b582c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -0,0 +1,602 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 GPIO register definitions
11*/
12
13
14#ifndef __ASM_ARCH_REGS_GPIO_H
15#define __ASM_ARCH_REGS_GPIO_H
16
17#include <mach/gpio-nrs.h>
18
19#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
20
21/* general configuration options */
22
23#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
24#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */
25#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
26#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
27#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */
28#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
29
30/* register address for the GPIO registers.
31 * S3C24XX_GPIOREG2 is for the second set of registers in the
32 * GPIO which move between s3c2410 and s3c2412 type systems */
33
34#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
35#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
36
37
38/* configure GPIO ports A..G */
39
40/* port A - S3C2410: 22bits, zero in bit X makes pin X output
41 * 1 makes port special function, this is default
42*/
43#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
44#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
45
46#define S3C2410_GPA0_ADDR0 (1<<0)
47#define S3C2410_GPA1_ADDR16 (1<<1)
48#define S3C2410_GPA2_ADDR17 (1<<2)
49#define S3C2410_GPA3_ADDR18 (1<<3)
50#define S3C2410_GPA4_ADDR19 (1<<4)
51#define S3C2410_GPA5_ADDR20 (1<<5)
52#define S3C2410_GPA6_ADDR21 (1<<6)
53#define S3C2410_GPA7_ADDR22 (1<<7)
54#define S3C2410_GPA8_ADDR23 (1<<8)
55#define S3C2410_GPA9_ADDR24 (1<<9)
56#define S3C2410_GPA10_ADDR25 (1<<10)
57#define S3C2410_GPA11_ADDR26 (1<<11)
58#define S3C2410_GPA12_nGCS1 (1<<12)
59#define S3C2410_GPA13_nGCS2 (1<<13)
60#define S3C2410_GPA14_nGCS3 (1<<14)
61#define S3C2410_GPA15_nGCS4 (1<<15)
62#define S3C2410_GPA16_nGCS5 (1<<16)
63#define S3C2410_GPA17_CLE (1<<17)
64#define S3C2410_GPA18_ALE (1<<18)
65#define S3C2410_GPA19_nFWE (1<<19)
66#define S3C2410_GPA20_nFRE (1<<20)
67#define S3C2410_GPA21_nRSTOUT (1<<21)
68#define S3C2410_GPA22_nFCE (1<<22)
69
70/* 0x08 and 0x0c are reserved on S3C2410 */
71
72/* S3C2410:
73 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
74 * 00 = input, 01 = output, 10=special function, 11=reserved
75
76 * bit 0,1 = pin 0, 2,3= pin 1...
77 *
78 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
79*/
80
81#define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
82#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
83#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
84
85/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
86
87#define S3C2410_GPB0_TOUT0 (0x02 << 0)
88
89#define S3C2410_GPB1_TOUT1 (0x02 << 2)
90
91#define S3C2410_GPB2_TOUT2 (0x02 << 4)
92
93#define S3C2410_GPB3_TOUT3 (0x02 << 6)
94
95#define S3C2410_GPB4_TCLK0 (0x02 << 8)
96#define S3C2410_GPB4_MASK (0x03 << 8)
97
98#define S3C2410_GPB5_nXBACK (0x02 << 10)
99#define S3C2443_GPB5_XBACK (0x03 << 10)
100
101#define S3C2410_GPB6_nXBREQ (0x02 << 12)
102#define S3C2443_GPB6_XBREQ (0x03 << 12)
103
104#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
105#define S3C2443_GPB7_XDACK1 (0x03 << 14)
106
107#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
108
109#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
110#define S3C2443_GPB9_XDACK0 (0x03 << 18)
111
112#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
113#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
114
115#define S3C2410_GPB_PUPDIS(x) (1<<(x))
116
117/* Port C consits of 16 GPIO/Special function
118 *
119 * almost identical setup to port b, but the special functions are mostly
120 * to do with the video system's sync/etc.
121*/
122
123#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
124#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
125#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
126#define S3C2410_GPC0_LEND (0x02 << 0)
127#define S3C2410_GPC1_VCLK (0x02 << 2)
128#define S3C2410_GPC2_VLINE (0x02 << 4)
129#define S3C2410_GPC3_VFRAME (0x02 << 6)
130#define S3C2410_GPC4_VM (0x02 << 8)
131#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
132#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
133#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
134#define S3C2410_GPC8_VD0 (0x02 << 16)
135#define S3C2410_GPC9_VD1 (0x02 << 18)
136#define S3C2410_GPC10_VD2 (0x02 << 20)
137#define S3C2410_GPC11_VD3 (0x02 << 22)
138#define S3C2410_GPC12_VD4 (0x02 << 24)
139#define S3C2410_GPC13_VD5 (0x02 << 26)
140#define S3C2410_GPC14_VD6 (0x02 << 28)
141#define S3C2410_GPC15_VD7 (0x02 << 30)
142#define S3C2410_GPC_PUPDIS(x) (1<<(x))
143
144/*
145 * S3C2410: Port D consists of 16 GPIO/Special function
146 *
147 * almost identical setup to port b, but the special functions are mostly
148 * to do with the video system's data.
149 *
150 * almost identical setup to port c
151*/
152
153#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
154#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
155#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
156
157#define S3C2410_GPD0_VD8 (0x02 << 0)
158#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
159
160#define S3C2410_GPD1_VD9 (0x02 << 2)
161#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
162
163#define S3C2410_GPD2_VD10 (0x02 << 4)
164
165#define S3C2410_GPD3_VD11 (0x02 << 6)
166
167#define S3C2410_GPD4_VD12 (0x02 << 8)
168
169#define S3C2410_GPD5_VD13 (0x02 << 10)
170
171#define S3C2410_GPD6_VD14 (0x02 << 12)
172
173#define S3C2410_GPD7_VD15 (0x02 << 14)
174
175#define S3C2410_GPD8_VD16 (0x02 << 16)
176#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
177
178#define S3C2410_GPD9_VD17 (0x02 << 18)
179#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
180
181#define S3C2410_GPD10_VD18 (0x02 << 20)
182#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
183
184#define S3C2410_GPD11_VD19 (0x02 << 22)
185
186#define S3C2410_GPD12_VD20 (0x02 << 24)
187
188#define S3C2410_GPD13_VD21 (0x02 << 26)
189
190#define S3C2410_GPD14_VD22 (0x02 << 28)
191#define S3C2410_GPD14_nSS1 (0x03 << 28)
192
193#define S3C2410_GPD15_VD23 (0x02 << 30)
194#define S3C2410_GPD15_nSS0 (0x03 << 30)
195
196#define S3C2410_GPD_PUPDIS(x) (1<<(x))
197
198/* S3C2410:
199 * Port E consists of 16 GPIO/Special function
200 *
201 * again, the same as port B, but dealing with I2S, SDI, and
202 * more miscellaneous functions
203 *
204 * GPIO / interrupt inputs
205*/
206
207#define S3C2410_GPECON S3C2410_GPIOREG(0x40)
208#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
209#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
210
211#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
212#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
213#define S3C2410_GPE0_MASK (0x03 << 0)
214
215#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
216#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
217#define S3C2410_GPE1_MASK (0x03 << 2)
218
219#define S3C2410_GPE2_CDCLK (0x02 << 4)
220#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
221
222#define S3C2410_GPE3_I2SSDI (0x02 << 6)
223#define S3C2443_GPE3_AC_SDI (0x03 << 6)
224#define S3C2410_GPE3_nSS0 (0x03 << 6)
225#define S3C2410_GPE3_MASK (0x03 << 6)
226
227#define S3C2410_GPE4_I2SSDO (0x02 << 8)
228#define S3C2443_GPE4_AC_SDO (0x03 << 8)
229#define S3C2410_GPE4_I2SSDI (0x03 << 8)
230#define S3C2410_GPE4_MASK (0x03 << 8)
231
232#define S3C2410_GPE5_SDCLK (0x02 << 10)
233#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
234#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
235
236#define S3C2410_GPE6_SDCMD (0x02 << 12)
237#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
238#define S3C2443_GPE6_AC_SDI (0x03 << 12)
239
240#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
241#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
242#define S3C2443_GPE7_AC_SDO (0x03 << 14)
243
244#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
245#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
246#define S3C2443_GPE8_AC_SYNC (0x03 << 16)
247
248#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
249#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
250#define S3C2443_GPE9_AC_nRESET (0x03 << 18)
251
252#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
253#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
254
255#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
256
257#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
258
259#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
260
261#define S3C2410_GPE14_IICSCL (0x02 << 28)
262#define S3C2410_GPE14_MASK (0x03 << 28)
263
264#define S3C2410_GPE15_IICSDA (0x02 << 30)
265#define S3C2410_GPE15_MASK (0x03 << 30)
266
267#define S3C2440_GPE0_ACSYNC (0x03 << 0)
268#define S3C2440_GPE1_ACBITCLK (0x03 << 2)
269#define S3C2440_GPE2_ACRESET (0x03 << 4)
270#define S3C2440_GPE3_ACIN (0x03 << 6)
271#define S3C2440_GPE4_ACOUT (0x03 << 8)
272
273#define S3C2410_GPE_PUPDIS(x) (1<<(x))
274
275/* S3C2410:
276 * Port F consists of 8 GPIO/Special function
277 *
278 * GPIO / interrupt inputs
279 *
280 * GPFCON has 2 bits for each of the input pins on port F
281 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
282 *
283 * pull up works like all other ports.
284 *
285 * GPIO/serial/misc pins
286*/
287
288#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
289#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
290#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
291
292#define S3C2410_GPF0_EINT0 (0x02 << 0)
293#define S3C2410_GPF1_EINT1 (0x02 << 2)
294#define S3C2410_GPF2_EINT2 (0x02 << 4)
295#define S3C2410_GPF3_EINT3 (0x02 << 6)
296#define S3C2410_GPF4_EINT4 (0x02 << 8)
297#define S3C2410_GPF5_EINT5 (0x02 << 10)
298#define S3C2410_GPF6_EINT6 (0x02 << 12)
299#define S3C2410_GPF7_EINT7 (0x02 << 14)
300#define S3C2410_GPF_PUPDIS(x) (1<<(x))
301
302/* S3C2410:
303 * Port G consists of 8 GPIO/IRQ/Special function
304 *
305 * GPGCON has 2 bits for each of the input pins on port F
306 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
307 *
308 * pull up works like all other ports.
309*/
310
311#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
312#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
313#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
314
315#define S3C2410_GPG0_EINT8 (0x02 << 0)
316
317#define S3C2410_GPG1_EINT9 (0x02 << 2)
318
319#define S3C2410_GPG2_EINT10 (0x02 << 4)
320#define S3C2410_GPG2_nSS0 (0x03 << 4)
321
322#define S3C2410_GPG3_EINT11 (0x02 << 6)
323#define S3C2410_GPG3_nSS1 (0x03 << 6)
324
325#define S3C2410_GPG4_EINT12 (0x02 << 8)
326#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
327#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
328
329#define S3C2410_GPG5_EINT13 (0x02 << 10)
330#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
331
332#define S3C2410_GPG6_EINT14 (0x02 << 12)
333#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
334
335#define S3C2410_GPG7_EINT15 (0x02 << 14)
336#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
337
338#define S3C2410_GPG8_EINT16 (0x02 << 16)
339
340#define S3C2410_GPG9_EINT17 (0x02 << 18)
341
342#define S3C2410_GPG10_EINT18 (0x02 << 20)
343
344#define S3C2410_GPG11_EINT19 (0x02 << 22)
345#define S3C2410_GPG11_TCLK1 (0x03 << 22)
346#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
347
348#define S3C2410_GPG12_EINT20 (0x02 << 24)
349#define S3C2410_GPG12_XMON (0x03 << 24)
350#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
351#define S3C2443_GPG12_nINPACK (0x03 << 24)
352
353#define S3C2410_GPG13_EINT21 (0x02 << 26)
354#define S3C2410_GPG13_nXPON (0x03 << 26)
355#define S3C2443_GPG13_CF_nREG (0x03 << 26)
356
357#define S3C2410_GPG14_EINT22 (0x02 << 28)
358#define S3C2410_GPG14_YMON (0x03 << 28)
359#define S3C2443_GPG14_CF_RESET (0x03 << 28)
360
361#define S3C2410_GPG15_EINT23 (0x02 << 30)
362#define S3C2410_GPG15_nYPON (0x03 << 30)
363#define S3C2443_GPG15_CF_PWR (0x03 << 30)
364
365#define S3C2410_GPG_PUPDIS(x) (1<<(x))
366
367/* Port H consists of11 GPIO/serial/Misc pins
368 *
369 * GPGCON has 2 bits for each of the input pins on port F
370 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
371 *
372 * pull up works like all other ports.
373*/
374
375#define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
376#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
377#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
378
379#define S3C2410_GPH0_nCTS0 (0x02 << 0)
380#define S3C2416_GPH0_TXD0 (0x02 << 0)
381
382#define S3C2410_GPH1_nRTS0 (0x02 << 2)
383#define S3C2416_GPH1_RXD0 (0x02 << 2)
384
385#define S3C2410_GPH2_TXD0 (0x02 << 4)
386#define S3C2416_GPH2_TXD1 (0x02 << 4)
387
388#define S3C2410_GPH3_RXD0 (0x02 << 6)
389#define S3C2416_GPH3_RXD1 (0x02 << 6)
390
391#define S3C2410_GPH4_TXD1 (0x02 << 8)
392#define S3C2416_GPH4_TXD2 (0x02 << 8)
393
394#define S3C2410_GPH5_RXD1 (0x02 << 10)
395#define S3C2416_GPH5_RXD2 (0x02 << 10)
396
397#define S3C2410_GPH6_TXD2 (0x02 << 12)
398#define S3C2416_GPH6_TXD3 (0x02 << 12)
399#define S3C2410_GPH6_nRTS1 (0x03 << 12)
400#define S3C2416_GPH6_nRTS2 (0x03 << 12)
401
402#define S3C2410_GPH7_RXD2 (0x02 << 14)
403#define S3C2416_GPH7_RXD3 (0x02 << 14)
404#define S3C2410_GPH7_nCTS1 (0x03 << 14)
405#define S3C2416_GPH7_nCTS2 (0x03 << 14)
406
407#define S3C2410_GPH8_UCLK (0x02 << 16)
408#define S3C2416_GPH8_nCTS0 (0x02 << 16)
409
410#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
411#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
412#define S3C2416_GPH9_nRTS0 (0x02 << 18)
413
414#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
415#define S3C2416_GPH10_nCTS1 (0x02 << 20)
416
417#define S3C2416_GPH11_nRTS1 (0x02 << 22)
418
419#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
420
421#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
422
423#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
424
425/* The S3C2412 and S3C2413 move the GPJ register set to after
426 * GPH, which means all registers after 0x80 are now offset by 0x10
427 * for the 2412/2413 from the 2410/2440/2442
428*/
429
430/* S3C2443 and above */
431#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0)
432#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)
433#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8)
434
435#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0)
436#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)
437#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8)
438
439#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0)
440#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)
441#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8)
442
443#define S3C2443_GPMCON S3C2410_GPIOREG(0x100)
444#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104)
445#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
446
447/* miscellaneous control */
448#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
449#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
450
451#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
452
453/* see clock.h for dclk definitions */
454
455/* pullup control on databus */
456#define S3C2410_MISCCR_SPUCR_HEN (0<<0)
457#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
458#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
459#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
460
461#define S3C2410_MISCCR_USBDEV (0<<3)
462#define S3C2410_MISCCR_USBHOST (1<<3)
463
464#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
465#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
466#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
467#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
468#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
469#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
470#define S3C2410_MISCCR_CLK0_MASK (7<<4)
471
472#define S3C2412_MISCCR_CLK0_RTC (2<<4)
473
474#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
475#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
476#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
477#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
478#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
479#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
480#define S3C2410_MISCCR_CLK1_MASK (7<<8)
481
482#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
483
484#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
485#define S3C2416_MISCCR_SEL_SUSPND (1<<12)
486#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
487
488#define S3C2410_MISCCR_nRSTCON (1<<16)
489
490#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
491#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
492#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
493#define S3C2410_MISCCR_SDSLEEP (7<<17)
494
495#define S3C2416_MISCCR_FLT_I2C (1<<24)
496#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
497
498/* external interrupt control... */
499/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
500 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
501 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
502 *
503 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
504 *
505 * Samsung datasheet p9-25
506*/
507#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
508#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
509#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
510
511#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
512#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
513#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
514
515/* interrupt filtering conrrol for EINT16..EINT23 */
516#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
517#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
518#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
519#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
520
521#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
522#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
523#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
524#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
525
526/* values for interrupt filtering */
527#define S3C2410_EINTFLT_PCLK (0x00)
528#define S3C2410_EINTFLT_EXTCLK (1<<7)
529#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
530
531/* removed EINTxxxx defs from here, not meant for this */
532
533/* GSTATUS have miscellaneous information in them
534 *
535 * These move between s3c2410 and s3c2412 style systems.
536 */
537
538#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
539#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
540#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
541#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
542#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
543
544#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
545#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
546#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
547#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
548#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
549
550#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
551#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
552#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
553#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
554#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
555
556#define S3C2410_GSTATUS0_nWAIT (1<<3)
557#define S3C2410_GSTATUS0_NCON (1<<2)
558#define S3C2410_GSTATUS0_RnB (1<<1)
559#define S3C2410_GSTATUS0_nBATTFLT (1<<0)
560
561#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
562#define S3C2410_GSTATUS1_2410 (0x32410000)
563#define S3C2410_GSTATUS1_2412 (0x32412001)
564#define S3C2410_GSTATUS1_2416 (0x32416003)
565#define S3C2410_GSTATUS1_2440 (0x32440000)
566#define S3C2410_GSTATUS1_2442 (0x32440aaa)
567/* some 2416 CPUs report this value also */
568#define S3C2410_GSTATUS1_2450 (0x32450003)
569
570#define S3C2410_GSTATUS2_WTRESET (1<<2)
571#define S3C2410_GSTATUS2_OFFRESET (1<<1)
572#define S3C2410_GSTATUS2_PONRESET (1<<0)
573
574/* 2412/2413 sleep configuration registers */
575
576#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
577#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
578#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
579#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
580#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
581#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
582
583/* definitions for each pin bit */
584#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
585#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
586#define S3C2412_GPIO_SLPCON_IN ( 0x02 )
587#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
588
589#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
590#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
591#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
592#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2))
593#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */
594#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
595
596#define S3C2412_SLPCON_ALL_LOW (0x0)
597#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
598#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)
599#define S3C2412_SLPCON_ALL_PULL (0x33333333)
600
601#endif /* __ASM_ARCH_REGS_GPIO_H */
602
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
new file mode 100644
index 000000000000..19575e061114
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
@@ -0,0 +1,70 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 GPIO J register definitions
11*/
12
13
14#ifndef __ASM_ARCH_REGS_GPIOJ_H
15#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
16
17/* Port J consists of 13 GPIO/Camera pins
18 *
19 * GPJCON has 2 bits for each of the input pins on port F
20 * 00 = 0 input, 1 output, 2 Camera
21 *
22 * pull up works like all other ports.
23*/
24
25#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
26#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
27#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
28#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
29
30#define S3C2440_GPJ0_OUTP (0x01 << 0)
31#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0)
32
33#define S3C2440_GPJ1_OUTP (0x01 << 2)
34#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2)
35
36#define S3C2440_GPJ2_OUTP (0x01 << 4)
37#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4)
38
39#define S3C2440_GPJ3_OUTP (0x01 << 6)
40#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6)
41
42#define S3C2440_GPJ4_OUTP (0x01 << 8)
43#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8)
44
45#define S3C2440_GPJ5_OUTP (0x01 << 10)
46#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10)
47
48#define S3C2440_GPJ6_OUTP (0x01 << 12)
49#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12)
50
51#define S3C2440_GPJ7_OUTP (0x01 << 14)
52#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14)
53
54#define S3C2440_GPJ8_OUTP (0x01 << 16)
55#define S3C2440_GPJ8_CAMPCLK (0x02 << 16)
56
57#define S3C2440_GPJ9_OUTP (0x01 << 18)
58#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18)
59
60#define S3C2440_GPJ10_OUTP (0x01 << 20)
61#define S3C2440_GPJ10_CAMHREF (0x02 << 20)
62
63#define S3C2440_GPJ11_OUTP (0x01 << 22)
64#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
65
66#define S3C2440_GPJ12_OUTP (0x01 << 24)
67#define S3C2440_GPJ12_CAMRESET (0x02 << 24)
68
69#endif /* __ASM_ARCH_REGS_GPIOJ_H */
70
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-irq.h b/arch/arm/mach-s3c24xx/include/mach/regs-irq.h
new file mode 100644
index 000000000000..0f07ba30b1fb
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-irq.h
@@ -0,0 +1,53 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef ___ASM_ARCH_REGS_IRQ_H
13#define ___ASM_ARCH_REGS_IRQ_H
14
15/* interrupt controller */
16
17#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
18#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
19#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
20
21#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
22#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
23#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
24#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
25#define S3C2410_INTPND S3C2410_IRQREG(0x010)
26#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
27#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
28#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
29
30#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030)
31#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034)
32#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040)
33#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044)
34#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048)
35#define S3C2416_INTPND2 S3C2410_IRQREG(0x050)
36#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054)
37#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070)
38#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074)
39
40/* mask: 0=enable, 1=disable
41 * 1 bit EINT, 4=EINT4, 23=EINT23
42 * EINT0,1,2,3 are not handled here.
43*/
44
45#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
46#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
47#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
48#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
49
50#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
51#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
52
53#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
new file mode 100644
index 000000000000..ee8f040aff5f
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
@@ -0,0 +1,162 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-lcd.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef ___ASM_ARCH_REGS_LCD_H
13#define ___ASM_ARCH_REGS_LCD_H
14
15#define S3C2410_LCDREG(x) (x)
16
17/* LCD control registers */
18#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
19#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
20#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
21#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
22#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
23
24#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
25#define S3C2410_LCDCON1_MMODE (1<<7)
26#define S3C2410_LCDCON1_DSCAN4 (0<<5)
27#define S3C2410_LCDCON1_STN4 (1<<5)
28#define S3C2410_LCDCON1_STN8 (2<<5)
29#define S3C2410_LCDCON1_TFT (3<<5)
30
31#define S3C2410_LCDCON1_STN1BPP (0<<1)
32#define S3C2410_LCDCON1_STN2GREY (1<<1)
33#define S3C2410_LCDCON1_STN4GREY (2<<1)
34#define S3C2410_LCDCON1_STN8BPP (3<<1)
35#define S3C2410_LCDCON1_STN12BPP (4<<1)
36
37#define S3C2410_LCDCON1_TFT1BPP (8<<1)
38#define S3C2410_LCDCON1_TFT2BPP (9<<1)
39#define S3C2410_LCDCON1_TFT4BPP (10<<1)
40#define S3C2410_LCDCON1_TFT8BPP (11<<1)
41#define S3C2410_LCDCON1_TFT16BPP (12<<1)
42#define S3C2410_LCDCON1_TFT24BPP (13<<1)
43
44#define S3C2410_LCDCON1_ENVID (1)
45
46#define S3C2410_LCDCON1_MODEMASK 0x1E
47
48#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
49#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
50#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
51#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
52
53#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
54#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
55#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
56
57#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
58#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
59#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
60#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
61#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
62
63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
65
66/* LDCCON4 changes for STN mode on the S3C2412 */
67
68#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
69#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
70#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
71
72#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
73
74#define S3C2410_LCDCON5_BPP24BL (1<<12)
75#define S3C2410_LCDCON5_FRM565 (1<<11)
76#define S3C2410_LCDCON5_INVVCLK (1<<10)
77#define S3C2410_LCDCON5_INVVLINE (1<<9)
78#define S3C2410_LCDCON5_INVVFRAME (1<<8)
79#define S3C2410_LCDCON5_INVVD (1<<7)
80#define S3C2410_LCDCON5_INVVDEN (1<<6)
81#define S3C2410_LCDCON5_INVPWREN (1<<5)
82#define S3C2410_LCDCON5_INVLEND (1<<4)
83#define S3C2410_LCDCON5_PWREN (1<<3)
84#define S3C2410_LCDCON5_ENLEND (1<<2)
85#define S3C2410_LCDCON5_BSWP (1<<1)
86#define S3C2410_LCDCON5_HWSWP (1<<0)
87
88/* framebuffer start addressed */
89#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
90#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
91#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
92
93#define S3C2410_LCDBANK(x) ((x) << 21)
94#define S3C2410_LCDBASEU(x) (x)
95
96#define S3C2410_OFFSIZE(x) ((x) << 11)
97#define S3C2410_PAGEWIDTH(x) (x)
98
99/* colour lookup and miscellaneous controls */
100
101#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
102#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
103#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
104
105#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
106#define S3C2410_TPAL S3C2410_LCDREG(0x50)
107
108#define S3C2410_TPAL_EN (1<<24)
109
110/* interrupt info */
111#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
112#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
113#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
114#define S3C2410_LCDINT_FIWSEL (1<<2)
115#define S3C2410_LCDINT_FRSYNC (1<<1)
116#define S3C2410_LCDINT_FICNT (1<<0)
117
118/* s3c2442 extra stn registers */
119
120#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
121#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
122#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
123#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
124
125#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
126
127#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
128
129/* S3C2412 registers */
130
131#define S3C2412_TPAL S3C2410_LCDREG(0x20)
132
133#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
134#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
135#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
136
137#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
138
139#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
140#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
141#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
142#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
143
144#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
145#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
146#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
147
148#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
149
150/* general registers */
151
152/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
153 * are available. */
154
155#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54)
156#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24)
157
158#define S3C24XX_LCDINTPND (0x00)
159#define S3C24XX_LCDSRCPND (0x04)
160#define S3C24XX_LCDINTMSK (0x08)
161
162#endif /* ___ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
new file mode 100644
index 000000000000..e0c67b0163d8
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
@@ -0,0 +1,202 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Memory Control register definitions
11*/
12
13#ifndef __ASM_ARM_MEMREGS_H
14#define __ASM_ARM_MEMREGS_H
15
16#ifndef S3C2410_MEMREG
17#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#endif
19
20/* bus width, and wait state control */
21#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
22
23/* bank zero config - note, pinstrapped from OM pins! */
24#define S3C2410_BWSCON_DW0_16 (1<<1)
25#define S3C2410_BWSCON_DW0_32 (2<<1)
26
27/* bank one configs */
28#define S3C2410_BWSCON_DW1_8 (0<<4)
29#define S3C2410_BWSCON_DW1_16 (1<<4)
30#define S3C2410_BWSCON_DW1_32 (2<<4)
31#define S3C2410_BWSCON_WS1 (1<<6)
32#define S3C2410_BWSCON_ST1 (1<<7)
33
34/* bank 2 configurations */
35#define S3C2410_BWSCON_DW2_8 (0<<8)
36#define S3C2410_BWSCON_DW2_16 (1<<8)
37#define S3C2410_BWSCON_DW2_32 (2<<8)
38#define S3C2410_BWSCON_WS2 (1<<10)
39#define S3C2410_BWSCON_ST2 (1<<11)
40
41/* bank 3 configurations */
42#define S3C2410_BWSCON_DW3_8 (0<<12)
43#define S3C2410_BWSCON_DW3_16 (1<<12)
44#define S3C2410_BWSCON_DW3_32 (2<<12)
45#define S3C2410_BWSCON_WS3 (1<<14)
46#define S3C2410_BWSCON_ST3 (1<<15)
47
48/* bank 4 configurations */
49#define S3C2410_BWSCON_DW4_8 (0<<16)
50#define S3C2410_BWSCON_DW4_16 (1<<16)
51#define S3C2410_BWSCON_DW4_32 (2<<16)
52#define S3C2410_BWSCON_WS4 (1<<18)
53#define S3C2410_BWSCON_ST4 (1<<19)
54
55/* bank 5 configurations */
56#define S3C2410_BWSCON_DW5_8 (0<<20)
57#define S3C2410_BWSCON_DW5_16 (1<<20)
58#define S3C2410_BWSCON_DW5_32 (2<<20)
59#define S3C2410_BWSCON_WS5 (1<<22)
60#define S3C2410_BWSCON_ST5 (1<<23)
61
62/* bank 6 configurations */
63#define S3C2410_BWSCON_DW6_8 (0<<24)
64#define S3C2410_BWSCON_DW6_16 (1<<24)
65#define S3C2410_BWSCON_DW6_32 (2<<24)
66#define S3C2410_BWSCON_WS6 (1<<26)
67#define S3C2410_BWSCON_ST6 (1<<27)
68
69/* bank 7 configurations */
70#define S3C2410_BWSCON_DW7_8 (0<<28)
71#define S3C2410_BWSCON_DW7_16 (1<<28)
72#define S3C2410_BWSCON_DW7_32 (2<<28)
73#define S3C2410_BWSCON_WS7 (1<<30)
74#define S3C2410_BWSCON_ST7 (1<<31)
75
76/* accesor functions for getting BANK(n) configuration. (n != 0) */
77
78#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
79
80#define S3C2410_BWSCON_DW8 (0)
81#define S3C2410_BWSCON_DW16 (1)
82#define S3C2410_BWSCON_DW32 (2)
83#define S3C2410_BWSCON_WS (1 << 2)
84#define S3C2410_BWSCON_ST (1 << 3)
85
86/* memory set (rom, ram) */
87#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
88#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
89#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
90#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
91#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
92#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
93#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
94#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
95
96/* bank configuration registers */
97
98#define S3C2410_BANKCON_PMCnorm (0x00)
99#define S3C2410_BANKCON_PMC4 (0x01)
100#define S3C2410_BANKCON_PMC8 (0x02)
101#define S3C2410_BANKCON_PMC16 (0x03)
102
103/* bank configurations for banks 0..7, note banks
104 * 6 and 7 have different configurations depending on
105 * the memory type bits */
106
107#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
108#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
109#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
110#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
111#define S3C2410_BANKCON_Tacp_SHIFT (2)
112
113#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
114#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
115#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
116#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
117#define S3C2410_BANKCON_Tcah_SHIFT (4)
118
119#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
120#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
121#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
122#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
123#define S3C2410_BANKCON_Tcoh_SHIFT (6)
124
125#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
126#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
127#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
128#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
129#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
130#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
131#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
132#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
133#define S3C2410_BANKCON_Tacc_SHIFT (8)
134
135#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
136#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
137#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
138#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
139#define S3C2410_BANKCON_Tcos_SHIFT (11)
140
141#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
142#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
143#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
144#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
145#define S3C2410_BANKCON_Tacs_SHIFT (13)
146
147#define S3C2410_BANKCON_SRAM (0x0 << 15)
148#define S3C2410_BANKCON_SDRAM (0x3 << 15)
149
150/* next bits only for SDRAM in 6,7 */
151#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
152#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
153#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
154
155/* control column address select */
156#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
157#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
158#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
159
160#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
161#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
162#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
163#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
164
165/* refresh control */
166
167#define S3C2410_REFRESH_REFEN (1<<23)
168#define S3C2410_REFRESH_SELF (1<<22)
169#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
170
171#define S3C2410_REFRESH_TRP_MASK (3<<20)
172#define S3C2410_REFRESH_TRP_2clk (0<<20)
173#define S3C2410_REFRESH_TRP_3clk (1<<20)
174#define S3C2410_REFRESH_TRP_4clk (2<<20)
175
176#define S3C2410_REFRESH_TSRC_MASK (3<<18)
177#define S3C2410_REFRESH_TSRC_4clk (0<<18)
178#define S3C2410_REFRESH_TSRC_5clk (1<<18)
179#define S3C2410_REFRESH_TSRC_6clk (2<<18)
180#define S3C2410_REFRESH_TSRC_7clk (3<<18)
181
182
183/* mode select register(s) */
184
185#define S3C2410_MRSRB_CL1 (0x00 << 4)
186#define S3C2410_MRSRB_CL2 (0x02 << 4)
187#define S3C2410_MRSRB_CL3 (0x03 << 4)
188
189/* bank size register */
190#define S3C2410_BANKSIZE_128M (0x2 << 0)
191#define S3C2410_BANKSIZE_64M (0x1 << 0)
192#define S3C2410_BANKSIZE_32M (0x0 << 0)
193#define S3C2410_BANKSIZE_16M (0x7 << 0)
194#define S3C2410_BANKSIZE_8M (0x6 << 0)
195#define S3C2410_BANKSIZE_4M (0x5 << 0)
196#define S3C2410_BANKSIZE_2M (0x4 << 0)
197#define S3C2410_BANKSIZE_MASK (0x7 << 0)
198#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
199#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
200#define S3C2410_BANKSIZE_BURST (1<<7)
201
202#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
new file mode 100644
index 000000000000..4932b87bdf3d
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
@@ -0,0 +1,40 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-power.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24XX power control register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_PWR
14#define __ASM_ARM_REGS_PWR __FILE__
15
16#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
19#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
20
21#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
22#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
23#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
24#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
25
26#define S3C2412_PWRCFG_BATF_IRQ (1<<0)
27#define S3C2412_PWRCFG_BATF_IGNORE (2<<0)
28#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
29#define S3C2412_PWRCFG_BATF_MASK (3<<0)
30
31#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6)
32#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6)
33#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6)
34#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6)
35#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6)
36
37#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8)
38#define S3C2412_PWRCFG_NAND_NORST (1<<9)
39
40#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
new file mode 100644
index 000000000000..fb6352515090
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
@@ -0,0 +1,48 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2412 memory register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2412_MEM
15#define __ASM_ARM_REGS_S3C2412_MEM
16
17#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
19
20#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
21#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
22
23#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
24#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
25#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08)
26#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C)
27
28#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
29#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
30
31/* EBI control registers */
32
33#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
34#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
35
36/* SSMC control registers */
37
38#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
39#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
40#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
41#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
42#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
43#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
44#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
45#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
46#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
47
48#endif /* __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
new file mode 100644
index 000000000000..aa69dc79bc38
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
@@ -0,0 +1,23 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
2 *
3 * Copyright 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2412 specific register definitions
12*/
13
14#ifndef __ASM_ARCH_REGS_S3C2412_H
15#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
16
17#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
18#define S3C2412_SWRST_RESET (0x533C2412)
19
20/* see regs-power.h for the other registers in the power block. */
21
22#endif /* __ASM_ARCH_REGS_S3C2412_H */
23
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
new file mode 100644
index 000000000000..2f31b74974af
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
@@ -0,0 +1,30 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2416 memory register definitions
13*/
14
15#ifndef __ASM_ARM_REGS_S3C2416_MEM
16#define __ASM_ARM_REGS_S3C2416_MEM
17
18#ifndef S3C2416_MEMREG
19#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
20#endif
21
22#define S3C2416_BANKCFG S3C2416_MEMREG(0x00)
23#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04)
24#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08)
25#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C)
26
27#define S3C2416_REFRESH S3C2416_MEMREG(0x10)
28#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14)
29
30#endif /* __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
new file mode 100644
index 000000000000..e443167efb87
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
@@ -0,0 +1,24 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2416 specific register definitions
13*/
14
15#ifndef __ASM_ARCH_REGS_S3C2416_H
16#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
17
18#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44)
19#define S3C2416_SWRST_RESET (0x533C2416)
20
21/* see regs-power.h for the other registers in the power block. */
22
23#endif /* __ASM_ARCH_REGS_S3C2416_H */
24
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
new file mode 100644
index 000000000000..c3feff3c0488
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
@@ -0,0 +1,194 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2443 clock register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
15#define __ASM_ARM_REGS_S3C2443_CLOCK
16
17#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
18
19#define S3C2443_PLLCON_MDIVSHIFT 16
20#define S3C2443_PLLCON_PDIVSHIFT 8
21#define S3C2443_PLLCON_SDIVSHIFT 0
22#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
23#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
24#define S3C2443_PLLCON_SDIVMASK (3)
25
26#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
27#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
28#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
29#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
30#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
31#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
32#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
33#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
34#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
35#define S3C2443_SWRST S3C2443_CLKREG(0x44)
36#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
37#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
38#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
39#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
40#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
41#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
42#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
43#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
44
45#define S3C2443_SWRST_RESET (0x533c2443)
46
47#define S3C2443_PLLCON_OFF (1<<24)
48
49#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
50#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
51#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
52#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
53#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
54
55#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
56
57#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
58#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
59
60#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
61
62#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
63#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
64
65#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
66#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
67
68#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
69#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
70#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
71#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
72#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
73#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
74#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
75#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
76#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
77#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
78#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
79
80/* S3C2443_CLKDIV1 removed, only used in clock.c code */
81
82#define S3C2443_CLKCON_NAND
83
84#define S3C2443_HCLKCON_DMA0 (1<<0)
85#define S3C2443_HCLKCON_DMA1 (1<<1)
86#define S3C2443_HCLKCON_DMA2 (1<<2)
87#define S3C2443_HCLKCON_DMA3 (1<<3)
88#define S3C2443_HCLKCON_DMA4 (1<<4)
89#define S3C2443_HCLKCON_DMA5 (1<<5)
90#define S3C2443_HCLKCON_CAMIF (1<<8)
91#define S3C2443_HCLKCON_LCDC (1<<9)
92#define S3C2443_HCLKCON_USBH (1<<11)
93#define S3C2443_HCLKCON_USBD (1<<12)
94#define S3C2416_HCLKCON_HSMMC0 (1<<15)
95#define S3C2443_HCLKCON_HSMMC (1<<16)
96#define S3C2443_HCLKCON_CFC (1<<17)
97#define S3C2443_HCLKCON_SSMC (1<<18)
98#define S3C2443_HCLKCON_DRAMC (1<<19)
99
100#define S3C2443_PCLKCON_UART0 (1<<0)
101#define S3C2443_PCLKCON_UART1 (1<<1)
102#define S3C2443_PCLKCON_UART2 (1<<2)
103#define S3C2443_PCLKCON_UART3 (1<<3)
104#define S3C2443_PCLKCON_IIC (1<<4)
105#define S3C2443_PCLKCON_SDI (1<<5)
106#define S3C2443_PCLKCON_HSSPI (1<<6)
107#define S3C2443_PCLKCON_ADC (1<<7)
108#define S3C2443_PCLKCON_AC97 (1<<8)
109#define S3C2443_PCLKCON_IIS (1<<9)
110#define S3C2443_PCLKCON_PWMT (1<<10)
111#define S3C2443_PCLKCON_WDT (1<<11)
112#define S3C2443_PCLKCON_RTC (1<<12)
113#define S3C2443_PCLKCON_GPIO (1<<13)
114#define S3C2443_PCLKCON_SPI0 (1<<14)
115#define S3C2443_PCLKCON_SPI1 (1<<15)
116
117#define S3C2443_SCLKCON_DDRCLK (1<<16)
118#define S3C2443_SCLKCON_SSMCCLK (1<<15)
119#define S3C2443_SCLKCON_HSSPICLK (1<<14)
120#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
121#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
122#define S3C2443_SCLKCON_CAMCLK (1<<11)
123#define S3C2443_SCLKCON_DISPCLK (1<<10)
124#define S3C2443_SCLKCON_I2SCLK (1<<9)
125#define S3C2443_SCLKCON_UARTCLK (1<<8)
126#define S3C2443_SCLKCON_USBHOST (1<<1)
127
128#define S3C2443_PWRCFG_SLEEP (1<<15)
129
130#define S3C2443_PWRCFG_USBPHY (1 << 4)
131
132#define S3C2443_URSTCON_FUNCRST (1 << 2)
133#define S3C2443_URSTCON_PHYRST (1 << 0)
134
135#define S3C2443_PHYCTRL_CLKSEL (1 << 3)
136#define S3C2443_PHYCTRL_EXTCLK (1 << 2)
137#define S3C2443_PHYCTRL_PLLSEL (1 << 1)
138#define S3C2443_PHYCTRL_DSPORT (1 << 0)
139
140#define S3C2443_PHYPWR_COMMON_ON (1 << 31)
141#define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
142#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
143#define S3C2443_PHYPWR_XO_ON (1 << 2)
144#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
145#define S3C2443_PHYPWR_FSUSPEND (1 << 0)
146
147#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
148#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
149#define S3C2443_UCLKCON_TCLKEN (1 << 0)
150
151#include <asm/div64.h>
152
153static inline unsigned int
154s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
155{
156 unsigned int mdiv, pdiv, sdiv;
157 uint64_t fvco;
158
159 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
160 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
161 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
162
163 mdiv &= S3C2443_PLLCON_MDIVMASK;
164 pdiv &= S3C2443_PLLCON_PDIVMASK;
165 sdiv &= S3C2443_PLLCON_SDIVMASK;
166
167 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
168 do_div(fvco, pdiv << sdiv);
169
170 return (unsigned int)fvco;
171}
172
173static inline unsigned int
174s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
175{
176 unsigned int mdiv, pdiv, sdiv;
177 uint64_t fvco;
178
179 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
180 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
181 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
182
183 mdiv &= S3C2443_PLLCON_MDIVMASK;
184 pdiv &= S3C2443_PLLCON_PDIVMASK;
185 sdiv &= S3C2443_PLLCON_SDIVMASK;
186
187 fvco = (uint64_t)baseclk * (mdiv + 8);
188 do_div(fvco, (pdiv + 2) << sdiv);
189
190 return (unsigned int)fvco;
191}
192
193#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
194
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
new file mode 100644
index 000000000000..cbf2d8884e30
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
@@ -0,0 +1,127 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 MMC/SDIO register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_SDI
14#define __ASM_ARM_REGS_SDI "regs-sdi.h"
15
16#define S3C2410_SDICON (0x00)
17#define S3C2410_SDIPRE (0x04)
18#define S3C2410_SDICMDARG (0x08)
19#define S3C2410_SDICMDCON (0x0C)
20#define S3C2410_SDICMDSTAT (0x10)
21#define S3C2410_SDIRSP0 (0x14)
22#define S3C2410_SDIRSP1 (0x18)
23#define S3C2410_SDIRSP2 (0x1C)
24#define S3C2410_SDIRSP3 (0x20)
25#define S3C2410_SDITIMER (0x24)
26#define S3C2410_SDIBSIZE (0x28)
27#define S3C2410_SDIDCON (0x2C)
28#define S3C2410_SDIDCNT (0x30)
29#define S3C2410_SDIDSTA (0x34)
30#define S3C2410_SDIFSTA (0x38)
31
32#define S3C2410_SDIDATA (0x3C)
33#define S3C2410_SDIIMSK (0x40)
34
35#define S3C2440_SDIDATA (0x40)
36#define S3C2440_SDIIMSK (0x3C)
37
38#define S3C2440_SDICON_SDRESET (1<<8)
39#define S3C2440_SDICON_MMCCLOCK (1<<5)
40#define S3C2410_SDICON_BYTEORDER (1<<4)
41#define S3C2410_SDICON_SDIOIRQ (1<<3)
42#define S3C2410_SDICON_RWAITEN (1<<2)
43#define S3C2410_SDICON_FIFORESET (1<<1)
44#define S3C2410_SDICON_CLOCKTYPE (1<<0)
45
46#define S3C2410_SDICMDCON_ABORT (1<<12)
47#define S3C2410_SDICMDCON_WITHDATA (1<<11)
48#define S3C2410_SDICMDCON_LONGRSP (1<<10)
49#define S3C2410_SDICMDCON_WAITRSP (1<<9)
50#define S3C2410_SDICMDCON_CMDSTART (1<<8)
51#define S3C2410_SDICMDCON_SENDERHOST (1<<6)
52#define S3C2410_SDICMDCON_INDEX (0x3f)
53
54#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12)
55#define S3C2410_SDICMDSTAT_CMDSENT (1<<11)
56#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
57#define S3C2410_SDICMDSTAT_RSPFIN (1<<9)
58#define S3C2410_SDICMDSTAT_XFERING (1<<8)
59#define S3C2410_SDICMDSTAT_INDEX (0xff)
60
61#define S3C2440_SDIDCON_DS_BYTE (0<<22)
62#define S3C2440_SDIDCON_DS_HALFWORD (1<<22)
63#define S3C2440_SDIDCON_DS_WORD (2<<22)
64#define S3C2410_SDIDCON_IRQPERIOD (1<<21)
65#define S3C2410_SDIDCON_TXAFTERRESP (1<<20)
66#define S3C2410_SDIDCON_RXAFTERCMD (1<<19)
67#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18)
68#define S3C2410_SDIDCON_BLOCKMODE (1<<17)
69#define S3C2410_SDIDCON_WIDEBUS (1<<16)
70#define S3C2410_SDIDCON_DMAEN (1<<15)
71#define S3C2410_SDIDCON_STOP (1<<14)
72#define S3C2440_SDIDCON_DATSTART (1<<14)
73#define S3C2410_SDIDCON_DATMODE (3<<12)
74#define S3C2410_SDIDCON_BLKNUM (0x7ff)
75
76/* constants for S3C2410_SDIDCON_DATMODE */
77#define S3C2410_SDIDCON_XFER_READY (0<<12)
78#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
79#define S3C2410_SDIDCON_XFER_RXSTART (2<<12)
80#define S3C2410_SDIDCON_XFER_TXSTART (3<<12)
81
82#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
83#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12)
84
85#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10)
86#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
87#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */
88#define S3C2410_SDIDSTA_CRCFAIL (1<<7)
89#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6)
90#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5)
91#define S3C2410_SDIDSTA_XFERFINISH (1<<4)
92#define S3C2410_SDIDSTA_BUSYFINISH (1<<3)
93#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */
94#define S3C2410_SDIDSTA_TXDATAON (1<<1)
95#define S3C2410_SDIDSTA_RXDATAON (1<<0)
96
97#define S3C2440_SDIFSTA_FIFORESET (1<<16)
98#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */
99#define S3C2410_SDIFSTA_TFDET (1<<13)
100#define S3C2410_SDIFSTA_RFDET (1<<12)
101#define S3C2410_SDIFSTA_TFHALF (1<<11)
102#define S3C2410_SDIFSTA_TFEMPTY (1<<10)
103#define S3C2410_SDIFSTA_RFLAST (1<<9)
104#define S3C2410_SDIFSTA_RFFULL (1<<8)
105#define S3C2410_SDIFSTA_RFHALF (1<<7)
106#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
107
108#define S3C2410_SDIIMSK_RESPONSECRC (1<<17)
109#define S3C2410_SDIIMSK_CMDSENT (1<<16)
110#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15)
111#define S3C2410_SDIIMSK_RESPONSEND (1<<14)
112#define S3C2410_SDIIMSK_READWAIT (1<<13)
113#define S3C2410_SDIIMSK_SDIOIRQ (1<<12)
114#define S3C2410_SDIIMSK_FIFOFAIL (1<<11)
115#define S3C2410_SDIIMSK_CRCSTATUS (1<<10)
116#define S3C2410_SDIIMSK_DATACRC (1<<9)
117#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8)
118#define S3C2410_SDIIMSK_DATAFINISH (1<<7)
119#define S3C2410_SDIIMSK_BUSYFINISH (1<<6)
120#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */
121#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4)
122#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3)
123#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2)
124#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1)
125#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0)
126
127#endif /* __ASM_ARM_REGS_SDI */
diff --git a/arch/arm/mach-s3c24xx/include/mach/tick.h b/arch/arm/mach-s3c24xx/include/mach/tick.h
new file mode 100644
index 000000000000..544da41979db
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/tick.h
@@ -0,0 +1,15 @@
1/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C2410 - timer tick support
8 */
9
10#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
11
12static inline int s3c24xx_ostimer_pending(void)
13{
14 return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
15}
diff --git a/arch/arm/mach-s3c24xx/include/mach/timex.h b/arch/arm/mach-s3c24xx/include/mach/timex.h
new file mode 100644
index 000000000000..fe9ca1ffd51b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/timex.h
@@ -0,0 +1,24 @@
1/* arch/arm/mach-s3c2410/include/mach/timex.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
17 * a variable is useless. It seems as long as we make our timers an
18 * exact multiple of HZ, any value that makes a 1->1 correspondence
19 * for the time conversion functions to/from jiffies is acceptable.
20*/
21
22#define CLOCK_TICK_RATE 12000000
23
24#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..8b283f847daa
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
@@ -0,0 +1,54 @@
1/* arch/arm/mach-s3c2410/include/mach/uncompress.h
2 *
3 * Copyright (c) 2003-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 - uncompress code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_UNCOMPRESS_H
15#define __ASM_ARCH_UNCOMPRESS_H
16
17#include <mach/regs-gpio.h>
18#include <mach/map.h>
19
20/* working in physical space... */
21#undef S3C2410_GPIOREG
22#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
23
24#include <plat/uncompress.h>
25
26static inline int is_arm926(void)
27{
28 unsigned int cpuid;
29
30 asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
31
32 return ((cpuid & 0xff0) == 0x260);
33}
34
35static void arch_detect_cpu(void)
36{
37 unsigned int cpuid;
38
39 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
40 cpuid &= S3C2410_GSTATUS1_IDMASK;
41
42 if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
43 cpuid == S3C2410_GSTATUS1_2442 ||
44 cpuid == S3C2410_GSTATUS1_2416 ||
45 cpuid == S3C2410_GSTATUS1_2450) {
46 fifo_mask = S3C2440_UFSTAT_TXMASK;
47 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
48 } else {
49 fifo_mask = S3C2410_UFSTAT_TXMASK;
50 fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
51 }
52}
53
54#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
new file mode 100644
index 000000000000..e4119913d7c5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * VR1000 - CPLD control constants
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_VR1000CPLD_H
14#define __ASM_ARCH_VR1000CPLD_H
15
16#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
17
18#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
new file mode 100644
index 000000000000..47add133b8ee
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
@@ -0,0 +1,26 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - IRQ Number definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_VR1000IRQ_H
14#define __ASM_ARCH_VR1000IRQ_H
15
16/* irq numbers to onboard peripherals */
17
18#define IRQ_USBOC IRQ_EINT19
19#define IRQ_IDE0 IRQ_EINT16
20#define IRQ_IDE1 IRQ_EINT17
21#define IRQ_VR1000_SERIAL IRQ_EINT12
22#define IRQ_VR1000_DM9000A IRQ_EINT10
23#define IRQ_VR1000_DM9000N IRQ_EINT9
24#define IRQ_SMALERT IRQ_EINT8
25
26#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
new file mode 100644
index 000000000000..99612fcc4eb2
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
@@ -0,0 +1,110 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x13000000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space. We also have the board's CPLD to find register space
18 * for.
19 */
20
21#ifndef __ASM_ARCH_VR1000MAP_H
22#define __ASM_ARCH_VR1000MAP_H
23
24#include <mach/bast-map.h>
25
26#define VR1000_IOADDR(x) BAST_IOADDR(x)
27
28/* we put the CPLD registers next, to get them out of the way */
29
30#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
31#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
32
33#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
34#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
35
36#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
37#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
38
39#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
40#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
41
42/* next, we have the PC104 ISA interrupt registers */
43
44#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
45#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
46
47#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
48#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
49
50#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
51#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
52
53/* 0xE0000000 contains the IO space that is split by speed and
54 * wether the access is for 8 or 16bit IO... this ensures that
55 * the correct access is made
56 *
57 * 0x10000000 of space, partitioned as so:
58 *
59 * 0x00000000 to 0x04000000 8bit, slow
60 * 0x04000000 to 0x08000000 16bit, slow
61 * 0x08000000 to 0x0C000000 16bit, net
62 * 0x0C000000 to 0x10000000 16bit, fast
63 *
64 * each of these spaces has the following in:
65 *
66 * 0x02000000 to 0x02100000 1MB IDE primary channel
67 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
68 * 0x02200000 to 0x02400000 1MB IDE secondary channel
69 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
70 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
71 * 0x02600000 to 0x02700000 1MB
72 *
73 * the phyiscal layout of the zones are:
74 * nGCS2 - 8bit, slow
75 * nGCS3 - 16bit, slow
76 * nGCS4 - 16bit, net
77 * nGCS5 - 16bit, fast
78 */
79
80#define VR1000_VA_MULTISPACE (0xE0000000)
81
82#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
83#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
84#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
85#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
86#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
87#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
88#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
89#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
90#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
91
92/* physical offset addresses for the peripherals */
93
94#define VR1000_PA_IDEPRI (0x02000000)
95#define VR1000_PA_IDEPRIAUX (0x02800000)
96#define VR1000_PA_IDESEC (0x03000000)
97#define VR1000_PA_IDESECAUX (0x03800000)
98#define VR1000_PA_DM9000 (0x05000000)
99
100#define VR1000_PA_SERIAL (0x11800000)
101#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
102
103/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
104#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
105
106/* some configurations for the peripherals */
107
108#define VR1000_DM9000_CS VR1000_VAM_CS4
109
110#endif /* __ASM_ARCH_VR1000MAP_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 13:24:41 -0400