diff options
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h')
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h index a4bf27123170..fb6352515090 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h | |||
@@ -14,9 +14,11 @@ | |||
14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM | 14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM |
15 | #define __ASM_ARM_REGS_S3C2412_MEM | 15 | #define __ASM_ARM_REGS_S3C2412_MEM |
16 | 16 | ||
17 | #ifndef S3C2412_MEMREG | ||
18 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) | 17 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) |
19 | #endif | 18 | #define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) |
19 | |||
20 | #define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) | ||
21 | #define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) | ||
20 | 22 | ||
21 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) | 23 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) |
22 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) | 24 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) |
@@ -26,4 +28,21 @@ | |||
26 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) | 28 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) |
27 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) | 29 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) |
28 | 30 | ||
31 | /* EBI control registers */ | ||
32 | |||
33 | #define S3C2412_EBI_PR S3C2412_EBIREG(0x00) | ||
34 | #define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) | ||
35 | |||
36 | /* SSMC control registers */ | ||
37 | |||
38 | #define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) | ||
39 | #define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) | ||
40 | #define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) | ||
41 | #define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) | ||
42 | #define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) | ||
43 | #define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) | ||
44 | #define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) | ||
45 | #define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) | ||
46 | #define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) | ||
47 | |||
29 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ | 48 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ |