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-rw-r--r--arch/arm/mach-rpc/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-rpc/include/mach/memory.h2
-rw-r--r--arch/arm/mach-rpc/include/mach/uncompress.h12
-rw-r--r--arch/arm/mach-rpc/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-rpc/irq.c74
-rw-r--r--arch/arm/mach-rpc/riscpc.c2
6 files changed, 50 insertions, 54 deletions
diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S
index 6fc8d66395dc..85effffdc2b2 100644
--- a/arch/arm/mach-rpc/include/mach/debug-macro.S
+++ b/arch/arm/mach-rpc/include/mach/debug-macro.S
@@ -11,13 +11,11 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x00010000
16 tst \rx, #1 @ MMU enabled? 16 orr \rp, \rp, #0x00000fe0
17 moveq \rx, #0x03000000 17 orr \rv, \rp, #0xe0000000 @ virtual
18 movne \rx, #0xe0000000 18 orr \rp, \rp, #0x03000000 @ physical
19 orr \rx, \rx, #0x00010000
20 orr \rx, \rx, #0x00000fe0
21 .endm 19 .endm
22 20
23#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h
index 78191bf25192..18a221093bf5 100644
--- a/arch/arm/mach-rpc/include/mach/memory.h
+++ b/arch/arm/mach-rpc/include/mach/memory.h
@@ -21,7 +21,7 @@
21/* 21/*
22 * Physical DRAM offset. 22 * Physical DRAM offset.
23 */ 23 */
24#define PHYS_OFFSET UL(0x10000000) 24#define PLAT_PHYS_OFFSET UL(0x10000000)
25 25
26/* 26/*
27 * Cache flushing area - ROM 27 * Cache flushing area - ROM
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index 8c9e2c7161c6..9cd9bcdad6cc 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -66,12 +66,12 @@ extern __attribute__((pure)) struct param_struct *params(void);
66#define params (params()) 66#define params (params())
67 67
68#ifndef STANDALONE_DEBUG 68#ifndef STANDALONE_DEBUG
69static unsigned long video_num_cols; 69unsigned long video_num_cols;
70static unsigned long video_num_rows; 70unsigned long video_num_rows;
71static unsigned long video_x; 71unsigned long video_x;
72static unsigned long video_y; 72unsigned long video_y;
73static unsigned char bytes_per_char_v; 73unsigned char bytes_per_char_v;
74static int white; 74int white;
75 75
76/* 76/*
77 * This does not append a newline 77 * This does not append a newline
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
index 9a96fd69e705..fb700228637a 100644
--- a/arch/arm/mach-rpc/include/mach/vmalloc.h
+++ b/arch/arm/mach-rpc/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#define VMALLOC_END (PAGE_OFFSET + 0x1c000000) 10#define VMALLOC_END 0xdc000000UL
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 9dd15d679c5d..2e1b5309fbab 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -6,110 +6,110 @@
6#include <asm/hardware/iomd.h> 6#include <asm/hardware/iomd.h>
7#include <asm/irq.h> 7#include <asm/irq.h>
8 8
9static void iomd_ack_irq_a(unsigned int irq) 9static void iomd_ack_irq_a(struct irq_data *d)
10{ 10{
11 unsigned int val, mask; 11 unsigned int val, mask;
12 12
13 mask = 1 << irq; 13 mask = 1 << d->irq;
14 val = iomd_readb(IOMD_IRQMASKA); 14 val = iomd_readb(IOMD_IRQMASKA);
15 iomd_writeb(val & ~mask, IOMD_IRQMASKA); 15 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
16 iomd_writeb(mask, IOMD_IRQCLRA); 16 iomd_writeb(mask, IOMD_IRQCLRA);
17} 17}
18 18
19static void iomd_mask_irq_a(unsigned int irq) 19static void iomd_mask_irq_a(struct irq_data *d)
20{ 20{
21 unsigned int val, mask; 21 unsigned int val, mask;
22 22
23 mask = 1 << irq; 23 mask = 1 << d->irq;
24 val = iomd_readb(IOMD_IRQMASKA); 24 val = iomd_readb(IOMD_IRQMASKA);
25 iomd_writeb(val & ~mask, IOMD_IRQMASKA); 25 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
26} 26}
27 27
28static void iomd_unmask_irq_a(unsigned int irq) 28static void iomd_unmask_irq_a(struct irq_data *d)
29{ 29{
30 unsigned int val, mask; 30 unsigned int val, mask;
31 31
32 mask = 1 << irq; 32 mask = 1 << d->irq;
33 val = iomd_readb(IOMD_IRQMASKA); 33 val = iomd_readb(IOMD_IRQMASKA);
34 iomd_writeb(val | mask, IOMD_IRQMASKA); 34 iomd_writeb(val | mask, IOMD_IRQMASKA);
35} 35}
36 36
37static struct irq_chip iomd_a_chip = { 37static struct irq_chip iomd_a_chip = {
38 .ack = iomd_ack_irq_a, 38 .irq_ack = iomd_ack_irq_a,
39 .mask = iomd_mask_irq_a, 39 .irq_mask = iomd_mask_irq_a,
40 .unmask = iomd_unmask_irq_a, 40 .irq_unmask = iomd_unmask_irq_a,
41}; 41};
42 42
43static void iomd_mask_irq_b(unsigned int irq) 43static void iomd_mask_irq_b(struct irq_data *d)
44{ 44{
45 unsigned int val, mask; 45 unsigned int val, mask;
46 46
47 mask = 1 << (irq & 7); 47 mask = 1 << (d->irq & 7);
48 val = iomd_readb(IOMD_IRQMASKB); 48 val = iomd_readb(IOMD_IRQMASKB);
49 iomd_writeb(val & ~mask, IOMD_IRQMASKB); 49 iomd_writeb(val & ~mask, IOMD_IRQMASKB);
50} 50}
51 51
52static void iomd_unmask_irq_b(unsigned int irq) 52static void iomd_unmask_irq_b(struct irq_data *d)
53{ 53{
54 unsigned int val, mask; 54 unsigned int val, mask;
55 55
56 mask = 1 << (irq & 7); 56 mask = 1 << (d->irq & 7);
57 val = iomd_readb(IOMD_IRQMASKB); 57 val = iomd_readb(IOMD_IRQMASKB);
58 iomd_writeb(val | mask, IOMD_IRQMASKB); 58 iomd_writeb(val | mask, IOMD_IRQMASKB);
59} 59}
60 60
61static struct irq_chip iomd_b_chip = { 61static struct irq_chip iomd_b_chip = {
62 .ack = iomd_mask_irq_b, 62 .irq_ack = iomd_mask_irq_b,
63 .mask = iomd_mask_irq_b, 63 .irq_mask = iomd_mask_irq_b,
64 .unmask = iomd_unmask_irq_b, 64 .irq_unmask = iomd_unmask_irq_b,
65}; 65};
66 66
67static void iomd_mask_irq_dma(unsigned int irq) 67static void iomd_mask_irq_dma(struct irq_data *d)
68{ 68{
69 unsigned int val, mask; 69 unsigned int val, mask;
70 70
71 mask = 1 << (irq & 7); 71 mask = 1 << (d->irq & 7);
72 val = iomd_readb(IOMD_DMAMASK); 72 val = iomd_readb(IOMD_DMAMASK);
73 iomd_writeb(val & ~mask, IOMD_DMAMASK); 73 iomd_writeb(val & ~mask, IOMD_DMAMASK);
74} 74}
75 75
76static void iomd_unmask_irq_dma(unsigned int irq) 76static void iomd_unmask_irq_dma(struct irq_data *d)
77{ 77{
78 unsigned int val, mask; 78 unsigned int val, mask;
79 79
80 mask = 1 << (irq & 7); 80 mask = 1 << (d->irq & 7);
81 val = iomd_readb(IOMD_DMAMASK); 81 val = iomd_readb(IOMD_DMAMASK);
82 iomd_writeb(val | mask, IOMD_DMAMASK); 82 iomd_writeb(val | mask, IOMD_DMAMASK);
83} 83}
84 84
85static struct irq_chip iomd_dma_chip = { 85static struct irq_chip iomd_dma_chip = {
86 .ack = iomd_mask_irq_dma, 86 .irq_ack = iomd_mask_irq_dma,
87 .mask = iomd_mask_irq_dma, 87 .irq_mask = iomd_mask_irq_dma,
88 .unmask = iomd_unmask_irq_dma, 88 .irq_unmask = iomd_unmask_irq_dma,
89}; 89};
90 90
91static void iomd_mask_irq_fiq(unsigned int irq) 91static void iomd_mask_irq_fiq(struct irq_data *d)
92{ 92{
93 unsigned int val, mask; 93 unsigned int val, mask;
94 94
95 mask = 1 << (irq & 7); 95 mask = 1 << (d->irq & 7);
96 val = iomd_readb(IOMD_FIQMASK); 96 val = iomd_readb(IOMD_FIQMASK);
97 iomd_writeb(val & ~mask, IOMD_FIQMASK); 97 iomd_writeb(val & ~mask, IOMD_FIQMASK);
98} 98}
99 99
100static void iomd_unmask_irq_fiq(unsigned int irq) 100static void iomd_unmask_irq_fiq(struct irq_data *d)
101{ 101{
102 unsigned int val, mask; 102 unsigned int val, mask;
103 103
104 mask = 1 << (irq & 7); 104 mask = 1 << (d->irq & 7);
105 val = iomd_readb(IOMD_FIQMASK); 105 val = iomd_readb(IOMD_FIQMASK);
106 iomd_writeb(val | mask, IOMD_FIQMASK); 106 iomd_writeb(val | mask, IOMD_FIQMASK);
107} 107}
108 108
109static struct irq_chip iomd_fiq_chip = { 109static struct irq_chip iomd_fiq_chip = {
110 .ack = iomd_mask_irq_fiq, 110 .irq_ack = iomd_mask_irq_fiq,
111 .mask = iomd_mask_irq_fiq, 111 .irq_mask = iomd_mask_irq_fiq,
112 .unmask = iomd_unmask_irq_fiq, 112 .irq_unmask = iomd_unmask_irq_fiq,
113}; 113};
114 114
115void __init rpc_init_irq(void) 115void __init rpc_init_irq(void)
@@ -133,25 +133,25 @@ void __init rpc_init_irq(void)
133 133
134 switch (irq) { 134 switch (irq) {
135 case 0 ... 7: 135 case 0 ... 7:
136 set_irq_chip(irq, &iomd_a_chip); 136 irq_set_chip_and_handler(irq, &iomd_a_chip,
137 set_irq_handler(irq, handle_level_irq); 137 handle_level_irq);
138 set_irq_flags(irq, flags); 138 set_irq_flags(irq, flags);
139 break; 139 break;
140 140
141 case 8 ... 15: 141 case 8 ... 15:
142 set_irq_chip(irq, &iomd_b_chip); 142 irq_set_chip_and_handler(irq, &iomd_b_chip,
143 set_irq_handler(irq, handle_level_irq); 143 handle_level_irq);
144 set_irq_flags(irq, flags); 144 set_irq_flags(irq, flags);
145 break; 145 break;
146 146
147 case 16 ... 21: 147 case 16 ... 21:
148 set_irq_chip(irq, &iomd_dma_chip); 148 irq_set_chip_and_handler(irq, &iomd_dma_chip,
149 set_irq_handler(irq, handle_level_irq); 149 handle_level_irq);
150 set_irq_flags(irq, flags); 150 set_irq_flags(irq, flags);
151 break; 151 break;
152 152
153 case 64 ... 71: 153 case 64 ... 71:
154 set_irq_chip(irq, &iomd_fiq_chip); 154 irq_set_chip(irq, &iomd_fiq_chip);
155 set_irq_flags(irq, IRQF_VALID); 155 set_irq_flags(irq, IRQF_VALID);
156 break; 156 break;
157 } 157 }
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index c7fc01e9d1f6..580b3c73d2c7 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -218,8 +218,6 @@ extern struct sys_timer ioc_timer;
218 218
219MACHINE_START(RISCPC, "Acorn-RiscPC") 219MACHINE_START(RISCPC, "Acorn-RiscPC")
220 /* Maintainer: Russell King */ 220 /* Maintainer: Russell King */
221 .phys_io = 0x03000000,
222 .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
223 .boot_params = 0x10000100, 221 .boot_params = 0x10000100,
224 .reserve_lp0 = 1, 222 .reserve_lp0 = 1,
225 .reserve_lp1 = 1, 223 .reserve_lp1 = 1,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 14:08:06 -0500