72 files changed, 4068 insertions, 1133 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index a062235e83a8..8eea7306f29b 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -19,20 +19,34 @@ config CPU_PXA320
 config CPU_PXA930
        bool "PXA930 (codename Tavor-P)"
+config CPU_PXA935
+        bool "PXA935 (codename Tavor-P65)"
 endmenu
 endif
 config ARCH_GUMSTIX
-        bool "Gumstix XScale boards"
+        bool "Gumstix XScale 255 boards"
+        select PXA25x
        help
-          Say Y here if you intend to run this kernel on a
+          Say Y here if you intend to run this kernel on
-          Gumstix Full Function Minature Computer.
+          Basix, Connex, ws-200ax, ws-400ax systems
-config MACH_GUMSTIX_F
+choice
-        bool "Basix, Connex, ws-200ax, ws-400ax systems"
+        prompt "Gumstix Carrier/Expansion Board"
        depends on ARCH_GUMSTIX
-        select PXA25x
+config GUMSTIX_AM200EPD
+        bool "Enable AM200EPD board support"
+endchoice
+config MACH_INTELMOTE2
+        bool "Intel Mote 2 Platform"
+        select PXA27x
+        select IWMMXT
+        select PXA_HAVE_BOARD_IRQS
 config ARCH_LUBBOCK
        bool "Intel DBPXA250 Development Platform"
@@ -199,6 +213,10 @@ config MACH_E800
 config TRIZEPS_PXA
        bool "PXA based Keith und Koep Trizeps DIMM-Modules"
+config MACH_H5000
+        bool "HP iPAQ h5000"
+        select PXA25x
 config MACH_TRIZEPS4
        bool "Keith und Koep Trizeps4 DIMM-Module"
        depends on TRIZEPS_PXA
@@ -283,7 +301,6 @@ config MACH_MIOA701
        bool "Mitac Mio A701 Support"
        select PXA27x
        select IWMMXT
-        select LEDS_GPIO
        select HAVE_PWM
        select GPIO_SYSFS
        help
@@ -342,10 +359,6 @@ config PCM990_DISPLAY_NONE
 endchoice
-config MACH_AM200EPD
-        depends on MACH_GUMSTIX_F
-        bool "Enable AM200EPD board support"
 config PXA_EZX
        bool "Motorola EZX Platform"
        select PXA27x
@@ -386,16 +399,25 @@ endmenu
 config PXA25x
        bool
+        select CPU_XSCALE
        help
          Select code specific to PXA21x/25x/26x variants
 config PXA27x
        bool
+        select CPU_XSCALE
        help
          Select code specific to PXA27x variants
+config CPU_PXA26x
+        bool
+        select PXA25x
+        help
+          Select code specific to PXA26x (codename Dalhart)
 config PXA3xx
        bool
+        select CPU_XSC3
        help
          Select code specific to PXA3xx variants
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index d64c68b232e3..7b28bb561d63 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 # Specific board support
 obj-$(CONFIG_ARCH_GUMSTIX)      += gumstix.o
-obj-$(CONFIG_MACH_AM200EPD)     += am200epd.o
+obj-$(CONFIG_GUMSTIX_AM200EPD)  += am200epd.o
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
@@ -35,6 +35,7 @@ obj-$(CONFIG_MACH_MP900C)	+= mp900.o
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
 obj-$(CONFIG_MACH_TRIZEPS4)     += trizeps4.o
 obj-$(CONFIG_MACH_COLIBRI)      += colibri.o
+obj-$(CONFIG_MACH_H5000)        += h5000.o
 obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o sharpsl_pm.o corgi_pm.o
 obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o sharpsl_pm.o spitz_pm.o
 obj-$(CONFIG_CORGI_SSP_DEPRECATED)      += corgi_ssp.o corgi_lcd.o
@@ -69,6 +70,8 @@ obj-$(CONFIG_MACH_ARMCORE)      += cm-x2xx.o cm-x255.o cm-x270.o
 obj-$(CONFIG_MACH_CM_X300)      += cm-x300.o
 obj-$(CONFIG_PXA_EZX)           += ezx.o
+obj-$(CONFIG_MACH_INTELMOTE2)   += imote2.o
 # Support for blinky lights
 led-y := leds.o
 led-$(CONFIG_ARCH_LUBBOCK)      += leds-lubbock.o
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index b965085a37b9..77ee80e5e47b 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -30,8 +30,12 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
+#include <mach/gumstix.h>
+#include <mach/mfp-pxa25x.h>
 #include <mach/pxafb.h>
+#include "generic.h"
 #include <video/metronomefb.h>
 static unsigned int panel_type = 6;
@@ -331,7 +335,16 @@ static struct metronome_board am200_board = {
        .cleanup                = am200_cleanup,
 };
-static int __init am200_init(void)
+static unsigned long am200_pin_config[] __initdata = {
+        GPIO51_GPIO,
+        GPIO49_GPIO,
+        GPIO48_GPIO,
+        GPIO32_GPIO,
+        GPIO17_GPIO,
+        GPIO16_GPIO,
+};
+int __init am200_init(void)
 {
        int ret;
@@ -339,6 +352,8 @@ static int __init am200_init(void)
         * creation events */
        fb_register_client(&am200_fb_notif);
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(am200_pin_config));
        /* request our platform independent driver */
        request_module("metronomefb");
@@ -367,8 +382,6 @@ static int __init am200_init(void)
 module_param(panel_type, uint, 0);
 MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97");
-module_init(am200_init);
 MODULE_DESCRIPTION("board driver for am200 metronome epd kit");
 MODULE_AUTHOR("Jaya Kumar");
 MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index ca8e20538157..40b774084514 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -12,53 +12,16 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <asm/clkdev.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
 #include <mach/hardware.h>
 #include "devices.h"
 #include "generic.h"
 #include "clock.h"
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clocks_lock);
-static struct clk *clk_lookup(struct device *dev, const char *id)
-{
-        struct clk *p;
-        list_for_each_entry(p, &clocks, node)
-                if (strcmp(id, p->name) == 0 && p->dev == dev)
-                        return p;
-        return NULL;
-}
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        mutex_lock(&clocks_mutex);
-        p = clk_lookup(dev, id);
-        if (!p)
-                p = clk_lookup(NULL, id);
-        if (p)
-                clk = p;
-        mutex_unlock(&clocks_mutex);
-        if (!IS_ERR(clk) && clk->ops == NULL)
-                clk = clk->other;
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
 int clk_enable(struct clk *clk)
 {
        unsigned long flags;
@@ -116,37 +79,27 @@ const struct clkops clk_cken_ops = {
        .disable        = clk_cken_disable,
 };
-void clks_register(struct clk *clks, size_t num)
+void clks_register(struct clk_lookup *clks, size_t num)
 {
        int i;
-        mutex_lock(&clocks_mutex);
        for (i = 0; i < num; i++)
-                list_add(&clks[i].node, &clocks);
+                clkdev_add(&clks[i]);
-        mutex_unlock(&clocks_mutex);
 }
 int clk_add_alias(char *alias, struct device *alias_dev, char *id,
        struct device *dev)
 {
-        struct clk *r = clk_lookup(dev, id);
+        struct clk *r = clk_get(dev, id);
-        struct clk *new;
+        struct clk_lookup *l;
        if (!r)
                return -ENODEV;
-        new = kzalloc(sizeof(struct clk), GFP_KERNEL);
+        l = clkdev_alloc(r, alias, alias_dev ? dev_name(alias_dev) : NULL);
+        clk_put(r);
-        if (!new)
+        if (!l)
-                return -ENOMEM;
+                return -ENODEV;
+        clkdev_add(l);
-        new->name = alias;
-        new->dev = alias_dev;
-        new->other = r;
-        mutex_lock(&clocks_mutex);
-        list_add(&new->node, &clocks);
-        mutex_unlock(&clocks_mutex);
        return 0;
 }
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 73be795fe3bf..4e9c613c6767 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -1,6 +1,4 @@
-#include <linux/list.h>
+#include <asm/clkdev.h>
-struct clk;
 struct clkops {
        void                    (*enable)(struct clk *);
@@ -9,9 +7,6 @@ struct clkops {
 };
 struct clk {
-        struct list_head        node;
-        const char              *name;
-        struct device           *dev;
        const struct clkops     *ops;
        unsigned long           rate;
        unsigned int            cken;
@@ -20,41 +15,31 @@ struct clk {
        struct clk              *other;
 };
-#define INIT_CKEN(_name, _cken, _rate, _delay, _dev)    \
+#define INIT_CLKREG(_clk,_devname,_conname)             \
        {                                               \
-                .name   = _name,                        \
+                .clk            = _clk,                 \
-                .dev    = _dev,                         \
+                .dev_id         = _devname,             \
+                .con_id         = _conname,             \
+        }
+#define DEFINE_CKEN(_name, _cken, _rate, _delay)        \
+struct clk clk_##_name = {                              \
                .ops    = &clk_cken_ops,                \
                .rate   = _rate,                        \
                .cken   = CKEN_##_cken,                 \
                .delay  = _delay,                       \
        }
-#define INIT_CK(_name, _cken, _ops, _dev)               \
+#define DEFINE_CK(_name, _cken, _ops)                   \
-        {                                               \
+struct clk clk_##_name = {                              \
-                .name   = _name,                        \
-                .dev    = _dev,                         \
                .ops    = _ops,                         \
                .cken   = CKEN_##_cken,                 \
        }
-/*
+#define DEFINE_CLK(_name, _ops, _rate, _delay)          \
- * This is a placeholder to alias one clock device+name pair
+struct clk clk_##_name = {                              \
- * to another struct clk.
+                .ops    = _ops,                         \
- */
+                .rate   = _rate,                        \
-#define INIT_CKOTHER(_name, _other, _dev)               \
-        {                                               \
-                .name   = _name,                        \
-                .dev    = _dev,                         \
-                .other  = _other,                       \
-        }
-#define INIT_CLK(_name, _ops, _rate, _delay, _dev)      \
-        {                                               \
-                .name   = _name,                        \
-                .dev    = _dev,                         \
-                .ops    = _ops,                         \
-                .rate   = _rate,                        \
                .delay  = _delay,                       \
        }
@@ -64,20 +49,16 @@ void clk_cken_enable(struct clk *clk);
 void clk_cken_disable(struct clk *clk);
 #ifdef CONFIG_PXA3xx
-#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev)  \
+#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay)   \
-        {                                               \
+struct clk clk_##_name = {                              \
-                .name   = _name,                        \
-                .dev    = _dev,                         \
                .ops    = &clk_pxa3xx_cken_ops,         \
                .rate   = _rate,                        \
                .cken   = CKEN_##_cken,                 \
                .delay  = _delay,                       \
        }
-#define PXA3xx_CK(_name, _cken, _ops, _dev)             \
+#define DEFINE_PXA3_CK(_name, _cken, _ops)              \
-        {                                               \
+struct clk clk_##_name = {                              \
-                .name   = _name,                        \
-                .dev    = _dev,                         \
                .ops    = _ops,                         \
                .cken   = CKEN_##_cken,                 \
        }
@@ -87,7 +68,7 @@ extern void clk_pxa3xx_cken_enable(struct clk *);
 extern void clk_pxa3xx_cken_disable(struct clk *);
 #endif
-void clks_register(struct clk *clks, size_t num);
+void clks_register(struct clk_lookup *clks, size_t num);
 int clk_add_alias(char *alias, struct device *alias_dev, char *id,
        struct device *dev);
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index 0b3ce3b6d896..d99fd9e4d888 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -210,10 +210,8 @@ static struct pxafb_mode_info generic_stn_320x240_mode = {
 static struct pxafb_mach_info generic_stn_320x240 = {
        .modes          = &generic_stn_320x240_mode,
        .num_modes      = 1,
-        .lccr0          = 0,
+        .lcd_conn       = LCD_COLOR_STN_8BPP | LCD_PCLK_EDGE_FALL |\
-        .lccr3          = (LCCR3_PixClkDiv(0x03) |
+                          LCD_AC_BIAS_FREQ(0xff),
-                           LCCR3_Acb(0xff) |
-                           LCCR3_PCP),
        .cmap_inverse   = 0,
        .cmap_static    = 0,
 };
@@ -236,10 +234,8 @@ static struct pxafb_mode_info generic_tft_640x480_mode = {
 static struct pxafb_mach_info generic_tft_640x480 = {
        .modes          = &generic_tft_640x480_mode,
        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
+        .lcd_conn       = LCD_COLOR_TFT_8BPP | LCD_PCLK_EDGE_FALL |\
-        .lccr3          = (LCCR3_PixClkDiv(0x01) |
+                          LCD_AC_BIAS_FREQ(0xff),
-                           LCCR3_Acb(0xff) |
-                           LCCR3_PCP),
        .cmap_inverse   = 0,
        .cmap_static    = 0,
 };
@@ -263,9 +259,7 @@ static struct pxafb_mode_info generic_crt_640x480_mode = {
 static struct pxafb_mach_info generic_crt_640x480 = {
        .modes          = &generic_crt_640x480_mode,
        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
+        .lcd_conn       = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
-        .lccr3          = (LCCR3_PixClkDiv(0x01) |
-                           LCCR3_Acb(0xff)),
        .cmap_inverse   = 0,
        .cmap_static    = 0,
 };
@@ -289,9 +283,7 @@ static struct pxafb_mode_info generic_crt_800x600_mode = {
 static struct pxafb_mach_info generic_crt_800x600 = {
        .modes          = &generic_crt_800x600_mode,
        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
+        .lcd_conn       = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
-        .lccr3          = (LCCR3_PixClkDiv(0x02) |
-                           LCCR3_Acb(0xff)),
        .cmap_inverse   = 0,
        .cmap_static    = 0,
 };
@@ -314,10 +306,7 @@ static struct pxafb_mode_info generic_tft_320x240_mode = {
 static struct pxafb_mach_info generic_tft_320x240 = {
        .modes          = &generic_tft_320x240_mode,
        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
+        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_AC_BIAS_FREQ(0xff),
-        .lccr3          = (LCCR3_PixClkDiv(0x06) |
-                           LCCR3_Acb(0xff) |
-                           LCCR3_PCP),
        .cmap_inverse   = 0,
        .cmap_static    = 0,
 };
@@ -341,9 +330,7 @@ static struct pxafb_mode_info generic_stn_640x480_mode = {
 static struct pxafb_mach_info generic_stn_640x480 = {
        .modes          = &generic_stn_640x480_mode,
        .num_modes      = 1,
-        .lccr0          = 0,
+        .lcd_conn       = LCD_COLOR_STN_8BPP | LCD_AC_BIAS_FREQ(0xff),
-        .lccr3          = (LCCR3_PixClkDiv(0x02) |
-                           LCCR3_Acb(0xff)),
        .cmap_inverse   = 0,
        .cmap_static    = 0,
 };
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index deb46cd144bf..ff0c577cd1ac 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -31,7 +31,6 @@
 #include <mach/mfp-pxa300.h>
 #include <mach/hardware.h>
-#include <mach/gpio.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
@@ -137,6 +136,10 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
        GPIO82_GPIO | MFP_PULL_HIGH,    /* MMC CD */
        GPIO85_GPIO,                    /* MMC WP */
        GPIO99_GPIO,                    /* Ethernet IRQ */
+        /* Standard I2C */
+        GPIO21_I2C_SCL,
+        GPIO22_I2C_SDA,
 };
 #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 65558d6aa220..c5e28a46b292 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -19,6 +19,7 @@
 #include <linux/fs.h>
 #include <linux/interrupt.h>
 #include <linux/mmc/host.h>
+#include <linux/mtd/physmap.h>
 #include <linux/pm.h>
 #include <linux/gpio.h>
 #include <linux/backlight.h>
@@ -541,11 +542,42 @@ err_free_1:
 static inline void corgi_init_spi(void) {}
 #endif
+static struct mtd_partition sharpsl_rom_parts[] = {
+        {
+                .name   ="Boot PROM Filesystem",
+                .offset = 0x00120000,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data sharpsl_rom_data = {
+        .width          = 2,
+        .nr_parts       = ARRAY_SIZE(sharpsl_rom_parts),
+        .parts          = sharpsl_rom_parts,
+};
+static struct resource sharpsl_rom_resources[] = {
+        {
+                .start  = 0x00000000,
+                .end    = 0x007fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device sharpsl_rom_device = {
+        .name   = "physmap-flash",
+        .id     = -1,
+        .resource = sharpsl_rom_resources,
+        .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
+        .dev.platform_data = &sharpsl_rom_data,
+};
 static struct platform_device *devices[] __initdata = {
        &corgiscoop_device,
        &corgifb_device,
        &corgikbd_device,
        &corgiled_device,
+        &sharpsl_rom_device,
 };
 static void corgi_poweroff(void)
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 1f272ea83f36..771dd4eac935 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -64,7 +64,7 @@ typedef struct {
 /* Define the refresh period in mSec for the SDRAM and the number of rows */
 #define SDRAM_TREF      64      /* standard 64ms SDRAM */
-#define SDRAM_ROWS      4096    /* 64MB=8192 32MB=4096 */
+static unsigned int sdram_rows;
 #define CCLKCFG_TURBO           0x1
 #define CCLKCFG_FCS             0x2
@@ -73,6 +73,9 @@ typedef struct {
 #define MDREFR_DB2_MASK         (MDREFR_K2DB2 | MDREFR_K1DB2)
 #define MDREFR_DRI_MASK         0xFFF
+#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
+#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
 /*
 * PXA255 definitions
 */
@@ -109,6 +112,10 @@ static struct cpufreq_frequency_table
 static struct cpufreq_frequency_table
        pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
+static unsigned int pxa255_turbo_table;
+module_param(pxa255_turbo_table, uint, 0);
+MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
 /*
 * PXA270 definitions
 *
@@ -158,22 +165,16 @@ static struct cpufreq_frequency_table
 extern unsigned get_clk_frequency_khz(int info);
-static void find_freq_tables(struct cpufreq_policy *policy,
+static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
-                             struct cpufreq_frequency_table **freq_table,
                             pxa_freqs_t **pxa_freqs)
 {
        if (cpu_is_pxa25x()) {
-                if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
+                if (!pxa255_turbo_table) {
                        *pxa_freqs = pxa255_run_freqs;
                        *freq_table = pxa255_run_freq_table;
-                } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
+                } else {
                        *pxa_freqs = pxa255_turbo_freqs;
                        *freq_table = pxa255_turbo_freq_table;
-                } else {
-                        printk("CPU PXA: Unknown policy found. "
-                               "Using CPUFREQ_POLICY_PERFORMANCE\n");
-                        *pxa_freqs = pxa255_run_freqs;
-                        *freq_table = pxa255_run_freq_table;
                }
        }
        if (cpu_is_pxa27x()) {
@@ -194,14 +195,28 @@ static void pxa27x_guess_max_freq(void)
        }
 }
+static void init_sdram_rows(void)
+{
+        uint32_t mdcnfg = MDCNFG;
+        unsigned int drac2 = 0, drac0 = 0;
+        if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
+                drac2 = MDCNFG_DRAC2(mdcnfg);
+        if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
+                drac0 = MDCNFG_DRAC0(mdcnfg);
+        sdram_rows = 1 << (11 + max(drac0, drac2));
+}
 static u32 mdrefr_dri(unsigned int freq)
 {
        u32 dri = 0;
        if (cpu_is_pxa25x())
-                dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
+                dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
        if (cpu_is_pxa27x())
-                dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
+                dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
        return dri;
 }
@@ -212,7 +227,7 @@ static int pxa_verify_policy(struct cpufreq_policy *policy)
        pxa_freqs_t *pxa_freqs;
        int ret;
-        find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs);
+        find_freq_tables(&pxa_freqs_table, &pxa_freqs);
        ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
        if (freq_debug)
@@ -240,7 +255,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
        unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
        /* Get the current policy */
-        find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings);
+        find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
        /* Lookup the next frequency */
        if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
@@ -329,11 +344,15 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
 {
        int i;
        unsigned int freq;
+        struct cpufreq_frequency_table *pxa255_freq_table;
+        pxa_freqs_t *pxa255_freqs;
        /* try to guess pxa27x cpu */
        if (cpu_is_pxa27x())
                pxa27x_guess_max_freq();
+        init_sdram_rows();
        /* set default policy and cpuinfo */
        policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
        policy->cur = get_clk_frequency_khz(0);    /* current freq */
@@ -354,6 +373,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
        }
        pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
+        pxa255_turbo_table = !!pxa255_turbo_table;
        /* Generate the pxa27x cpufreq_frequency_table struct */
        for (i = 0; i < NUM_PXA27x_FREQS; i++) {
                freq = pxa27x_freqs[i].khz;
@@ -368,8 +389,12 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
         * Set the policy's minimum and maximum frequencies from the tables
         * just constructed.  This sets cpuinfo.mxx_freq, min and max.
         */
-        if (cpu_is_pxa25x())
+        if (cpu_is_pxa25x()) {
-                cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table);
+                find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
+                pr_info("PXA255 cpufreq using %s frequency table\n",
+                        pxa255_turbo_table ? "turbo" : "run");
+                cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
+        }
        else if (cpu_is_pxa27x())
                cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 35736fc08634..e16f8e3d58d3 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,13 +4,12 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <mach/gpio.h>
+#include <mach/pxa-regs.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/i2c.h>
-#include <mach/mfp-pxa27x.h>
 #include <mach/ohci.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
@@ -156,8 +155,8 @@ void __init set_pxa_fb_parent(struct device *parent_dev)
 static struct resource pxa_resource_ffuart[] = {
        {
-                .start  = __PREG(FFUART),
+                .start  = 0x40100000,
-                .end    = __PREG(FFUART) + 35,
+                .end    = 0x40100023,
                .flags  = IORESOURCE_MEM,
        }, {
                .start  = IRQ_FFUART,
@@ -175,8 +174,8 @@ struct platform_device pxa_device_ffuart= {
 static struct resource pxa_resource_btuart[] = {
        {
-                .start  = __PREG(BTUART),
+                .start  = 0x40200000,
-                .end    = __PREG(BTUART) + 35,
+                .end    = 0x40200023,
                .flags  = IORESOURCE_MEM,
        }, {
                .start  = IRQ_BTUART,
@@ -194,8 +193,8 @@ struct platform_device pxa_device_btuart = {
 static struct resource pxa_resource_stuart[] = {
        {
-                .start  = __PREG(STUART),
+                .start  = 0x40700000,
-                .end    = __PREG(STUART) + 35,
+                .end    = 0x40700023,
                .flags  = IORESOURCE_MEM,
        }, {
                .start  = IRQ_STUART,
@@ -213,8 +212,8 @@ struct platform_device pxa_device_stuart = {
 static struct resource pxa_resource_hwuart[] = {
        {
-                .start  = __PREG(HWUART),
+                .start  = 0x41600000,
-                .end    = __PREG(HWUART) + 47,
+                .end    = 0x4160002F,
                .flags  = IORESOURCE_MEM,
        }, {
                .start  = IRQ_HWUART,
@@ -249,18 +248,53 @@ struct platform_device pxa_device_i2c = {
        .num_resources  = ARRAY_SIZE(pxai2c_resources),
 };
-static unsigned long pxa27x_i2c_mfp_cfg[] = {
-        GPIO117_I2C_SCL,
-        GPIO118_I2C_SDA,
-};
 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
 {
-        if (cpu_is_pxa27x())
-                pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
        pxa_register_device(&pxa_device_i2c, info);
 }
+#ifdef CONFIG_PXA27x
+static struct resource pxa27x_resources_i2c_power[] = {
+        {
+                .start  = 0x40f00180,
+                .end    = 0x40f001a3,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PWRI2C,
+                .end    = IRQ_PWRI2C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa27x_device_i2c_power = {
+        .name           = "pxa2xx-i2c",
+        .id             = 1,
+        .resource       = pxa27x_resources_i2c_power,
+        .num_resources  = ARRAY_SIZE(pxa27x_resources_i2c_power),
+};
+#endif
+#ifdef CONFIG_PXA3xx
+static struct resource pxa3xx_resources_i2c_power[] = {
+        {
+                .start  = 0x40f500c0,
+                .end    = 0x40f500d3,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PWRI2C,
+                .end    = IRQ_PWRI2C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa3xx_device_i2c_power = {
+        .name           = "pxa2xx-i2c",
+        .id             = 1,
+        .resource       = pxa3xx_resources_i2c_power,
+        .num_resources  = ARRAY_SIZE(pxa3xx_resources_i2c_power),
+};
+#endif
 static struct resource pxai2s_resources[] = {
        {
                .start  = 0x40400000,
@@ -296,11 +330,36 @@ void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
        pxa_register_device(&pxa_device_ficp, info);
 }
-struct platform_device pxa_device_rtc = {
+static struct resource pxa_rtc_resources[] = {
+        [0] = {
+                .start  = 0x40900000,
+                .end    = 0x40900000 + 0x3b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_RTC1Hz,
+                .end    = IRQ_RTC1Hz,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_RTCAlrm,
+                .end    = IRQ_RTCAlrm,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device sa1100_device_rtc = {
        .name           = "sa1100-rtc",
        .id             = -1,
 };
+struct platform_device pxa_device_rtc = {
+        .name           = "pxa-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_rtc_resources),
+        .resource       = pxa_rtc_resources,
+};
 static struct resource pxa_ac97_resources[] = {
        [0] = {
                .start  = 0x40500000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index bb04af4b0aa3..ecc24a4dca6d 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -11,6 +11,7 @@ extern struct platform_device pxa_device_hwuart;
 extern struct platform_device pxa_device_i2c;
 extern struct platform_device pxa_device_i2s;
 extern struct platform_device pxa_device_ficp;
+extern struct platform_device sa1100_device_rtc;
 extern struct platform_device pxa_device_rtc;
 extern struct platform_device pxa_device_ac97;
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c
index c0be17e0ab82..b1514fb20d3a 100644
--- a/arch/arm/mach-pxa/dma.c
+++ b/arch/arm/mach-pxa/dma.c
@@ -21,7 +21,7 @@
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
-#include <asm/dma.h>
+#include <mach/dma.h>
 #include <mach/pxa-regs.h>
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c
index d488eded2058..1bd7f740427c 100644
--- a/arch/arm/mach-pxa/e330.c
+++ b/arch/arm/mach-pxa/e330.c
@@ -1,5 +1,5 @@
 /*
- * Hardware definitions for the Toshiba eseries PDAs
+ * Hardware definitions for the Toshiba e330 PDAs
 *
 * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
 *
@@ -12,6 +12,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/tc6387xb.h>
 #include <asm/setup.h>
 #include <asm/mach/arch.h>
@@ -19,13 +22,44 @@
 #include <mach/mfp-pxa25x.h>
 #include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 #include "generic.h"
 #include "eseries.h"
+#include "clock.h"
+/* -------------------- e330 tc6387xb parameters -------------------- */
+static struct tc6387xb_platform_data e330_tc6387xb_info = {
+        .enable   = &eseries_tmio_enable,
+        .disable  = &eseries_tmio_disable,
+        .suspend  = &eseries_tmio_suspend,
+        .resume   = &eseries_tmio_resume,
+};
+static struct platform_device e330_tc6387xb_device = {
+        .name           = "tc6387xb",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &e330_tc6387xb_info,
+        },
+        .num_resources = 2,
+        .resource      = eseries_tmio_resources,
+};
+/* --------------------------------------------------------------- */
+static struct platform_device *devices[] __initdata = {
+        &e330_tc6387xb_device,
+};
 static void __init e330_init(void)
 {
+        eseries_register_clks();
+        eseries_get_tmio_gpios();
+        platform_add_devices(devices, ARRAY_SIZE(devices));
        pxa_set_udc_info(&e7xx_udc_mach_info);
 }
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c
index 8ecbc5479828..251129391d7d 100644
--- a/arch/arm/mach-pxa/e350.c
+++ b/arch/arm/mach-pxa/e350.c
@@ -1,5 +1,5 @@
 /*
- * Hardware definitions for the Toshiba eseries PDAs
+ * Hardware definitions for the Toshiba e350 PDAs
 *
 * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
 *
@@ -12,20 +12,54 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/t7l66xb.h>
 #include <asm/setup.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/pxa-regs.h>
 #include <mach/hardware.h>
+#include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 #include "generic.h"
 #include "eseries.h"
+#include "clock.h"
+/* -------------------- e350 t7l66xb parameters -------------------- */
+static struct t7l66xb_platform_data e350_t7l66xb_info = {
+        .irq_base               = IRQ_BOARD_START,
+        .enable                 = &eseries_tmio_enable,
+        .suspend                = &eseries_tmio_suspend,
+        .resume                 = &eseries_tmio_resume,
+};
+static struct platform_device e350_t7l66xb_device = {
+        .name           = "t7l66xb",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &e350_t7l66xb_info,
+        },
+        .num_resources = 2,
+        .resource      = eseries_tmio_resources,
+};
+/* ---------------------------------------------------------- */
+static struct platform_device *devices[] __initdata = {
+        &e350_t7l66xb_device,
+};
 static void __init e350_init(void)
 {
+        eseries_register_clks();
+        eseries_get_tmio_gpios();
+        platform_add_devices(devices, ARRAY_SIZE(devices));
        pxa_set_udc_info(&e7xx_udc_mach_info);
 }
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c
index 544bbaa20621..bed0336aca3d 100644
--- a/arch/arm/mach-pxa/e400.c
+++ b/arch/arm/mach-pxa/e400.c
@@ -12,20 +12,26 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/t7l66xb.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
 #include <asm/setup.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-#include <mach/pxa-regs.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/pxa-regs.h>
 #include <mach/hardware.h>
+#include <mach/eseries-gpio.h>
 #include <mach/pxafb.h>
 #include <mach/udc.h>
 #include "generic.h"
 #include "eseries.h"
+#include "clock.h"
 /* ------------------------ E400 LCD definitions ------------------------ */
@@ -46,7 +52,7 @@ static struct pxafb_mode_info e400_pxafb_mode_info = {
 static struct pxafb_mach_info e400_pxafb_mach_info = {
        .modes          = &e400_pxafb_mode_info,
        .num_modes      = 1,
-        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lcd_conn       = LCD_COLOR_TFT_16BPP,
        .lccr3          = 0,
        .pxafb_backlight_power  = NULL,
 };
@@ -65,7 +71,10 @@ static unsigned long e400_pin_config[] __initdata = {
        GPIO42_BTUART_RXD,
        GPIO43_BTUART_TXD,
        GPIO44_BTUART_CTS,
-        GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
+        /* TMIO controller */
+        GPIO19_GPIO, /* t7l66xb #PCLR */
+        GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
        /* wakeup */
        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
@@ -73,10 +82,60 @@ static unsigned long e400_pin_config[] __initdata = {
 /* ---------------------------------------------------------------------- */
+static struct mtd_partition partition_a = {
+        .name = "Internal NAND flash",
+        .offset =  0,
+        .size =  MTDPART_SIZ_FULL,
+};
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+static struct nand_bbt_descr e400_t7l66xb_nand_bbt = {
+        .options = 0,
+        .offs = 4,
+        .len = 2,
+        .pattern = scan_ff_pattern
+};
+static struct tmio_nand_data e400_t7l66xb_nand_config = {
+        .num_partitions = 1,
+        .partition = &partition_a,
+        .badblock_pattern = &e400_t7l66xb_nand_bbt,
+};
+static struct t7l66xb_platform_data e400_t7l66xb_info = {
+        .irq_base               = IRQ_BOARD_START,
+        .enable                 = &eseries_tmio_enable,
+        .suspend                = &eseries_tmio_suspend,
+        .resume                 = &eseries_tmio_resume,
+        .nand_data              = &e400_t7l66xb_nand_config,
+};
+static struct platform_device e400_t7l66xb_device = {
+        .name           = "t7l66xb",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &e400_t7l66xb_info,
+        },
+        .num_resources = 2,
+        .resource      = eseries_tmio_resources,
+};
+/* ---------------------------------------------------------- */
+static struct platform_device *devices[] __initdata = {
+        &e400_t7l66xb_device,
+};
 static void __init e400_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
+        /* Fixme - e400 may have a switched clock */
+        eseries_register_clks();
+        eseries_get_tmio_gpios();
        set_pxa_fb_info(&e400_pxafb_mach_info);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
        pxa_set_udc_info(&e7xx_udc_mach_info);
 }
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
index c57a15b37f0d..b00d670b2ea6 100644
--- a/arch/arm/mach-pxa/e740.c
+++ b/arch/arm/mach-pxa/e740.c
@@ -15,6 +15,8 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/fb.h>
+#include <linux/clk.h>
+#include <linux/mfd/t7l66xb.h>
 #include <video/w100fb.h>
@@ -23,12 +25,16 @@
 #include <asm/mach-types.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/pxa-regs.h>
 #include <mach/hardware.h>
+#include <mach/eseries-gpio.h>
 #include <mach/udc.h>
+#include <mach/irda.h>
 #include "generic.h"
 #include "eseries.h"
+#include "clock.h"
+#include "devices.h"
 /* ------------------------ e740 video support --------------------------- */
@@ -116,7 +122,17 @@ static unsigned long e740_pin_config[] __initdata = {
        GPIO42_BTUART_RXD,
        GPIO43_BTUART_TXD,
        GPIO44_BTUART_CTS,
-        GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
+        /* TMIO controller */
+        GPIO19_GPIO, /* t7l66xb #PCLR */
+        GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
+        /* UDC */
+        GPIO13_GPIO,
+        GPIO3_GPIO,
+        /* IrDA */
+        GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
        /* PC Card */
        GPIO8_GPIO,   /* CD0 */
@@ -142,17 +158,43 @@ static unsigned long e740_pin_config[] __initdata = {
        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
 };
+/* -------------------- e740 t7l66xb parameters -------------------- */
+static struct t7l66xb_platform_data e740_t7l66xb_info = {
+        .irq_base               = IRQ_BOARD_START,
+        .enable                 = &eseries_tmio_enable,
+        .suspend                = &eseries_tmio_suspend,
+        .resume                 = &eseries_tmio_resume,
+};
+static struct platform_device e740_t7l66xb_device = {
+        .name           = "t7l66xb",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &e740_t7l66xb_info,
+        },
+        .num_resources = 2,
+        .resource      = eseries_tmio_resources,
+};
 /* ----------------------------------------------------------------------- */
 static struct platform_device *devices[] __initdata = {
        &e740_fb_device,
+        &e740_t7l66xb_device,
 };
 static void __init e740_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
+        eseries_register_clks();
+        clk_add_alias("CLK_CK48M", &e740_t7l66xb_device.dev,
+                        "UDCCLK", &pxa25x_device_udc.dev),
+        eseries_get_tmio_gpios();
        platform_add_devices(devices, ARRAY_SIZE(devices));
        pxa_set_udc_info(&e7xx_udc_mach_info);
+        e7xx_irda_init();
+        pxa_set_ficp_info(&e7xx_ficp_platform_data);
 }
 MACHINE_START(E740, "Toshiba e740")
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c
index 640e738b85df..84d7c1aac58d 100644
--- a/arch/arm/mach-pxa/e750.c
+++ b/arch/arm/mach-pxa/e750.c
@@ -15,6 +15,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/fb.h>
+#include <linux/mfd/tc6393xb.h>
 #include <video/w100fb.h>
@@ -23,11 +24,15 @@
 #include <asm/mach-types.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/pxa-regs.h>
 #include <mach/hardware.h>
+#include <mach/eseries-gpio.h>
 #include <mach/udc.h>
+#include <mach/irda.h>
 #include "generic.h"
 #include "eseries.h"
+#include "clock.h"
 /* ---------------------- E750 LCD definitions -------------------- */
@@ -100,16 +105,45 @@ static struct platform_device e750_fb_device = {
        .resource       = e750_fb_resources,
 };
-/* ----------------------------------------------------------------------- */
+/* ----------------- e750 tc6393xb parameters ------------------ */
+static struct tc6393xb_platform_data e750_tc6393xb_info = {
+        .irq_base       = IRQ_BOARD_START,
+        .scr_pll2cr     = 0x0cc1,
+        .scr_gper       = 0,
+        .gpio_base      = -1,
+        .suspend        = &eseries_tmio_suspend,
+        .resume         = &eseries_tmio_resume,
+        .enable         = &eseries_tmio_enable,
+        .disable        = &eseries_tmio_disable,
+};
+static struct platform_device e750_tc6393xb_device = {
+        .name           = "tc6393xb",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &e750_tc6393xb_info,
+        },
+        .num_resources = 2,
+        .resource      = eseries_tmio_resources,
+};
+/* ------------------------------------------------------------- */
 static struct platform_device *devices[] __initdata = {
        &e750_fb_device,
+        &e750_tc6393xb_device,
 };
 static void __init e750_init(void)
 {
+        clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev,
+                        "GPIO11_CLK", NULL),
+        eseries_get_tmio_gpios();
        platform_add_devices(devices, ARRAY_SIZE(devices));
        pxa_set_udc_info(&e7xx_udc_mach_info);
+        e7xx_irda_init();
+        pxa_set_ficp_info(&e7xx_ficp_platform_data);
 }
 MACHINE_START(E750, "Toshiba e750")
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c
index a293e09bfe25..9a86a426f924 100644
--- a/arch/arm/mach-pxa/e800.c
+++ b/arch/arm/mach-pxa/e800.c
@@ -15,6 +15,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/fb.h>
+#include <linux/mfd/tc6393xb.h>
 #include <video/w100fb.h>
@@ -23,12 +24,14 @@
 #include <asm/mach-types.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/pxa-regs.h>
 #include <mach/hardware.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 #include "generic.h"
 #include "eseries.h"
+#include "clock.h"
 /* ------------------------ e800 LCD definitions ------------------------- */
@@ -160,14 +163,41 @@ static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
        .gpio_pullup_inverted = 1
 };
+/* ----------------- e800 tc6393xb parameters ------------------ */
+static struct tc6393xb_platform_data e800_tc6393xb_info = {
+        .irq_base       = IRQ_BOARD_START,
+        .scr_pll2cr     = 0x0cc1,
+        .scr_gper       = 0,
+        .gpio_base      = -1,
+        .suspend        = &eseries_tmio_suspend,
+        .resume         = &eseries_tmio_resume,
+        .enable         = &eseries_tmio_enable,
+        .disable        = &eseries_tmio_disable,
+};
+static struct platform_device e800_tc6393xb_device = {
+        .name           = "tc6393xb",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &e800_tc6393xb_info,
+        },
+        .num_resources = 2,
+        .resource      = eseries_tmio_resources,
+};
 /* ----------------------------------------------------------------------- */
 static struct platform_device *devices[] __initdata = {
        &e800_fb_device,
+        &e800_tc6393xb_device,
 };
 static void __init e800_init(void)
 {
+        clk_add_alias("CLK_CK3P6MI", &e800_tc6393xb_device.dev,
+                        "GPIO11_CLK", NULL),
+        eseries_get_tmio_gpios();
        platform_add_devices(devices, ARRAY_SIZE(devices));
        pxa_set_udc_info(&e800_udc_mach_info);
 }
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index d28849b50a14..dfce7d5b659e 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -12,6 +12,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
 #include <asm/setup.h>
 #include <asm/mach/arch.h>
@@ -21,8 +24,10 @@
 #include <mach/hardware.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
+#include <mach/irda.h>
 #include "generic.h"
+#include "clock.h"
 /* Only e800 has 128MB RAM */
 void __init eseries_fixup(struct machine_desc *desc,
@@ -43,3 +48,122 @@ struct pxa2xx_udc_mach_info e7xx_udc_mach_info = {
        .gpio_pullup_inverted = 1
 };
+static void e7xx_irda_transceiver_mode(struct device *dev, int mode)
+{
+        if (mode & IR_OFF) {
+                gpio_set_value(GPIO_E7XX_IR_OFF, 1);
+                pxa2xx_transceiver_mode(dev, mode);
+        } else {
+                pxa2xx_transceiver_mode(dev, mode);
+                gpio_set_value(GPIO_E7XX_IR_OFF, 0);
+        }
+}
+int e7xx_irda_init(void)
+{
+        int ret;
+        ret = gpio_request(GPIO_E7XX_IR_OFF, "IrDA power");
+        if (ret)
+                goto out;
+        ret = gpio_direction_output(GPIO_E7XX_IR_OFF, 0);
+        if (ret)
+                goto out;
+        e7xx_irda_transceiver_mode(NULL, IR_SIRMODE | IR_OFF);
+out:
+        return ret;
+}
+static void e7xx_irda_shutdown(struct device *dev)
+{
+        e7xx_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF);
+        gpio_free(GPIO_E7XX_IR_OFF);
+}
+struct pxaficp_platform_data e7xx_ficp_platform_data = {
+        .transceiver_cap  = IR_SIRMODE | IR_OFF,
+        .transceiver_mode = e7xx_irda_transceiver_mode,
+        .shutdown = e7xx_irda_shutdown,
+};
+int eseries_tmio_enable(struct platform_device *dev)
+{
+        /* Reset - bring SUSPEND high before PCLR */
+        gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
+        gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0);
+        msleep(1);
+        gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1);
+        msleep(1);
+        gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 1);
+        msleep(1);
+        return 0;
+}
+int eseries_tmio_disable(struct platform_device *dev)
+{
+        gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
+        gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0);
+        return 0;
+}
+int eseries_tmio_suspend(struct platform_device *dev)
+{
+        gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
+        return 0;
+}
+int eseries_tmio_resume(struct platform_device *dev)
+{
+        gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1);
+        msleep(1);
+        return 0;
+}
+void eseries_get_tmio_gpios(void)
+{
+        gpio_request(GPIO_ESERIES_TMIO_SUSPEND, NULL);
+        gpio_request(GPIO_ESERIES_TMIO_PCLR, NULL);
+        gpio_direction_output(GPIO_ESERIES_TMIO_SUSPEND, 0);
+        gpio_direction_output(GPIO_ESERIES_TMIO_PCLR, 0);
+}
+/* TMIO controller uses the same resources on all e-series machines. */
+struct resource eseries_tmio_resources[] = {
+        [0] = {
+                .start  = PXA_CS4_PHYS,
+                .end    = PXA_CS4_PHYS + 0x1fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ),
+                .end    = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+/* Some e-series hardware cannot control the 32K clock */
+static void clk_32k_dummy(struct clk *clk)
+{
+}
+static const struct clkops clk_32k_dummy_ops = {
+        .enable         = clk_32k_dummy,
+        .disable        = clk_32k_dummy,
+};
+static struct clk tmio_dummy_clk = {
+        .ops    = &clk_32k_dummy_ops,
+        .rate   = 32768,
+};
+static struct clk_lookup eseries_clkregs[] = {
+        INIT_CLKREG(&tmio_dummy_clk, NULL, "CLK_CK32K"),
+};
+void eseries_register_clks(void)
+{
+        clks_register(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
+}
diff --git a/arch/arm/mach-pxa/eseries.h b/arch/arm/mach-pxa/eseries.h
index a83f88d4b6ad..5930f5e2a123 100644
--- a/arch/arm/mach-pxa/eseries.h
+++ b/arch/arm/mach-pxa/eseries.h
@@ -2,3 +2,15 @@ void __init eseries_fixup(struct machine_desc *desc,
        struct tag *tags, char **cmdline, struct meminfo *mi);
 extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info;
+extern struct pxaficp_platform_data e7xx_ficp_platform_data;
+extern int e7xx_irda_init(void);
+extern int eseries_tmio_enable(struct platform_device *dev);
+extern int eseries_tmio_disable(struct platform_device *dev);
+extern int eseries_tmio_suspend(struct platform_device *dev);
+extern int eseries_tmio_resume(struct platform_device *dev);
+extern void eseries_get_tmio_gpios(void);
+extern struct resource eseries_tmio_resources[];
+extern struct platform_device e300_tc6387xb_device;
+extern void eseries_register_clks(void);
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index cc3d850cc0b6..df5f822f3b6c 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -16,11 +16,14 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/pwm_backlight.h>
+#include <linux/input.h>
 #include <asm/setup.h>
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/i2c.h>
+#include <mach/hardware.h>
+#include <mach/pxa27x_keypad.h>
 #include <mach/mfp-pxa27x.h>
 #include <mach/pxa-regs.h>
@@ -101,120 +104,732 @@ static unsigned long ezx_pin_config[] __initdata = {
        GPIO44_BTUART_CTS,
        GPIO45_BTUART_RTS,
-        /* STUART */
+        /* I2C */
-        GPIO46_STUART_RXD,
+        GPIO117_I2C_SCL,
-        GPIO47_STUART_TXD,
+        GPIO118_I2C_SDA,
-        /* For A780 support (connected with Neptune GSM chip) */
+        /* PCAP SSP */
-        GPIO30_USB_P3_2,        /* ICL_TXENB */
+        GPIO29_SSP1_SCLK,
-        GPIO31_USB_P3_6,        /* ICL_VPOUT */
+        GPIO25_SSP1_TXD,
-        GPIO90_USB_P3_5,        /* ICL_VPIN */
+        GPIO26_SSP1_RXD,
-        GPIO91_USB_P3_1,        /* ICL_XRXD */
+        GPIO24_GPIO,                            /* pcap chip select */
-        GPIO56_USB_P3_4,        /* ICL_VMOUT */
+        GPIO1_GPIO,                             /* pcap interrupt */
-        GPIO113_USB_P3_3,       /* /ICL_VMIN */
+        GPIO4_GPIO,                             /* WDI_AP */
+        GPIO55_GPIO,                            /* SYS_RESTART */
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO11_GPIO,                            /* mmc detect */
+        /* usb to external transceiver */
+        GPIO34_USB_P2_2,
+        GPIO35_USB_P2_1,
+        GPIO36_USB_P2_4,
+        GPIO39_USB_P2_6,
+        GPIO40_USB_P2_5,
+        GPIO53_USB_P2_3,
+        /* usb to Neptune GSM chip */
+        GPIO30_USB_P3_2,
+        GPIO31_USB_P3_6,
+        GPIO90_USB_P3_5,
+        GPIO91_USB_P3_1,
+        GPIO56_USB_P3_4,
+        GPIO113_USB_P3_3,
+};
+#if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_E680)
+static unsigned long gen1_pin_config[] __initdata = {
+        /* flip / lockswitch */
+        GPIO12_GPIO,
+        /* bluetooth (bcm2035) */
+        GPIO14_GPIO | WAKEUP_ON_LEVEL_HIGH,     /* HOSTWAKE */
+        GPIO48_GPIO,                            /* RESET */
+        GPIO28_GPIO,                            /* WAKEUP */
+        /* Neptune handshake */
+        GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH,      /* BP_RDY */
+        GPIO57_GPIO,                            /* AP_RDY */
+        GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH,     /* WDI */
+        GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH,      /* WDI2 */
+        GPIO82_GPIO,                            /* RESET */
+        GPIO99_GPIO,                            /* TC_MM_EN */
+        /* sound */
+        GPIO52_SSP3_SCLK,
+        GPIO83_SSP3_SFRM,
+        GPIO81_SSP3_TXD,
+        GPIO89_SSP3_RXD,
+        /* ssp2 pins to in */
+        GPIO22_GPIO,                            /* SSP2_SCLK */
+        GPIO37_GPIO,                            /* SSP2_SFRM */
+        GPIO38_GPIO,                            /* SSP2_TXD */
+        GPIO88_GPIO,                            /* SSP2_RXD */
+        /* camera */
+        GPIO23_CIF_MCLK,
+        GPIO54_CIF_PCLK,
+        GPIO85_CIF_LV,
+        GPIO84_CIF_FV,
+        GPIO27_CIF_DD_0,
+        GPIO114_CIF_DD_1,
+        GPIO51_CIF_DD_2,
+        GPIO115_CIF_DD_3,
+        GPIO95_CIF_DD_4,
+        GPIO94_CIF_DD_5,
+        GPIO17_CIF_DD_6,
+        GPIO108_CIF_DD_7,
+        GPIO50_GPIO,                            /* CAM_EN */
+        GPIO19_GPIO,                            /* CAM_RST */
+        /* EMU */
+        GPIO120_GPIO,                           /* EMU_MUX1 */
+        GPIO119_GPIO,                           /* EMU_MUX2 */
+        GPIO86_GPIO,                            /* SNP_INT_CTL */
+        GPIO87_GPIO,                            /* SNP_INT_IN */
+};
+#endif
+#if defined(CONFIG_MACH_EZX_A1200) || defined(CONFIG_MACH_EZX_A910) || \
+        defined(CONFIG_MACH_EZX_E2) || defined(CONFIG_MACH_EZX_E6)
+static unsigned long gen2_pin_config[] __initdata = {
+        /* flip / lockswitch */
+        GPIO15_GPIO,
+        /* EOC */
+        GPIO10_GPIO,
+        /* bluetooth (bcm2045) */
+        GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH,     /* HOSTWAKE */
+        GPIO37_GPIO,                            /* RESET */
+        GPIO57_GPIO,                            /* WAKEUP */
+        /* Neptune handshake */
+        GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH,      /* BP_RDY */
+        GPIO96_GPIO,                            /* AP_RDY */
+        GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH,      /* WDI */
+        GPIO116_GPIO,                           /* RESET */
+        GPIO41_GPIO,                            /* BP_FLASH */
+        /* sound */
+        GPIO52_SSP3_SCLK,
+        GPIO83_SSP3_SFRM,
+        GPIO81_SSP3_TXD,
+        GPIO82_SSP3_RXD,
+        /* ssp2 pins to in */
+        GPIO22_GPIO,                            /* SSP2_SCLK */
+        GPIO14_GPIO,                            /* SSP2_SFRM */
+        GPIO38_GPIO,                            /* SSP2_TXD */
+        GPIO88_GPIO,                            /* SSP2_RXD */
+        /* camera */
+        GPIO23_CIF_MCLK,
+        GPIO54_CIF_PCLK,
+        GPIO85_CIF_LV,
+        GPIO84_CIF_FV,
+        GPIO27_CIF_DD_0,
+        GPIO114_CIF_DD_1,
+        GPIO51_CIF_DD_2,
+        GPIO115_CIF_DD_3,
+        GPIO95_CIF_DD_4,
+        GPIO48_CIF_DD_5,
+        GPIO93_CIF_DD_6,
+        GPIO12_CIF_DD_7,
+        GPIO50_GPIO,                            /* CAM_EN */
+        GPIO28_GPIO,                            /* CAM_RST */
+        GPIO17_GPIO,                            /* CAM_FLASH */
+};
+#endif
+#ifdef CONFIG_MACH_EZX_A780
+static unsigned long a780_pin_config[] __initdata = {
+        /* keypad */
+        GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        /* attenuate sound */
+        GPIO96_GPIO,
+};
+#endif
+#ifdef CONFIG_MACH_EZX_E680
+static unsigned long e680_pin_config[] __initdata = {
+        /* keypad */
+        GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO96_KP_DKIN_3 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_DKIN_4 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_DKIN_5 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        /* MIDI */
+        GPIO79_GPIO,                            /* VA_SEL_BUL */
+        GPIO80_GPIO,                            /* FLT_SEL_BUL */
+        GPIO78_GPIO,                            /* MIDI_RESET */
+        GPIO33_GPIO,                            /* MIDI_CS */
+        GPIO15_GPIO,                            /* MIDI_IRQ */
+        GPIO49_GPIO,                            /* MIDI_NPWE */
+        GPIO18_GPIO,                            /* MIDI_RDY */
+        /* leds */
+        GPIO46_GPIO,
+        GPIO47_GPIO,
+};
+#endif
+#ifdef CONFIG_MACH_EZX_A1200
+static unsigned long a1200_pin_config[] __initdata = {
+        /* keypad */
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
+};
+#endif
+#ifdef CONFIG_MACH_EZX_A910
+static unsigned long a910_pin_config[] __initdata = {
+        /* keypad */
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
+        /* WLAN */
+        GPIO89_GPIO,                            /* RESET */
+        GPIO33_GPIO,                            /* WAKEUP */
+        GPIO94_GPIO | WAKEUP_ON_LEVEL_HIGH,     /* HOSTWAKE */
+        /* MMC CS */
+        GPIO20_GPIO,
+};
+#endif
+#ifdef CONFIG_MACH_EZX_E2
+static unsigned long e2_pin_config[] __initdata = {
+        /* keypad */
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
 };
+#endif
+#ifdef CONFIG_MACH_EZX_E6
+static unsigned long e6_pin_config[] __initdata = {
+        /* keypad */
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
+};
+#endif
+/* KEYPAD */
+#ifdef CONFIG_MACH_EZX_A780
+static unsigned int a780_key_map[] = {
+        KEY(0, 0, KEY_SEND),
+        KEY(0, 1, KEY_BACK),
+        KEY(0, 2, KEY_END),
+        KEY(0, 3, KEY_PAGEUP),
+        KEY(0, 4, KEY_UP),
+        KEY(1, 0, KEY_NUMERIC_1),
+        KEY(1, 1, KEY_NUMERIC_2),
+        KEY(1, 2, KEY_NUMERIC_3),
+        KEY(1, 3, KEY_SELECT),
+        KEY(1, 4, KEY_KPENTER),
+        KEY(2, 0, KEY_NUMERIC_4),
+        KEY(2, 1, KEY_NUMERIC_5),
+        KEY(2, 2, KEY_NUMERIC_6),
+        KEY(2, 3, KEY_RECORD),
+        KEY(2, 4, KEY_LEFT),
+        KEY(3, 0, KEY_NUMERIC_7),
+        KEY(3, 1, KEY_NUMERIC_8),
+        KEY(3, 2, KEY_NUMERIC_9),
+        KEY(3, 3, KEY_HOME),
+        KEY(3, 4, KEY_RIGHT),
+        KEY(4, 0, KEY_NUMERIC_STAR),
+        KEY(4, 1, KEY_NUMERIC_0),
+        KEY(4, 2, KEY_NUMERIC_POUND),
+        KEY(4, 3, KEY_PAGEDOWN),
+        KEY(4, 4, KEY_DOWN),
+};
+static struct pxa27x_keypad_platform_data a780_keypad_platform_data = {
+        .matrix_key_rows = 5,
+        .matrix_key_cols = 5,
+        .matrix_key_map = a780_key_map,
+        .matrix_key_map_size = ARRAY_SIZE(a780_key_map),
+        .direct_key_map = { KEY_CAMERA },
+        .direct_key_num = 1,
+        .debounce_interval = 30,
+};
+#endif /* CONFIG_MACH_EZX_A780 */
+#ifdef CONFIG_MACH_EZX_E680
+static unsigned int e680_key_map[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_RESERVED),
+        KEY(0, 3, KEY_SEND),
+        KEY(1, 0, KEY_DOWN),
+        KEY(1, 1, KEY_LEFT),
+        KEY(1, 2, KEY_PAGEUP),
+        KEY(1, 3, KEY_PAGEDOWN),
+        KEY(2, 0, KEY_RESERVED),
+        KEY(2, 1, KEY_RESERVED),
+        KEY(2, 2, KEY_RESERVED),
+        KEY(2, 3, KEY_KPENTER),
+};
+static struct pxa27x_keypad_platform_data e680_keypad_platform_data = {
+        .matrix_key_rows = 3,
+        .matrix_key_cols = 4,
+        .matrix_key_map = e680_key_map,
+        .matrix_key_map_size = ARRAY_SIZE(e680_key_map),
+        .direct_key_map = {
+                KEY_CAMERA,
+                KEY_RESERVED,
+                KEY_RESERVED,
+                KEY_F1,
+                KEY_CANCEL,
+                KEY_F2,
+        },
+        .direct_key_num = 6,
+        .debounce_interval = 30,
+};
+#endif /* CONFIG_MACH_EZX_E680 */
+#ifdef CONFIG_MACH_EZX_A1200
+static unsigned int a1200_key_map[] = {
+        KEY(0, 0, KEY_RESERVED),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_PAGEDOWN),
+        KEY(0, 3, KEY_RESERVED),
+        KEY(0, 4, KEY_RESERVED),
+        KEY(0, 5, KEY_RESERVED),
+        KEY(1, 0, KEY_RESERVED),
+        KEY(1, 1, KEY_DOWN),
+        KEY(1, 2, KEY_CAMERA),
+        KEY(1, 3, KEY_RESERVED),
+        KEY(1, 4, KEY_RESERVED),
+        KEY(1, 5, KEY_RESERVED),
+        KEY(2, 0, KEY_RESERVED),
+        KEY(2, 1, KEY_KPENTER),
+        KEY(2, 2, KEY_RECORD),
+        KEY(2, 3, KEY_RESERVED),
+        KEY(2, 4, KEY_RESERVED),
+        KEY(2, 5, KEY_SELECT),
+        KEY(3, 0, KEY_RESERVED),
+        KEY(3, 1, KEY_UP),
+        KEY(3, 2, KEY_SEND),
+        KEY(3, 3, KEY_RESERVED),
+        KEY(3, 4, KEY_RESERVED),
+        KEY(3, 5, KEY_RESERVED),
+        KEY(4, 0, KEY_RESERVED),
+        KEY(4, 1, KEY_LEFT),
+        KEY(4, 2, KEY_PAGEUP),
+        KEY(4, 3, KEY_RESERVED),
+        KEY(4, 4, KEY_RESERVED),
+        KEY(4, 5, KEY_RESERVED),
+};
+static struct pxa27x_keypad_platform_data a1200_keypad_platform_data = {
+        .matrix_key_rows = 5,
+        .matrix_key_cols = 6,
+        .matrix_key_map = a1200_key_map,
+        .matrix_key_map_size = ARRAY_SIZE(a1200_key_map),
+        .debounce_interval = 30,
+};
+#endif /* CONFIG_MACH_EZX_A1200 */
+#ifdef CONFIG_MACH_EZX_E6
+static unsigned int e6_key_map[] = {
+        KEY(0, 0, KEY_RESERVED),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_PAGEDOWN),
+        KEY(0, 3, KEY_RESERVED),
+        KEY(0, 4, KEY_RESERVED),
+        KEY(0, 5, KEY_NEXTSONG),
+        KEY(1, 0, KEY_RESERVED),
+        KEY(1, 1, KEY_DOWN),
+        KEY(1, 2, KEY_PROG1),
+        KEY(1, 3, KEY_RESERVED),
+        KEY(1, 4, KEY_RESERVED),
+        KEY(1, 5, KEY_RESERVED),
+        KEY(2, 0, KEY_RESERVED),
+        KEY(2, 1, KEY_ENTER),
+        KEY(2, 2, KEY_CAMERA),
+        KEY(2, 3, KEY_RESERVED),
+        KEY(2, 4, KEY_RESERVED),
+        KEY(2, 5, KEY_WWW),
+        KEY(3, 0, KEY_RESERVED),
+        KEY(3, 1, KEY_UP),
+        KEY(3, 2, KEY_SEND),
+        KEY(3, 3, KEY_RESERVED),
+        KEY(3, 4, KEY_RESERVED),
+        KEY(3, 5, KEY_PLAYPAUSE),
+        KEY(4, 0, KEY_RESERVED),
+        KEY(4, 1, KEY_LEFT),
+        KEY(4, 2, KEY_PAGEUP),
+        KEY(4, 3, KEY_RESERVED),
+        KEY(4, 4, KEY_RESERVED),
+        KEY(4, 5, KEY_PREVIOUSSONG),
+};
+static struct pxa27x_keypad_platform_data e6_keypad_platform_data = {
+        .matrix_key_rows = 5,
+        .matrix_key_cols = 6,
+        .matrix_key_map = e6_key_map,
+        .matrix_key_map_size = ARRAY_SIZE(e6_key_map),
-static void __init ezx_init(void)
+        .debounce_interval = 30,
+};
+#endif /* CONFIG_MACH_EZX_E6 */
+#ifdef CONFIG_MACH_EZX_A910
+static unsigned int a910_key_map[] = {
+        KEY(0, 0, KEY_NUMERIC_6),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_PAGEDOWN),
+        KEY(0, 3, KEY_KPENTER),
+        KEY(0, 4, KEY_NUMERIC_5),
+        KEY(0, 5, KEY_CAMERA),
+        KEY(1, 0, KEY_NUMERIC_8),
+        KEY(1, 1, KEY_DOWN),
+        KEY(1, 2, KEY_RESERVED),
+        KEY(1, 3, KEY_F1), /* Left SoftKey */
+        KEY(1, 4, KEY_NUMERIC_STAR),
+        KEY(1, 5, KEY_RESERVED),
+        KEY(2, 0, KEY_NUMERIC_7),
+        KEY(2, 1, KEY_NUMERIC_9),
+        KEY(2, 2, KEY_RECORD),
+        KEY(2, 3, KEY_F2), /* Right SoftKey */
+        KEY(2, 4, KEY_BACK),
+        KEY(2, 5, KEY_SELECT),
+        KEY(3, 0, KEY_NUMERIC_2),
+        KEY(3, 1, KEY_UP),
+        KEY(3, 2, KEY_SEND),
+        KEY(3, 3, KEY_NUMERIC_0),
+        KEY(3, 4, KEY_NUMERIC_1),
+        KEY(3, 5, KEY_RECORD),
+        KEY(4, 0, KEY_NUMERIC_4),
+        KEY(4, 1, KEY_LEFT),
+        KEY(4, 2, KEY_PAGEUP),
+        KEY(4, 3, KEY_NUMERIC_POUND),
+        KEY(4, 4, KEY_NUMERIC_3),
+        KEY(4, 5, KEY_RESERVED),
+};
+static struct pxa27x_keypad_platform_data a910_keypad_platform_data = {
+        .matrix_key_rows = 5,
+        .matrix_key_cols = 6,
+        .matrix_key_map = a910_key_map,
+        .matrix_key_map_size = ARRAY_SIZE(a910_key_map),
+        .debounce_interval = 30,
+};
+#endif /* CONFIG_MACH_EZX_A910 */
+#ifdef CONFIG_MACH_EZX_E2
+static unsigned int e2_key_map[] = {
+        KEY(0, 0, KEY_NUMERIC_6),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_NUMERIC_9),
+        KEY(0, 3, KEY_NEXTSONG),
+        KEY(0, 4, KEY_NUMERIC_5),
+        KEY(0, 5, KEY_F1), /* Left SoftKey */
+        KEY(1, 0, KEY_NUMERIC_8),
+        KEY(1, 1, KEY_DOWN),
+        KEY(1, 2, KEY_RESERVED),
+        KEY(1, 3, KEY_PAGEUP),
+        KEY(1, 4, KEY_NUMERIC_STAR),
+        KEY(1, 5, KEY_F2), /* Right SoftKey */
+        KEY(2, 0, KEY_NUMERIC_7),
+        KEY(2, 1, KEY_KPENTER),
+        KEY(2, 2, KEY_RECORD),
+        KEY(2, 3, KEY_PAGEDOWN),
+        KEY(2, 4, KEY_BACK),
+        KEY(2, 5, KEY_NUMERIC_0),
+        KEY(3, 0, KEY_NUMERIC_2),
+        KEY(3, 1, KEY_UP),
+        KEY(3, 2, KEY_SEND),
+        KEY(3, 3, KEY_PLAYPAUSE),
+        KEY(3, 4, KEY_NUMERIC_1),
+        KEY(3, 5, KEY_SOUND), /* Music SoftKey */
+        KEY(4, 0, KEY_NUMERIC_4),
+        KEY(4, 1, KEY_LEFT),
+        KEY(4, 2, KEY_NUMERIC_POUND),
+        KEY(4, 3, KEY_PREVIOUSSONG),
+        KEY(4, 4, KEY_NUMERIC_3),
+        KEY(4, 5, KEY_RESERVED),
+};
+static struct pxa27x_keypad_platform_data e2_keypad_platform_data = {
+        .matrix_key_rows = 5,
+        .matrix_key_cols = 6,
+        .matrix_key_map = e2_key_map,
+        .matrix_key_map_size = ARRAY_SIZE(e2_key_map),
+        .debounce_interval = 30,
+};
+#endif /* CONFIG_MACH_EZX_E2 */
+#ifdef CONFIG_MACH_EZX_A780
+static void __init a780_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config));
        pxa_set_i2c_info(NULL);
-        if (machine_is_ezx_a780() || machine_is_ezx_e680())
-                set_pxa_fb_info(&ezx_fb_info_1);
-        else
-                set_pxa_fb_info(&ezx_fb_info_2);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        set_pxa_fb_info(&ezx_fb_info_1);
-}
-static void __init ezx_fixup(struct machine_desc *desc, struct tag *tags,
+        pxa_set_keypad_info(&a780_keypad_platform_data);
-                char **cmdline, struct meminfo *mi)
-{
+        platform_add_devices(devices, ARRAY_SIZE(devices));
-        /* We have two ram chips. First one with 32MB at 0xA0000000 and a second
-         * 16MB one at 0xAC000000
-         */
-        mi->nr_banks = 2;
-        mi->bank[0].start = 0xa0000000;
-        mi->bank[0].node = 0;
-        mi->bank[0].size = (32*1024*1024);
-        mi->bank[1].start = 0xac000000;
-        mi->bank[1].node = 1;
-        mi->bank[1].size = (16*1024*1024);
 }
-#ifdef CONFIG_MACH_EZX_A780
 MACHINE_START(EZX_A780, "Motorola EZX A780")
        .phys_io        = 0x40000000,
        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .fixup                  = ezx_fixup,
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
-        .init_machine   = &ezx_init,
+        .init_machine   = a780_init,
 MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_E680
+static struct i2c_board_info __initdata e680_i2c_board_info[] = {
+        { I2C_BOARD_INFO("tea5767", 0x81) },
+};
+static void __init e680_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config));
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info));
+        set_pxa_fb_info(&ezx_fb_info_1);
+        pxa_set_keypad_info(&e680_keypad_platform_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
 MACHINE_START(EZX_E680, "Motorola EZX E680")
        .phys_io        = 0x40000000,
        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .fixup                  = ezx_fixup,
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
-        .init_machine   = &ezx_init,
+        .init_machine   = e680_init,
 MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_A1200
+static struct i2c_board_info __initdata a1200_i2c_board_info[] = {
+        { I2C_BOARD_INFO("tea5767", 0x81) },
+};
+static void __init a1200_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config));
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info));
+        set_pxa_fb_info(&ezx_fb_info_2);
+        pxa_set_keypad_info(&a1200_keypad_platform_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
 MACHINE_START(EZX_A1200, "Motorola EZX A1200")
        .phys_io        = 0x40000000,
        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .fixup                  = ezx_fixup,
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
-        .init_machine   = &ezx_init,
+        .init_machine   = a1200_init,
 MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_A910
+static void __init a910_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config));
+        pxa_set_i2c_info(NULL);
+        set_pxa_fb_info(&ezx_fb_info_2);
+        pxa_set_keypad_info(&a910_keypad_platform_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
 MACHINE_START(EZX_A910, "Motorola EZX A910")
        .phys_io        = 0x40000000,
        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .fixup                  = ezx_fixup,
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
-        .init_machine   = &ezx_init,
+        .init_machine   = a910_init,
 MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_E6
+static struct i2c_board_info __initdata e6_i2c_board_info[] = {
+        { I2C_BOARD_INFO("tea5767", 0x81) },
+};
+static void __init e6_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config));
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info));
+        set_pxa_fb_info(&ezx_fb_info_2);
+        pxa_set_keypad_info(&e6_keypad_platform_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
 MACHINE_START(EZX_E6, "Motorola EZX E6")
        .phys_io        = 0x40000000,
        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .fixup                  = ezx_fixup,
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
-        .init_machine   = &ezx_init,
+        .init_machine   = e6_init,
 MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_E2
+static struct i2c_board_info __initdata e2_i2c_board_info[] = {
+        { I2C_BOARD_INFO("tea5767", 0x81) },
+};
+static void __init e2_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config));
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info));
+        set_pxa_fb_info(&ezx_fb_info_2);
+        pxa_set_keypad_info(&e2_keypad_platform_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
 MACHINE_START(EZX_E2, "Motorola EZX E2")
        .phys_io        = 0x40000000,
        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .fixup                  = ezx_fixup,
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
-        .init_machine   = &ezx_init,
+        .init_machine   = e2_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 85ed0b33331f..0ccc91c92c44 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -24,6 +24,7 @@
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <asm/mach-types.h>
 #include <mach/pxa-regs.h>
 #include <mach/reset.h>
@@ -39,6 +40,21 @@ void clear_reset_status(unsigned int mask)
                pxa3xx_clear_reset_status(mask);
 }
+unsigned long get_clock_tick_rate(void)
+{
+        unsigned long clock_tick_rate;
+        if (cpu_is_pxa25x())
+                clock_tick_rate = 3686400;
+        else if (machine_is_mainstone())
+                clock_tick_rate = 3249600;
+        else
+                clock_tick_rate = 3250000;
+        return clock_tick_rate;
+}
+EXPORT_SYMBOL(get_clock_tick_rate);
 /*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
index 14930cf8be7b..5fec1e479cb3 100644
--- a/arch/arm/mach-pxa/gpio.c
+++ b/arch/arm/mach-pxa/gpio.c
@@ -25,6 +25,18 @@
 #include "generic.h"
+#define GPIO0_BASE      ((void __iomem *)io_p2v(0x40E00000))
+#define GPIO1_BASE      ((void __iomem *)io_p2v(0x40E00004))
+#define GPIO2_BASE      ((void __iomem *)io_p2v(0x40E00008))
+#define GPIO3_BASE      ((void __iomem *)io_p2v(0x40E00100))
+#define GPLR_OFFSET     0x00
+#define GPDR_OFFSET     0x0C
+#define GPSR_OFFSET     0x18
+#define GPCR_OFFSET     0x24
+#define GRER_OFFSET     0x30
+#define GFER_OFFSET     0x3C
+#define GEDR_OFFSET     0x48
 struct pxa_gpio_chip {
        struct gpio_chip chip;
@@ -33,6 +45,18 @@ struct pxa_gpio_chip {
 int pxa_last_gpio;
+#ifdef CONFIG_CPU_PXA26x
+/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
+ * as well as their Alternate Function value being '1' for GPIO in GAFRx.
+ */
+static int __gpio_is_inverted(unsigned gpio)
+{
+        return cpu_is_pxa25x() && gpio > 85;
+}
+#else
+#define __gpio_is_inverted(gpio)        (0)
+#endif
 /*
 * Configure pins for GPIO or other functions
 */
@@ -75,7 +99,10 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
        gpdr = pxa->regbase + GPDR_OFFSET;
        local_irq_save(flags);
        value = __raw_readl(gpdr);
-        value &= ~mask;
+        if (__gpio_is_inverted(chip->base + offset))
+                value |= mask;
+        else
+                value &= ~mask;
        __raw_writel(value, gpdr);
        local_irq_restore(flags);
@@ -97,7 +124,10 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip,
        gpdr = pxa->regbase + GPDR_OFFSET;
        local_irq_save(flags);
        tmp = __raw_readl(gpdr);
-        tmp |= mask;
+        if (__gpio_is_inverted(chip->base + offset))
+                tmp &= ~mask;
+        else
+                tmp |= mask;
        __raw_writel(tmp, gpdr);
        local_irq_restore(flags);
@@ -173,10 +203,17 @@ static unsigned long GPIO_IRQ_mask[4];
 */
 static int __gpio_is_occupied(unsigned gpio)
 {
-        if (cpu_is_pxa25x() || cpu_is_pxa27x())
+        if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
-                return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
+                int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
-        else
+                int dir = GPDR(gpio) & GPIO_bit(gpio);
-                return 0;
+                if (__gpio_is_inverted(gpio))
+                        return af != 1 || dir == 0;
+                else
+                        return af != 0 || dir != 0;
+        }
+        return 0;
 }
 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
@@ -190,9 +227,8 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
                /* Don't mess with enabled GPIOs using preconfigured edges or
                 * GPIOs set to alternate function or to output during probe
                 */
-                if ((GPIO_IRQ_rising_edge[idx] |
+                if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) ||
-                     GPIO_IRQ_falling_edge[idx] |
+                    (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio)))
-                     GPDR(gpio)) & GPIO_bit(gpio))
                        return 0;
                if (__gpio_is_occupied(gpio))
@@ -201,7 +237,10 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
        }
-        GPDR(gpio) &= ~GPIO_bit(gpio);
+        if (__gpio_is_inverted(gpio))
+                GPDR(gpio) |= GPIO_bit(gpio);
+        else
+                GPDR(gpio) &= ~GPIO_bit(gpio);
        if (type & IRQ_TYPE_EDGE_RISING)
                __set_bit(gpio, GPIO_IRQ_rising_edge);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index d8962a0fb98d..e296ce11658c 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -184,15 +184,22 @@ static unsigned long gumstix_pin_config[] __initdata = {
        GPIO6_MMC_CLK,
        GPIO53_MMC_CLK,
        GPIO8_MMC_CS0,
-        /* these are used by AM200EPD */
-        GPIO51_GPIO,
-        GPIO49_GPIO,
-        GPIO48_GPIO,
-        GPIO32_GPIO,
-        GPIO17_GPIO,
-        GPIO16_GPIO,
 };
+int __attribute__((weak)) am200_init(void)
+{
+        return 0;
+}
+static void __init carrier_board_init(void)
+{
+        /*
+         * put carrier/expansion board init here if
+         * they cannot be detected programatically
+         */
+        am200_init();
+}
 static void __init gumstix_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config));
@@ -201,6 +208,7 @@ static void __init gumstix_init(void)
        gumstix_udc_init();
        gumstix_mmc_init();
        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+        carrier_board_init();
 }
 MACHINE_START(GUMSTIX, "Gumstix")
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
new file mode 100644
index 000000000000..da6e4422c0f3
--- /dev/null
+++ b/arch/arm/mach-pxa/h5000.c
@@ -0,0 +1,200 @@
+/*
+ * Hardware definitions for HP iPAQ h5xxx Handheld Computers
+ *
+ * Copyright 2000-2003  Hewlett-Packard Company.
+ * Copyright 2002       Jamey Hicks <jamey.hicks@hp.com>
+ * Copyright 2004-2005  Phil Blundell <pb@handhelds.org>
+ * Copyright 2007-2008  Anton Vorontsov <cbouatmailru@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Author: Jamey Hicks.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/h5000.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/udc.h>
+#include "generic.h"
+/*
+ * Flash
+ */
+static struct mtd_partition h5000_flash0_partitions[] = {
+        {
+                .name = "bootldr",
+                .size = 0x00040000,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        {
+                .name = "root",
+                .size = MTDPART_SIZ_FULL,
+                .offset = MTDPART_OFS_APPEND,
+        },
+};
+static struct mtd_partition h5000_flash1_partitions[] = {
+        {
+                .name = "second root",
+                .size = SZ_16M - 0x00040000,
+                .offset = 0,
+        },
+        {
+                .name = "asset",
+                .size = MTDPART_SIZ_FULL,
+                .offset = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,
+        },
+};
+static struct physmap_flash_data h5000_flash0_data = {
+        .width = 4,
+        .parts = h5000_flash0_partitions,
+        .nr_parts = ARRAY_SIZE(h5000_flash0_partitions),
+};
+static struct physmap_flash_data h5000_flash1_data = {
+        .width = 4,
+        .parts = h5000_flash1_partitions,
+        .nr_parts = ARRAY_SIZE(h5000_flash1_partitions),
+};
+static struct resource h5000_flash0_resources = {
+        .start = PXA_CS0_PHYS,
+        .end = PXA_CS0_PHYS + SZ_32M - 1,
+        .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+};
+static struct resource h5000_flash1_resources = {
+        .start = PXA_CS0_PHYS + SZ_32M,
+        .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1,
+        .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+};
+static struct platform_device h5000_flash[] = {
+        {
+                .name = "physmap-flash",
+                .id = 0,
+                .resource = &h5000_flash0_resources,
+                .num_resources = 1,
+                .dev = {
+                        .platform_data = &h5000_flash0_data,
+                },
+        },
+        {
+                .name = "physmap-flash",
+                .id = 1,
+                .resource = &h5000_flash1_resources,
+                .num_resources = 1,
+                .dev = {
+                        .platform_data = &h5000_flash1_data,
+                },
+        },
+};
+/*
+ * USB Device Controller
+ */
+static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = {
+        .gpio_pullup = H5000_GPIO_USB_PULLUP,
+};
+/*
+ * GPIO setup
+ */
+static unsigned long h5000_pin_config[] __initdata = {
+        /* Crystal and Clock Signals */
+        GPIO12_32KHz,
+        /* SDRAM and Static Memory I/O Signals */
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,
+        GPIO79_nCS_3,
+        GPIO80_nCS_4,
+        /* FFUART */
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+        GPIO36_FFUART_DCD,
+        GPIO37_FFUART_DSR,
+        GPIO38_FFUART_RI,
+        GPIO39_FFUART_TXD,
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+        /* SSP1 */
+        GPIO23_SSP1_SCLK,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+};
+/*
+ * Localbus setup:
+ * CS0: Flash;
+ * CS1: MediaQ chip, select 16-bit bus and vlio;
+ * CS5: SAMCOP.
+ */
+static void fix_msc(void)
+{
+        MSC0 = 0x129c24f2;
+        MSC1 = 0x7ff424fa;
+        MSC2 = 0x7ff47ff4;
+        MDREFR |= 0x02080000;
+}
+/*
+ * Platform devices
+ */
+static struct platform_device *devices[] __initdata = {
+        &h5000_flash[0],
+        &h5000_flash[1],
+};
+static void __init h5000_init(void)
+{
+        fix_msc();
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config));
+        pxa_set_udc_info(&h5000_udc_mach_info);
+        platform_add_devices(ARRAY_AND_SIZE(devices));
+}
+MACHINE_START(H5400, "HP iPAQ H5000")
+        .phys_io = 0x40000000,
+        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params = 0xa0000100,
+        .map_io = pxa_map_io,
+        .init_irq = pxa25x_init_irq,
+        .timer = &pxa_timer,
+        .init_machine = h5000_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c
new file mode 100644
index 000000000000..364c5e271330
--- /dev/null
+++ b/arch/arm/mach-pxa/imote2.c
@@ -0,0 +1,575 @@
+/*
+ * linux/arch/arm/mach-pxa/imote2.c
+ *
+ * Author:      Ed C. Epp
+ * Created:     Nov 05, 2002
+ * Copyright:   Intel Corp.
+ *
+ * Modified 2008:  Jonathan Cameron
+ *
+ * The Imote2 is a wireless sensor node platform sold
+ * by Crossbow (www.xbow.com).
+ */
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/mfd/da903x.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <mach/i2c.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/regs-ssp.h>
+#include <mach/udc.h>
+#include <mach/mmc.h>
+#include <mach/pxa2xx_spi.h>
+#include <mach/pxa27x-udc.h>
+#include "devices.h"
+#include "generic.h"
+static unsigned long imote2_pin_config[] __initdata = {
+        /* Device Identification for wakeup*/
+        GPIO102_GPIO,
+        /* Button */
+        GPIO91_GPIO,
+        /* DA9030 */
+        GPIO1_GPIO,
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO112_MMC_CMD,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        /* 802.15.4 radio - driver out of mainline */
+        GPIO22_GPIO,                    /* CC_RSTN */
+        GPIO114_GPIO,                   /* CC_FIFO */
+        GPIO116_GPIO,                   /* CC_CCA */
+        GPIO0_GPIO,                     /* CC_FIFOP */
+        GPIO16_GPIO,                    /* CCSFD */
+        GPIO39_GPIO,                    /* CSn */
+        GPIO115_GPIO,                   /* Power enable */
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+        /* SSP 3 - 802.15.4 radio */
+        GPIO39_GPIO,                    /* Chip Select */
+        GPIO34_SSP3_SCLK,
+        GPIO35_SSP3_TXD,
+        GPIO41_SSP3_RXD,
+        /* SSP 2 - to daughter boards */
+        GPIO37_GPIO,                    /* Chip Select */
+        GPIO36_SSP2_SCLK,
+        GPIO38_SSP2_TXD,
+        GPIO11_SSP2_RXD,
+        /* SSP 1 - to daughter boards */
+        GPIO24_GPIO,                    /* Chip Select */
+        GPIO23_SSP1_SCLK,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+        /* BTUART Basic Connector*/
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+        /* STUART Serial console via debug board*/
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+        /* Basic sensor board */
+        GPIO96_GPIO,    /* accelerometer interrupt */
+        GPIO99_GPIO,    /* ADC interrupt */
+        /* Connector pins specified as gpios */
+        GPIO94_GPIO, /* large basic connector pin 14 */
+        GPIO10_GPIO, /* large basic connector pin 23 */
+        /* LEDS */
+        GPIO103_GPIO, /* red led */
+        GPIO104_GPIO, /* green led */
+        GPIO105_GPIO, /* blue led */
+};
+static struct gpio_led imote2_led_pins[] = {
+        {
+                .name       =  "imote2:red",
+                .gpio       = 103,
+                .active_low = 1,
+        }, {
+                .name       = "imote2:green",
+                .gpio       = 104,
+                .active_low = 1,
+        }, {
+                .name       = "imote2:blue",
+                .gpio       = 105,
+                .active_low = 1,
+        },
+};
+static struct gpio_led_platform_data imote2_led_data = {
+        .num_leds = ARRAY_SIZE(imote2_led_pins),
+        .leds     = imote2_led_pins,
+};
+static struct platform_device imote2_leds = {
+        .name = "leds-gpio",
+        .id   = -1,
+        .dev = {
+                .platform_data = &imote2_led_data,
+        },
+};
+/* Reverse engineered partly from Platformx drivers */
+enum imote2_ldos{
+        vcc_vref,
+        vcc_cc2420,
+        vcc_mica,
+        vcc_bt,
+        /* The two voltages available to sensor boards */
+        vcc_sensor_1_8,
+        vcc_sensor_3,
+        vcc_sram_ext, /* directly connected to the pxa271 */
+        vcc_pxa_pll,
+        vcc_pxa_usim, /* Reference voltage for certain gpios */
+        vcc_pxa_mem,
+        vcc_pxa_flash,
+        vcc_pxa_core, /*Dc-Dc buck not yet supported */
+        vcc_lcd,
+        vcc_bb,
+        vcc_bbio,
+        vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/
+};
+/* The values of the various regulator constraints are obviously dependent
+ * on exactly what is wired to each ldo.  Unfortunately this information is
+ * not generally available.  More information has been requested from Xbow
+ * but as of yet they haven't been forthcoming.
+ *
+ * Some of these are clearly Stargate 2 related (no way of plugging
+ * in an lcd on the IM2 for example!).
+ */
+static struct regulator_init_data imote2_ldo_init_data[] = {
+        [vcc_bbio] = {
+                .constraints = { /* board default 1.8V */
+                        .name = "vcc_bbio",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_bb] = {
+                .constraints = { /* board default 2.8V */
+                        .name = "vcc_bb",
+                        .min_uV = 2700000,
+                        .max_uV = 3000000,
+                },
+        },
+        [vcc_pxa_flash] = {
+                .constraints = {/* default is 1.8V */
+                        .name = "vcc_pxa_flash",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_cc2420] = { /* also vcc_io */
+                .constraints = {
+                        /* board default is 2.8V */
+                        .name = "vcc_cc2420",
+                        .min_uV = 2700000,
+                        .max_uV = 3300000,
+                },
+        },
+        [vcc_vref] = { /* Reference for what? */
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_vref",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_sram_ext] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_sram_ext",
+                        .min_uV = 2800000,
+                        .max_uV = 2800000,
+                },
+        },
+        [vcc_mica] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_mica",
+                        .min_uV = 2800000,
+                        .max_uV = 2800000,
+                },
+        },
+        [vcc_bt] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_bt",
+                        .min_uV = 2800000,
+                        .max_uV = 2800000,
+                },
+        },
+        [vcc_lcd] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_lcd",
+                        .min_uV = 2700000,
+                        .max_uV = 3300000,
+                },
+        },
+        [vcc_io] = { /* Same or higher than everything
+                          * bar vccbat and vccusb */
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_io",
+                        .min_uV = 2692000,
+                        .max_uV = 3300000,
+                },
+        },
+        [vcc_sensor_1_8] = {
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_sensor_1_8",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_sensor_3] = { /* curiously default 2.8V */
+                .constraints = {
+                        .name = "vcc_sensor_3",
+                        .min_uV = 2800000,
+                        .max_uV = 3000000,
+                },
+        },
+        [vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/
+                .constraints = {
+                        .name = "vcc_pxa_pll",
+                        .min_uV = 1170000,
+                        .max_uV = 1430000,
+                },
+        },
+        [vcc_pxa_usim] = {
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_pxa_usim",
+                        .min_uV = 1710000,
+                        .max_uV = 2160000,
+                },
+        },
+        [vcc_pxa_mem] = {
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_pxa_mem",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+};
+static struct da903x_subdev_info imote2_da9030_subdevs[] = {
+        {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO2,
+                .platform_data = &imote2_ldo_init_data[vcc_bbio],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO3,
+                .platform_data = &imote2_ldo_init_data[vcc_bb],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO4,
+                .platform_data = &imote2_ldo_init_data[vcc_pxa_flash],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO5,
+                .platform_data = &imote2_ldo_init_data[vcc_cc2420],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO6,
+                .platform_data = &imote2_ldo_init_data[vcc_vref],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO7,
+                .platform_data = &imote2_ldo_init_data[vcc_sram_ext],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO8,
+                .platform_data = &imote2_ldo_init_data[vcc_mica],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO9,
+                .platform_data = &imote2_ldo_init_data[vcc_bt],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO10,
+                .platform_data = &imote2_ldo_init_data[vcc_sensor_1_8],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO11,
+                .platform_data = &imote2_ldo_init_data[vcc_sensor_3],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO12,
+                .platform_data = &imote2_ldo_init_data[vcc_lcd],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO15,
+                .platform_data = &imote2_ldo_init_data[vcc_pxa_pll],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO17,
+                .platform_data = &imote2_ldo_init_data[vcc_pxa_usim],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO18,
+                .platform_data = &imote2_ldo_init_data[vcc_io],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO19,
+                .platform_data = &imote2_ldo_init_data[vcc_pxa_mem],
+        },
+};
+static struct da903x_platform_data imote2_da9030_pdata = {
+        .num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs),
+        .subdevs = imote2_da9030_subdevs,
+};
+/* As the the imote2 doesn't currently have a conventional SD slot
+ * there is no option to hotplug cards, making all this rather simple
+ */
+static int imote2_mci_get_ro(struct device *dev)
+{
+        return 0;
+}
+/* Rather simple case as hotplugging not possible */
+static struct pxamci_platform_data imote2_mci_platform_data = {
+        .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */
+        .get_ro = imote2_mci_get_ro,
+};
+static struct mtd_partition imote2flash_partitions[] = {
+        {
+                .name = "Bootloader",
+                .size = 0x00040000,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE,
+        }, {
+                .name = "Kernel",
+                .size = 0x00200000,
+                .offset = 0x00040000,
+                .mask_flags = 0,
+        }, {
+                .name = "Filesystem",
+                .size = 0x01DC0000,
+                .offset = 0x00240000,
+                .mask_flags = 0,
+        },
+};
+static struct resource flash_resources = {
+        .start = PXA_CS0_PHYS,
+        .end = PXA_CS0_PHYS + SZ_32M - 1,
+        .flags = IORESOURCE_MEM,
+};
+static struct flash_platform_data imote2_flash_data = {
+        .map_name = "cfi_probe",
+        .parts = imote2flash_partitions,
+        .nr_parts = ARRAY_SIZE(imote2flash_partitions),
+        .name = "PXA27xOnChipROM",
+        .width = 2,
+};
+static struct platform_device imote2_flash_device = {
+        .name = "pxa2xx-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &imote2_flash_data,
+        },
+        .resource = &flash_resources,
+        .num_resources = 1,
+};
+/* Some of the drivers here are out of kernel at the moment (parts of IIO)
+ * and it may be a while before they are in the mainline.
+ */
+static struct i2c_board_info __initdata imote2_i2c_board_info[] = {
+        { /* UCAM sensor board */
+                .type = "max1238",
+                .addr = 0x35,
+        }, { /* ITS400 Sensor board only */
+                .type = "max1363",
+                .addr = 0x34,
+                /* Through a nand gate - Also beware, on V2 sensor board the
+                 * pull up resistors are missing.
+                 */
+                .irq = IRQ_GPIO(99),
+        }, { /* ITS400 Sensor board only */
+                .type = "tsl2561",
+                .addr = 0x49,
+                /* Through a nand gate - Also beware, on V2 sensor board the
+                 * pull up resistors are missing.
+                 */
+                .irq = IRQ_GPIO(99),
+        }, { /* ITS400 Sensor board only */
+                .type = "tmp175",
+                .addr = 0x4A,
+                .irq = IRQ_GPIO(96),
+        },
+};
+static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = {
+        {
+                .type = "da9030",
+                .addr = 0x49,
+                .platform_data = &imote2_da9030_pdata,
+                .irq = gpio_to_irq(1),
+        },
+};
+static struct pxa2xx_spi_master pxa_ssp_master_0_info = {
+        .num_chipselect = 1,
+};
+static struct pxa2xx_spi_master pxa_ssp_master_1_info = {
+        .num_chipselect = 1,
+};
+static struct pxa2xx_spi_master pxa_ssp_master_2_info = {
+        .num_chipselect = 1,
+};
+/* Patch posted by Eric Miao <eric.miao@marvell.com> will remove
+ * the need for these functions.
+ */
+static void spi1control(u32 command)
+{
+        gpio_set_value(24, command & PXA2XX_CS_ASSERT ? 0 : 1);
+};
+static void spi3control(u32 command)
+{
+        gpio_set_value(39, command & PXA2XX_CS_ASSERT ? 0 : 1);
+};
+static struct pxa2xx_spi_chip staccel_chip_info = {
+        .tx_threshold = 8,
+        .rx_threshold = 8,
+        .dma_burst_size = 8,
+        .timeout = 235,
+        .cs_control = spi1control,
+};
+static struct pxa2xx_spi_chip cc2420_info = {
+        .tx_threshold = 8,
+        .rx_threshold = 8,
+        .dma_burst_size = 8,
+        .timeout = 235,
+        .cs_control = spi3control,
+};
+static struct spi_board_info spi_board_info[] __initdata = {
+        { /* Driver in IIO */
+                .modalias = "lis3l02dq",
+                .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */
+                .bus_num = 1,
+                .chip_select = 0,
+                .controller_data = &staccel_chip_info,
+                .irq = IRQ_GPIO(96),
+        }, { /* Driver out of kernel as it needs considerable rewriting */
+                .modalias = "cc2420",
+                .max_speed_hz = 6500000,
+                .bus_num = 3,
+                .chip_select = 0,
+                .controller_data = &cc2420_info,
+        },
+};
+static void im2_udc_command(int cmd)
+{
+        switch (cmd) {
+        case PXA2XX_UDC_CMD_CONNECT:
+                UP2OCR |=  UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE;
+                break;
+        case PXA2XX_UDC_CMD_DISCONNECT:
+                UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE);
+                break;
+        }
+}
+static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
+        .udc_command            = im2_udc_command,
+};
+static struct platform_device *imote2_devices[] = {
+        &imote2_flash_device,
+        &imote2_leds,
+};
+static struct i2c_pxa_platform_data i2c_pwr_pdata = {
+        .fast_mode = 1,
+};
+static struct i2c_pxa_platform_data i2c_pdata = {
+        .fast_mode = 1,
+};
+static void __init imote2_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config));
+        /* SPI chip select directions - all other directions should
+         * be handled by drivers.*/
+        gpio_direction_output(37, 0);
+        gpio_direction_output(24, 0);
+        gpio_direction_output(39, 0);
+        platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices));
+        pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
+        pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info);
+        pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info);
+        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+        i2c_register_board_info(0, imote2_i2c_board_info,
+                                ARRAY_SIZE(imote2_i2c_board_info));
+        i2c_register_board_info(1, imote2_pwr_i2c_board_info,
+                                ARRAY_SIZE(imote2_pwr_i2c_board_info));
+        pxa27x_set_i2c_power_info(&i2c_pwr_pdata);
+        pxa_set_i2c_info(&i2c_pdata);
+        pxa_set_mci_info(&imote2_mci_platform_data);
+        pxa_set_udc_info(&imote2_udc_info);
+}
+MACHINE_START(INTELMOTE2, "IMOTE 2")
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = imote2_init,
+        .boot_params    = 0xA0000100,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/clkdev.h b/arch/arm/mach-pxa/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index 955bfe606067..7804637a6df3 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -30,10 +30,6 @@ typedef enum {
        DMA_PRIO_LOW = 2
 } pxa_dma_prio;
-#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-#define HAVE_ARCH_PCI_SET_DMA_MASK      1
-#endif
 /*
 * DMA registration
 */
diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
index 4c90b1310270..efbd2aa9ecec 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
@@ -43,8 +43,10 @@
 #define GPIO_E800_PCMCIA_PWR1    73
 /* e7xx IrDA power control */
-#define GPIO_E7XX_IR_ON          38
+#define GPIO_E7XX_IR_OFF         38
 /* ASIC related GPIOs */
 #define GPIO_ESERIES_TMIO_IRQ        5
+#define GPIO_ESERIES_TMIO_PCLR      19
+#define GPIO_ESERIES_TMIO_SUSPEND   45
 #define GPIO_E800_ANGELX_IRQ      8
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index 42ee1956750e..099f54a41de4 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -94,3 +94,7 @@ has detected a cable insertion; driven low otherwise. */
 #define GPIO26_PRDY_nBSY_MD             (GPIO26_PRDY_nBSY | GPIO_IN)
 #define GPIO27_PRDY_nBSY_MD             (GPIO27_PRDY_nBSY | GPIO_IN)
 #define GPIO36_nCD_MD                   (GPIO36_nCD | GPIO_IN)
+/* for expansion boards that can't be programatically detected */
+extern int am200_init(void);
diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h
new file mode 100644
index 000000000000..2a5ae3802787
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/h5000.h
@@ -0,0 +1,113 @@
+/*
+ * Hardware definitions for HP iPAQ h5xxx Handheld Computers
+ *
+ * Copyright(20)02 Hewlett-Packard Company.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Author: Jamey Hicks
+ */
+#ifndef __ASM_ARCH_H5000_H
+#define __ASM_ARCH_H5000_H
+#include <mach/mfp-pxa25x.h>
+/*
+ * CPU GPIOs
+ */
+#define H5000_GPIO_POWER_BUTTON   (0)
+#define H5000_GPIO_RESET_BUTTON_N (1)
+#define H5000_GPIO_OPT_INT        (2)
+#define H5000_GPIO_BACKUP_POWER   (3)
+#define H5000_GPIO_ACTION_BUTTON  (4)
+#define H5000_GPIO_COM_DCD_SOMETHING  (5) /* what is this really ? */
+/* 6 not connected */
+#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */
+/* 8 not connected */
+#define H5000_GPIO_RSO_N          (9)       /* reset output from max1702 which regulates 3.3 and 2.5 */
+#define H5000_GPIO_ASIC_INT_N   (10)       /* from companion asic */
+#define H5000_GPIO_BT_ENV_0     (11)       /* to LMX9814, set to 1 according to regdump */
+/*(12) not connected */
+#define H5000_GPIO_BT_ENV_1     (13)       /* to LMX9814, set to 1 according to regdump */
+#define H5000_GPIO_BT_WU        (14)       /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */
+/*(15) is CS1# */
+/*(16) not connected */
+/*(17) not connected */
+/*(18) is pcmcia ready */
+/*(19) is dreq1 */
+/*(20) is dreq0 */
+#define H5000_GPIO_OE_RD_NWR    (21)       /* output enable on rd/nwr signal to companion asic */
+/*(22) is not connected */
+#define H5000_GPIO_OPT_SPI_CLK  (23)       /* to extension pack */
+#define H5000_GPIO_OPT_SPI_CS_N (24)       /* to extension pack */
+#define H5000_GPIO_OPT_SPI_DOUT (25)       /* to extension pack */
+#define H5000_GPIO_OPT_SPI_DIN  (26)       /* to extension pack */
+/*(27) not connected */
+#define H5000_GPIO_I2S_BITCLK   (28)       /* connected to AC97 codec */
+#define H5000_GPIO_I2S_DATAOUT  (29)       /* connected to AC97 codec */
+#define H5000_GPIO_I2S_DATAIN   (30)       /* connected to AC97 codec */
+#define H5000_GPIO_I2S_LRCLK    (31)       /* connected to AC97 codec */
+#define H5000_GPIO_I2S_SYSCLK   (32)       /* connected to AC97 codec */
+/*(33) is CS5# */
+#define H5000_GPIO_COM_RXD      (34)       /* connected to cradle/cable connector */
+#define H5000_GPIO_COM_CTS      (35)       /* connected to cradle/cable connector */
+#define H5000_GPIO_COM_DCD      (36)       /* connected to cradle/cable connector */
+#define H5000_GPIO_COM_DSR      (37)       /* connected to cradle/cable connector */
+#define H5000_GPIO_COM_RI       (38)       /* connected to cradle/cable connector */
+#define H5000_GPIO_COM_TXD      (39)       /* connected to cradle/cable connector */
+#define H5000_GPIO_COM_DTR      (40)       /* connected to cradle/cable connector */
+#define H5000_GPIO_COM_RTS      (41)       /* connected to cradle/cable connector */
+#define H5000_GPIO_BT_RXD       (42)       /* connected to BT (LMX9814) */
+#define H5000_GPIO_BT_TXD       (43)       /* connected to BT (LMX9814) */
+#define H5000_GPIO_BT_CTS       (44)       /* connected to BT (LMX9814) */
+#define H5000_GPIO_BT_RTS       (45)       /* connected to BT (LMX9814) */
+#define H5000_GPIO_IRDA_RXD     (46)
+#define H5000_GPIO_IRDA_TXD     (47)
+#define H5000_GPIO_POE_N        (48)       /* used for pcmcia */
+#define H5000_GPIO_PWE_N        (49)       /* used for pcmcia */
+#define H5000_GPIO_PIOR_N       (50)       /* used for pcmcia */
+#define H5000_GPIO_PIOW_N       (51)       /* used for pcmcia */
+#define H5000_GPIO_PCE1_N       (52)       /* used for pcmcia */
+#define H5000_GPIO_PCE2_N       (53)       /* used for pcmcia */
+#define H5000_GPIO_PSKTSEL      (54)       /* used for pcmcia */
+#define H5000_GPIO_PREG_N       (55)       /* used for pcmcia */
+#define H5000_GPIO_PWAIT_N      (56)       /* used for pcmcia */
+#define H5000_GPIO_IOIS16_N     (57)       /* used for pcmcia */
+#define H5000_GPIO_IRDA_SD      (58)       /* to hsdl3002 sd */
+/*(59) not connected */
+#define H5000_GPIO_POWER_SD_N   (60)       /* controls power to SD */
+#define H5000_GPIO_POWER_RS232_N        (61)       /* inverted FORCEON to rs232 transceiver */
+#define H5000_GPIO_POWER_ACCEL_N        (62)       /* controls power to accel */
+/*(63) is not connected */
+#define H5000_GPIO_OPT_NVRAM    (64)       /* controls power to expansion pack */
+#define H5000_GPIO_CHG_EN       (65)       /* to sc801 en */
+#define H5000_GPIO_USB_PULLUP   (66)       /* USB d+ pullup via 1.5K resistor */
+#define H5000_GPIO_BT_2V8_N     (67)       /* 2.8V used by bluetooth */
+#define H5000_GPIO_EXT_CHG_RATE (68)       /* enables external charging rate */
+/*(69) is not connected */
+#define H5000_GPIO_CIR_RESET    (70)       /* consumer IR reset */
+#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71)
+#define H5000_GPIO_BT_M_RESET   (72)
+#define H5000_GPIO_STD_CHG_RATE (73)
+#define H5000_GPIO_SD_WP_N      (74)
+#define H5000_GPIO_MOTOR_ON_N   (75)       /* external pullup on this */
+#define H5000_GPIO_HEADPHONE_DETECT     (76)
+#define H5000_GPIO_USB_CHG_RATE (77)       /* select rate for charging via usb */
+/*(78) is CS2# */
+/*(79) is CS3# */
+/*(80) is CS4# */
+#endif /* __ASM_ARCH_H5000_H */
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index a582a6d9b92b..16ab79547dae 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -102,6 +102,9 @@
 *  PXA930      B0      0x69056835      0x5E643013
 *  PXA930      B1      0x69056837      0x7E643013
 *  PXA930      B2      0x69056838      0x8E643013
+ *
+ *  PXA935      A0      0x56056931      0x1E653013
+ *  PXA935      B0      0x56056936      0x6E653013
 */
 #ifdef CONFIG_PXA25x
 #define __cpu_is_pxa210(id)                             \
@@ -178,12 +181,22 @@
 #define __cpu_is_pxa930(id)                             \
        ({                                              \
                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x683;           \
+                _id == 0x683;                           \
         })
 #else
 #define __cpu_is_pxa930(id)     (0)
 #endif
+#ifdef CONFIG_CPU_PXA935
+#define __cpu_is_pxa935(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x693;                           \
+         })
+#else
+#define __cpu_is_pxa935(id)     (0)
+#endif
 #define cpu_is_pxa210()                                 \
        ({                                              \
                __cpu_is_pxa210(read_cpuid_id());       \
@@ -204,8 +217,6 @@
                __cpu_is_pxa25x(read_cpuid_id());       \
        })
-extern int cpu_is_pxa26x(void);
 #define cpu_is_pxa27x()                                 \
        ({                                              \
                __cpu_is_pxa27x(read_cpuid_id());       \
@@ -232,6 +243,12 @@ extern int cpu_is_pxa26x(void);
                __cpu_is_pxa930(id);                    \
         })
+#define cpu_is_pxa935()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa935(id);                    \
+         })
 /*
 * CPUID Core Generation Bit
 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
@@ -249,6 +266,12 @@ extern int cpu_is_pxa26x(void);
                _id == 0x3;                             \
         })
+#define __cpu_is_pxa9xx(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x683 || _id == 0x693;           \
+         })
 #define cpu_is_pxa2xx()                                 \
        ({                                              \
                __cpu_is_pxa2xx(read_cpuid_id());       \
@@ -259,32 +282,25 @@ extern int cpu_is_pxa26x(void);
                __cpu_is_pxa3xx(read_cpuid_id());       \
         })
-/*
+#define cpu_is_pxa9xx()                                 \
- * Handy routine to set GPIO alternate functions
+        ({                                              \
- */
+                __cpu_is_pxa9xx(read_cpuid_id());       \
-extern int pxa_gpio_mode( int gpio_mode );
+         })
-/*
- * Return GPIO level, nonzero means high, zero is low
- */
-extern int pxa_gpio_get_value(unsigned gpio);
-/*
- * Set output GPIO level
- */
-extern void pxa_gpio_set_value(unsigned gpio, int value);
 /*
 * return current memory and LCD clock frequency in units of 10kHz
 */
 extern unsigned int get_memclk_frequency_10khz(void);
+/* return the clock tick rate of the OS timer */
+extern unsigned long get_clock_tick_rate(void);
 #endif
 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
 #define PCIBIOS_MIN_IO          0
 #define PCIBIOS_MIN_MEM         0
 #define pcibios_assign_all_busses()     1
+#define HAVE_ARCH_PCI_SET_DMA_MASK      1
 #endif
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index 600fd4f76603..262691fb97d8 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -6,15 +6,13 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
-#include <mach/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
 * We don't actually have real ISA nor PCI buses, but there is so many
 * drivers out there that might just work if we fake them...
 */
-#define __io(a)                 ((void __iomem *)(a))
+#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)            (a)
+#define __mem_pci(a)    (a)
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 5c4e320c1437..6c9b21c51322 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -1,8 +1,13 @@
-#ifndef __ASM_ARCH_ZYLONITE_H
+#ifndef __ASM_ARCH_LITTLETON_H
-#define __ASM_ARCH_ZYLONITE_H
+#define __ASM_ARCH_LITTLETON_H
+#include <mach/gpio.h>
 #define LITTLETON_ETH_PHYS      0x30000000
 #define LITTLETON_GPIO_LCD_CS   (17)
-#endif /* __ASM_ARCH_ZYLONITE_H */
+#define EXT0_GPIO_BASE  (NR_BUILTIN_GPIO)
+#define EXT0_GPIO(x)    (EXT0_GPIO_BASE + (x))
+#endif /* __ASM_ARCH_LITTLETON_H */
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 59aef89808d6..f626730ee42e 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -18,16 +18,6 @@
 #define PHYS_OFFSET     UL(0xa0000000)
 /*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)         __virt_to_phys(x)
-#define __bus_to_virt(x)         __phys_to_virt(x)
-/*
 * The nodes are matched with the physical SDRAM banks as follows:
 *
 *      node 0:  0xa0000000-0xa3ffffff  -->  0xc0000000-0xc3ffffff
@@ -47,6 +37,7 @@ void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
        cmx2xx_pci_adjust_zones(node, size, holes)
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_64M - 1)
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_64M)
 #endif
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index 617cab2cc8d0..a72869b73ee3 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -158,4 +158,35 @@
 #define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
 #define GPIO77_LCD_BIAS         MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+#ifdef CONFIG_CPU_PXA26x
+/* GPIO */
+#define GPIO85_GPIO             MFP_CFG_IN(GPIO85, AF0)
+#define GPIO86_GPIO             MFP_CFG_IN(GPIO86, AF1)
+#define GPIO87_GPIO             MFP_CFG_IN(GPIO87, AF1)
+#define GPIO88_GPIO             MFP_CFG_IN(GPIO88, AF1)
+#define GPIO89_GPIO             MFP_CFG_IN(GPIO89, AF1)
+/* SDRAM */
+#define GPIO86_nSDCS2           MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH)
+#define GPIO87_nSDCS3           MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH)
+#define GPIO88_RDnWR            MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH)
+#define GPIO89_nACRESET         MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH)
+/* USB */
+#define GPIO9_USB_RCV           MFP_CFG_IN(GPIO9, AF1)
+#define GPIO32_USB_VP           MFP_CFG_IN(GPIO32, AF2)
+#define GPIO34_USB_VM           MFP_CFG_IN(GPIO34, AF2)
+#define GPIO39_USB_VPO          MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW)
+#define GPIO56_USB_VMO          MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
+#define GPIO57_USB_nOE          MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH)
+/* ASSP */
+#define GPIO28_ASSP_BITCLK_IN   MFP_CFG_IN(GPIO28, AF3)
+#define GPIO28_ASSP_BITCLK_OUT  MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW)
+#define GPIO29_ASSP_RXD         MFP_CFG_IN(GPIO29, AF3)
+#define GPIO30_ASSP_TXD         MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
+#define GPIO31_ASSP_SFRM_IN     MFP_CFG_IN(GPIO31, AF1)
+#define GPIO31_ASSP_SFRM_OUT    MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
+#endif
 #endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index 122bdbd53182..da4f85a4f990 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -11,6 +11,12 @@
 #include <mach/mfp.h>
 #include <mach/mfp-pxa2xx.h>
+/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
+ * bit is set, regardless of the GPIO configuration
+ */
+#define GPIO3_GPIO              MFP_CFG_IN(GPIO3, AF0)
+#define GPIO4_GPIO              MFP_CFG_IN(GPIO4, AF0)
 /* GPIO */
 #define GPIO85_GPIO             MFP_CFG_IN(GPIO85, AF0)
 #define GPIO86_GPIO             MFP_CFG_IN(GPIO86, AF0)
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index fabd9b4df827..fa73f56a1372 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -421,6 +421,7 @@
 #define GPIO20_PWM0             MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
 #define GPIO21_PWM2             MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
 #define GPIO22_PWM3             MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
+#define GPIO32_PWM0             MFP_CFG_LPM(GPIO32, AF4, PULL_LOW)
 /* CIR */
 #define GPIO46_CIR_OUT          MFP_CFG(GPIO46, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
index 8483cb511831..02868447b0b1 100644
--- a/arch/arm/mach-pxa/include/mach/mioa701.h
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -10,12 +10,14 @@
         (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
 /* Global GPIOs */
-#define GPIO9_CHARGE_nEN                        9
+#define GPIO9_CHARGE_EN                         9
 #define GPIO18_POWEROFF                         18
 #define GPIO87_LCD_POWER                        87
+#define GPIO96_AC_DETECT                        96
+#define GPIO80_MAYBE_CHARGE_VDROP               80      /* Drop of 88mV */
 /* USB */
-#define GPIO13_USB_DETECT                       13
+#define GPIO13_nUSB_DETECT                      13
 #define GPIO22_USB_ENABLE                       22
 /* SDIO bits */
@@ -24,7 +26,10 @@
 #define GPIO91_SDIO_EN                          91
 /* Bluetooth */
+#define GPIO14_BT_nACTIVITY                     14
 #define GPIO83_BT_ON                            83
+#define GPIO77_BT_UNKNOWN1                      77
+#define GPIO86_BT_MAYBE_nRESET                  86
 /* GPS */
 #define GPIO23_GPS_UNKNOWN1                     23
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
index 4d452fcb1508..cfca8155be72 100644
--- a/arch/arm/mach-pxa/include/mach/mtd-xip.h
+++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h
@@ -15,6 +15,7 @@
 #ifndef __ARCH_PXA_MTD_XIP_H__
 #define __ARCH_PXA_MTD_XIP_H__
+#include <mach/hardware.h>
 #include <mach/pxa-regs.h>
 #define xip_irqpending()        (ICIP & ICMR)
diff --git a/arch/arm/mach-pxa/include/mach/palmasoc.h b/arch/arm/mach-pxa/include/mach/palmasoc.h
new file mode 100644
index 000000000000..6c4b1f7de20a
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmasoc.h
@@ -0,0 +1,13 @@
+#ifndef _INCLUDE_PALMASOC_H_
+#define _INCLUDE_PALMASOC_H_
+struct palm27x_asoc_info {
+        int     jack_gpio;
+};
+#ifdef CONFIG_SND_PXA2XX_SOC_PALM27X
+void __init palm27x_asoc_set_pdata(struct palm27x_asoc_info *data);
+#else
+static inline void palm27x_asoc_set_pdata(struct palm27x_asoc_info *data) {}
+#endif
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index 15295d960000..31d615aa7723 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -13,6 +13,7 @@
 #ifndef __PXA_REGS_H
 #define __PXA_REGS_H
+#include <mach/hardware.h>
 /*
 * PXA Chip selects
@@ -123,298 +124,6 @@
 #define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
 #define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
-/*
- * UARTs
- */
-/* Full Function UART (FFUART) */
-#define FFUART          FFRBR
-#define FFRBR           __REG(0x40100000)  /* Receive Buffer Register (read only) */
-#define FFTHR           __REG(0x40100000)  /* Transmit Holding Register (write only) */
-#define FFIER           __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
-#define FFIIR           __REG(0x40100008)  /* Interrupt ID Register (read only) */
-#define FFFCR           __REG(0x40100008)  /* FIFO Control Register (write only) */
-#define FFLCR           __REG(0x4010000C)  /* Line Control Register (read/write) */
-#define FFMCR           __REG(0x40100010)  /* Modem Control Register (read/write) */
-#define FFLSR           __REG(0x40100014)  /* Line Status Register (read only) */
-#define FFMSR           __REG(0x40100018)  /* Modem Status Register (read only) */
-#define FFSPR           __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
-#define FFISR           __REG(0x40100020)  /* Infrared Selection Register (read/write) */
-#define FFDLL           __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH           __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-/* Bluetooth UART (BTUART) */
-#define BTUART          BTRBR
-#define BTRBR           __REG(0x40200000)  /* Receive Buffer Register (read only) */
-#define BTTHR           __REG(0x40200000)  /* Transmit Holding Register (write only) */
-#define BTIER           __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
-#define BTIIR           __REG(0x40200008)  /* Interrupt ID Register (read only) */
-#define BTFCR           __REG(0x40200008)  /* FIFO Control Register (write only) */
-#define BTLCR           __REG(0x4020000C)  /* Line Control Register (read/write) */
-#define BTMCR           __REG(0x40200010)  /* Modem Control Register (read/write) */
-#define BTLSR           __REG(0x40200014)  /* Line Status Register (read only) */
-#define BTMSR           __REG(0x40200018)  /* Modem Status Register (read only) */
-#define BTSPR           __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
-#define BTISR           __REG(0x40200020)  /* Infrared Selection Register (read/write) */
-#define BTDLL           __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH           __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-/* Standard UART (STUART) */
-#define STUART          STRBR
-#define STRBR           __REG(0x40700000)  /* Receive Buffer Register (read only) */
-#define STTHR           __REG(0x40700000)  /* Transmit Holding Register (write only) */
-#define STIER           __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
-#define STIIR           __REG(0x40700008)  /* Interrupt ID Register (read only) */
-#define STFCR           __REG(0x40700008)  /* FIFO Control Register (write only) */
-#define STLCR           __REG(0x4070000C)  /* Line Control Register (read/write) */
-#define STMCR           __REG(0x40700010)  /* Modem Control Register (read/write) */
-#define STLSR           __REG(0x40700014)  /* Line Status Register (read only) */
-#define STMSR           __REG(0x40700018)  /* Reserved */
-#define STSPR           __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
-#define STISR           __REG(0x40700020)  /* Infrared Selection Register (read/write) */
-#define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-/* Hardware UART (HWUART) */
-#define HWUART          HWRBR
-#define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
-#define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
-#define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
-#define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
-#define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
-#define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
-#define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
-#define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
-#define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
-#define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
-#define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
-#define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
-#define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
-#define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
-#define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-#define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
-#define IER_UUE         (1 << 6)        /* UART Unit Enable */
-#define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
-#define IER_RTIOE       (1 << 4)        /* Receiver Time Out Interrupt Enable */
-#define IER_MIE         (1 << 3)        /* Modem Interrupt Enable */
-#define IER_RLSE        (1 << 2)        /* Receiver Line Status Interrupt Enable */
-#define IER_TIE         (1 << 1)        /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE       (1 << 0)        /* Receiver Data Available Interrupt Enable */
-#define IIR_FIFOES1     (1 << 7)        /* FIFO Mode Enable Status */
-#define IIR_FIFOES0     (1 << 6)        /* FIFO Mode Enable Status */
-#define IIR_TOD         (1 << 3)        /* Time Out Detected */
-#define IIR_IID2        (1 << 2)        /* Interrupt Source Encoded */
-#define IIR_IID1        (1 << 1)        /* Interrupt Source Encoded */
-#define IIR_IP          (1 << 0)        /* Interrupt Pending (active low) */
-#define FCR_ITL2        (1 << 7)        /* Interrupt Trigger Level */
-#define FCR_ITL1        (1 << 6)        /* Interrupt Trigger Level */
-#define FCR_RESETTF     (1 << 2)        /* Reset Transmitter FIFO */
-#define FCR_RESETRF     (1 << 1)        /* Reset Receiver FIFO */
-#define FCR_TRFIFOE     (1 << 0)        /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1       (0)
-#define FCR_ITL_8       (FCR_ITL1)
-#define FCR_ITL_16      (FCR_ITL2)
-#define FCR_ITL_32      (FCR_ITL2|FCR_ITL1)
-#define LCR_DLAB        (1 << 7)        /* Divisor Latch Access Bit */
-#define LCR_SB          (1 << 6)        /* Set Break */
-#define LCR_STKYP       (1 << 5)        /* Sticky Parity */
-#define LCR_EPS         (1 << 4)        /* Even Parity Select */
-#define LCR_PEN         (1 << 3)        /* Parity Enable */
-#define LCR_STB         (1 << 2)        /* Stop Bit */
-#define LCR_WLS1        (1 << 1)        /* Word Length Select */
-#define LCR_WLS0        (1 << 0)        /* Word Length Select */
-#define LSR_FIFOE       (1 << 7)        /* FIFO Error Status */
-#define LSR_TEMT        (1 << 6)        /* Transmitter Empty */
-#define LSR_TDRQ        (1 << 5)        /* Transmit Data Request */
-#define LSR_BI          (1 << 4)        /* Break Interrupt */
-#define LSR_FE          (1 << 3)        /* Framing Error */
-#define LSR_PE          (1 << 2)        /* Parity Error */
-#define LSR_OE          (1 << 1)        /* Overrun Error */
-#define LSR_DR          (1 << 0)        /* Data Ready */
-#define MCR_LOOP        (1 << 4)
-#define MCR_OUT2        (1 << 3)        /* force MSR_DCD in loopback mode */
-#define MCR_OUT1        (1 << 2)        /* force MSR_RI in loopback mode */
-#define MCR_RTS         (1 << 1)        /* Request to Send */
-#define MCR_DTR         (1 << 0)        /* Data Terminal Ready */
-#define MSR_DCD         (1 << 7)        /* Data Carrier Detect */
-#define MSR_RI          (1 << 6)        /* Ring Indicator */
-#define MSR_DSR         (1 << 5)        /* Data Set Ready */
-#define MSR_CTS         (1 << 4)        /* Clear To Send */
-#define MSR_DDCD        (1 << 3)        /* Delta Data Carrier Detect */
-#define MSR_TERI        (1 << 2)        /* Trailing Edge Ring Indicator */
-#define MSR_DDSR        (1 << 1)        /* Delta Data Set Ready */
-#define MSR_DCTS        (1 << 0)        /* Delta Clear To Send */
-/*
- * IrSR (Infrared Selection Register)
- */
-#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
-#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
-#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
-#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
-#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
-/*
- * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
- */
-/*
- * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
- */
-/*
- * AC97 Controller registers
- */
-#define POCR            __REG(0x40500000)  /* PCM Out Control Register */
-#define POCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
-#define POCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-#define PICR            __REG(0x40500004)  /* PCM In Control Register */
-#define PICR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
-#define PICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-#define MCCR            __REG(0x40500008)  /* Mic In Control Register */
-#define MCCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
-#define MCCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-#define GCR             __REG(0x4050000C)  /* Global Control Register */
-#ifdef CONFIG_PXA3xx
-#define GCR_CLKBPB      (1 << 31)       /* Internal clock enable */
-#endif
-#define GCR_nDMAEN      (1 << 24)       /* non DMA Enable */
-#define GCR_CDONE_IE    (1 << 19)       /* Command Done Interrupt Enable */
-#define GCR_SDONE_IE    (1 << 18)       /* Status Done Interrupt Enable */
-#define GCR_SECRDY_IEN  (1 << 9)        /* Secondary Ready Interrupt Enable */
-#define GCR_PRIRDY_IEN  (1 << 8)        /* Primary Ready Interrupt Enable */
-#define GCR_SECRES_IEN  (1 << 5)        /* Secondary Resume Interrupt Enable */
-#define GCR_PRIRES_IEN  (1 << 4)        /* Primary Resume Interrupt Enable */
-#define GCR_ACLINK_OFF  (1 << 3)        /* AC-link Shut Off */
-#define GCR_WARM_RST    (1 << 2)        /* AC97 Warm Reset */
-#define GCR_COLD_RST    (1 << 1)        /* AC'97 Cold Reset (0 = active) */
-#define GCR_GIE         (1 << 0)        /* Codec GPI Interrupt Enable */
-#define POSR            __REG(0x40500010)  /* PCM Out Status Register */
-#define POSR_FIFOE      (1 << 4)        /* FIFO error */
-#define POSR_FSR        (1 << 2)        /* FIFO Service Request */
-#define PISR            __REG(0x40500014)  /* PCM In Status Register */
-#define PISR_FIFOE      (1 << 4)        /* FIFO error */
-#define PISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
-#define PISR_FSR        (1 << 2)        /* FIFO Service Request */
-#define MCSR            __REG(0x40500018)  /* Mic In Status Register */
-#define MCSR_FIFOE      (1 << 4)        /* FIFO error */
-#define MCSR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
-#define MCSR_FSR        (1 << 2)        /* FIFO Service Request */
-#define GSR             __REG(0x4050001C)  /* Global Status Register */
-#define GSR_CDONE       (1 << 19)       /* Command Done */
-#define GSR_SDONE       (1 << 18)       /* Status Done */
-#define GSR_RDCS        (1 << 15)       /* Read Completion Status */
-#define GSR_BIT3SLT12   (1 << 14)       /* Bit 3 of slot 12 */
-#define GSR_BIT2SLT12   (1 << 13)       /* Bit 2 of slot 12 */
-#define GSR_BIT1SLT12   (1 << 12)       /* Bit 1 of slot 12 */
-#define GSR_SECRES      (1 << 11)       /* Secondary Resume Interrupt */
-#define GSR_PRIRES      (1 << 10)       /* Primary Resume Interrupt */
-#define GSR_SCR         (1 << 9)        /* Secondary Codec Ready */
-#define GSR_PCR         (1 << 8)        /*  Primary Codec Ready */
-#define GSR_MCINT       (1 << 7)        /* Mic In Interrupt */
-#define GSR_POINT       (1 << 6)        /* PCM Out Interrupt */
-#define GSR_PIINT       (1 << 5)        /* PCM In Interrupt */
-#define GSR_ACOFFD      (1 << 3)        /* AC-link Shut Off Done */
-#define GSR_MOINT       (1 << 2)        /* Modem Out Interrupt */
-#define GSR_MIINT       (1 << 1)        /* Modem In Interrupt */
-#define GSR_GSCI        (1 << 0)        /* Codec GPI Status Change Interrupt */
-#define CAR             __REG(0x40500020)  /* CODEC Access Register */
-#define CAR_CAIP        (1 << 0)        /* Codec Access In Progress */
-#define PCDR            __REG(0x40500040)  /* PCM FIFO Data Register */
-#define MCDR            __REG(0x40500060)  /* Mic-in FIFO Data Register */
-#define MOCR            __REG(0x40500100)  /* Modem Out Control Register */
-#define MOCR_FEIE       (1 << 3)        /* FIFO Error */
-#define MOCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-#define MICR            __REG(0x40500108)  /* Modem In Control Register */
-#define MICR_FEIE       (1 << 3)        /* FIFO Error */
-#define MICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-#define MOSR            __REG(0x40500110)  /* Modem Out Status Register */
-#define MOSR_FIFOE      (1 << 4)        /* FIFO error */
-#define MOSR_FSR        (1 << 2)        /* FIFO Service Request */
-#define MISR            __REG(0x40500118)  /* Modem In Status Register */
-#define MISR_FIFOE      (1 << 4)        /* FIFO error */
-#define MISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
-#define MISR_FSR        (1 << 2)        /* FIFO Service Request */
-#define MODR            __REG(0x40500140)  /* Modem FIFO Data Register */
-#define PAC_REG_BASE    __REG(0x40500200)  /* Primary Audio Codec */
-#define SAC_REG_BASE    __REG(0x40500300)  /* Secondary Audio Codec */
-#define PMC_REG_BASE    __REG(0x40500400)  /* Primary Modem Codec */
-#define SMC_REG_BASE    __REG(0x40500500)  /* Secondary Modem Codec */
-/*
- * Fast Infrared Communication Port
- */
-#define FICP            __REG(0x40800000)  /* Start of FICP area */
-#define ICCR0           __REG(0x40800000)  /* ICP Control Register 0 */
-#define ICCR1           __REG(0x40800004)  /* ICP Control Register 1 */
-#define ICCR2           __REG(0x40800008)  /* ICP Control Register 2 */
-#define ICDR            __REG(0x4080000c)  /* ICP Data Register */
-#define ICSR0           __REG(0x40800014)  /* ICP Status Register 0 */
-#define ICSR1           __REG(0x40800018)  /* ICP Status Register 1 */
-#define ICCR0_AME       (1 << 7)        /* Address match enable */
-#define ICCR0_TIE       (1 << 6)        /* Transmit FIFO interrupt enable */
-#define ICCR0_RIE       (1 << 5)        /* Recieve FIFO interrupt enable */
-#define ICCR0_RXE       (1 << 4)        /* Receive enable */
-#define ICCR0_TXE       (1 << 3)        /* Transmit enable */
-#define ICCR0_TUS       (1 << 2)        /* Transmit FIFO underrun select */
-#define ICCR0_LBM       (1 << 1)        /* Loopback mode */
-#define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
-#define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
-#define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
-#define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
-#define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
-#define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
-#define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
-#ifdef CONFIG_PXA27x
-#define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
-#endif
-#define ICSR0_FRE       (1 << 5)        /* Framing error */
-#define ICSR0_RFS       (1 << 4)        /* Receive FIFO service request */
-#define ICSR0_TFS       (1 << 3)        /* Transnit FIFO service request */
-#define ICSR0_RAB       (1 << 2)        /* Receiver abort */
-#define ICSR0_TUR       (1 << 1)        /* Trunsmit FIFO underun */
-#define ICSR0_EIF       (1 << 0)        /* End/Error in FIFO */
-#define ICSR1_ROR       (1 << 6)        /* Receiver FIFO underrun  */
-#define ICSR1_CRE       (1 << 5)        /* CRC error */
-#define ICSR1_EOF       (1 << 4)        /* End of frame */
-#define ICSR1_TNF       (1 << 3)        /* Transmit FIFO not full */
-#define ICSR1_RNE       (1 << 2)        /* Receive FIFO not empty */
-#define ICSR1_TBY       (1 << 1)        /* Tramsmiter busy flag */
-#define ICSR1_RSY       (1 << 0)        /* Recevier synchronized flag */
 /*
 * Real Time Clock
 */
@@ -463,19 +172,6 @@
 /*
- * Pulse Width Modulator
- */
-#define PWM_CTRL0       __REG(0x40B00000)  /* PWM 0 Control Register */
-#define PWM_PWDUTY0     __REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
-#define PWM_PERVAL0     __REG(0x40B00008)  /* PWM 0 Period Control Register */
-#define PWM_CTRL1       __REG(0x40C00000)  /* PWM 1Control Register */
-#define PWM_PWDUTY1     __REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
-#define PWM_PERVAL1     __REG(0x40C00008)  /* PWM 1 Period Control Register */
-/*
 * Interrupt Controller
 */
@@ -496,19 +192,6 @@
 * General Purpose I/O
 */
-#define GPIO0_BASE      ((void __iomem *)io_p2v(0x40E00000))
-#define GPIO1_BASE      ((void __iomem *)io_p2v(0x40E00004))
-#define GPIO2_BASE      ((void __iomem *)io_p2v(0x40E00008))
-#define GPIO3_BASE      ((void __iomem *)io_p2v(0x40E00100))
-#define GPLR_OFFSET     0x00
-#define GPDR_OFFSET     0x0C
-#define GPSR_OFFSET     0x18
-#define GPCR_OFFSET     0x24
-#define GRER_OFFSET     0x30
-#define GFER_OFFSET     0x3C
-#define GEDR_OFFSET     0x48
 #define GPLR0           __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
 #define GPLR1           __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
 #define GPLR2           __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
@@ -558,10 +241,6 @@
 #define GPIO_bit(x)     (1 << ((x) & 0x1f))
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-/* Interrupt Controller */
 #define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
 #define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
 #define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
@@ -580,189 +259,5 @@
 #define GEDR(x)         (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
 #define GAFR(x)         (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
                         ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
-#else
-#define GPLR(x)         __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define GPDR(x)         __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define GPSR(x)         __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define GPCR(x)         __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define GRER(x)         __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define GFER(x)         __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define GEDR(x)         __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define GAFR(x)         __REG2(0x40E00054, ((x) & 0x70) >> 2)
-#endif
-/*
- * Power Manager - see pxa2xx-regs.h
- */
-/*
- * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h
- */
-/*
- * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
- */
-/*
- * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
- */
-#ifdef CONFIG_PXA27x
-/* Camera Interface */
-#define CICR0           __REG(0x50000000)
-#define CICR1           __REG(0x50000004)
-#define CICR2           __REG(0x50000008)
-#define CICR3           __REG(0x5000000C)
-#define CICR4           __REG(0x50000010)
-#define CISR            __REG(0x50000014)
-#define CIFR            __REG(0x50000018)
-#define CITOR           __REG(0x5000001C)
-#define CIBR0           __REG(0x50000028)
-#define CIBR1           __REG(0x50000030)
-#define CIBR2           __REG(0x50000038)
-#define CICR0_DMAEN     (1 << 31)       /* DMA request enable */
-#define CICR0_PAR_EN    (1 << 30)       /* Parity enable */
-#define CICR0_SL_CAP_EN (1 << 29)       /* Capture enable for slave mode */
-#define CICR0_ENB       (1 << 28)       /* Camera interface enable */
-#define CICR0_DIS       (1 << 27)       /* Camera interface disable */
-#define CICR0_SIM       (0x7 << 24)     /* Sensor interface mode mask */
-#define CICR0_TOM       (1 << 9)        /* Time-out mask */
-#define CICR0_RDAVM     (1 << 8)        /* Receive-data-available mask */
-#define CICR0_FEM       (1 << 7)        /* FIFO-empty mask */
-#define CICR0_EOLM      (1 << 6)        /* End-of-line mask */
-#define CICR0_PERRM     (1 << 5)        /* Parity-error mask */
-#define CICR0_QDM       (1 << 4)        /* Quick-disable mask */
-#define CICR0_CDM       (1 << 3)        /* Disable-done mask */
-#define CICR0_SOFM      (1 << 2)        /* Start-of-frame mask */
-#define CICR0_EOFM      (1 << 1)        /* End-of-frame mask */
-#define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
-#define CICR1_TBIT      (1 << 31)       /* Transparency bit */
-#define CICR1_RGBT_CONV (0x3 << 29)     /* RGBT conversion mask */
-#define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
-#define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
-#define CICR1_RGB_F     (1 << 11)       /* RGB format */
-#define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
-#define CICR1_RGB_BPP   (0x7 << 7)      /* RGB bis per pixel mask */
-#define CICR1_RAW_BPP   (0x3 << 5)      /* Raw bis per pixel mask */
-#define CICR1_COLOR_SP  (0x3 << 3)      /* Color space mask */
-#define CICR1_DW        (0x7 << 0)      /* Data width mask */
-#define CICR2_BLW       (0xff << 24)    /* Beginning-of-line pixel clock
-                                           wait count mask */
-#define CICR2_ELW       (0xff << 16)    /* End-of-line pixel clock
-                                           wait count mask */
-#define CICR2_HSW       (0x3f << 10)    /* Horizontal sync pulse width mask */
-#define CICR2_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
-                                           wait count mask */
-#define CICR2_FSW       (0x7 << 0)      /* Frame stabilization
-                                           wait count mask */
-#define CICR3_BFW       (0xff << 24)    /* Beginning-of-frame line clock
-                                           wait count mask */
-#define CICR3_EFW       (0xff << 16)    /* End-of-frame line clock
-                                           wait count mask */
-#define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
-#define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
-                                           wait count mask */
-#define CICR3_LPF       (0x7ff << 0)    /* Lines per frame mask */
-#define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
-#define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
-#define CICR4_PCP       (1 << 22)       /* Pixel clock polarity */
-#define CICR4_HSP       (1 << 21)       /* Horizontal sync polarity */
-#define CICR4_VSP       (1 << 20)       /* Vertical sync polarity */
-#define CICR4_MCLK_EN   (1 << 19)       /* MCLK enable */
-#define CICR4_FR_RATE   (0x7 << 8)      /* Frame rate mask */
-#define CICR4_DIV       (0xff << 0)     /* Clock divisor mask */
-#define CISR_FTO        (1 << 15)       /* FIFO time-out */
-#define CISR_RDAV_2     (1 << 14)       /* Channel 2 receive data available */
-#define CISR_RDAV_1     (1 << 13)       /* Channel 1 receive data available */
-#define CISR_RDAV_0     (1 << 12)       /* Channel 0 receive data available */
-#define CISR_FEMPTY_2   (1 << 11)       /* Channel 2 FIFO empty */
-#define CISR_FEMPTY_1   (1 << 10)       /* Channel 1 FIFO empty */
-#define CISR_FEMPTY_0   (1 << 9)        /* Channel 0 FIFO empty */
-#define CISR_EOL        (1 << 8)        /* End of line */
-#define CISR_PAR_ERR    (1 << 7)        /* Parity error */
-#define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
-#define CISR_CDD        (1 << 5)        /* Camera interface disable done */
-#define CISR_SOF        (1 << 4)        /* Start of frame */
-#define CISR_EOF        (1 << 3)        /* End of frame */
-#define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
-#define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */
-#define CISR_IFO_0      (1 << 0)        /* FIFO overrun for Channel 0 */
-#define CIFR_FLVL2      (0x7f << 23)    /* FIFO 2 level mask */
-#define CIFR_FLVL1      (0x7f << 16)    /* FIFO 1 level mask */
-#define CIFR_FLVL0      (0xff << 8)     /* FIFO 0 level mask */
-#define CIFR_THL_0      (0x3 << 4)      /* Threshold Level for Channel 0 FIFO */
-#define CIFR_RESET_F    (1 << 3)        /* Reset input FIFOs */
-#define CIFR_FEN2       (1 << 2)        /* FIFO enable for channel 2 */
-#define CIFR_FEN1       (1 << 1)        /* FIFO enable for channel 1 */
-#define CIFR_FEN0       (1 << 0)        /* FIFO enable for channel 0 */
-#define SRAM_SIZE               0x40000 /* 4x64K  */
-#define SRAM_MEM_PHYS           0x5C000000
-#define IMPMCR          __REG(0x58000000) /* IM Power Management Control Reg */
-#define IMPMSR          __REG(0x58000008) /* IM Power Management Status Reg */
-#define IMPMCR_PC3              (0x3 << 22) /* Bank 3 Power Control */
-#define IMPMCR_PC3_RUN_MODE     (0x0 << 22) /*   Run mode */
-#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /*   Standby mode */
-#define IMPMCR_PC3_AUTO_MODE    (0x3 << 22) /*   Automatically controlled */
-#define IMPMCR_PC2              (0x3 << 20) /* Bank 2 Power Control */
-#define IMPMCR_PC2_RUN_MODE     (0x0 << 20) /*   Run mode */
-#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /*   Standby mode */
-#define IMPMCR_PC2_AUTO_MODE    (0x3 << 20) /*   Automatically controlled */
-#define IMPMCR_PC1              (0x3 << 18) /* Bank 1 Power Control */
-#define IMPMCR_PC1_RUN_MODE     (0x0 << 18) /*   Run mode */
-#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /*   Standby mode */
-#define IMPMCR_PC1_AUTO_MODE    (0x3 << 18) /*   Automatically controlled */
-#define IMPMCR_PC0              (0x3 << 16) /* Bank 0 Power Control */
-#define IMPMCR_PC0_RUN_MODE     (0x0 << 16) /*   Run mode */
-#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /*   Standby mode */
-#define IMPMCR_PC0_AUTO_MODE    (0x3 << 16) /*   Automatically controlled */
-#define IMPMCR_AW3              (1 << 11) /* Bank 3 Automatic Wake-up enable */
-#define IMPMCR_AW2              (1 << 10) /* Bank 2 Automatic Wake-up enable */
-#define IMPMCR_AW1              (1 << 9)  /* Bank 1 Automatic Wake-up enable */
-#define IMPMCR_AW0              (1 << 8)  /* Bank 0 Automatic Wake-up enable */
-#define IMPMCR_DST              (0xFF << 0) /* Delay Standby Time, ms */
-#define IMPMSR_PS3              (0x3 << 6) /* Bank 3 Power Status: */
-#define IMPMSR_PS3_RUN_MODE     (0x0 << 6) /*    Run mode */
-#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /*    Standby mode */
-#define IMPMSR_PS2              (0x3 << 4) /* Bank 2 Power Status: */
-#define IMPMSR_PS2_RUN_MODE     (0x0 << 4) /*    Run mode */
-#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /*    Standby mode */
-#define IMPMSR_PS1              (0x3 << 2) /* Bank 1 Power Status: */
-#define IMPMSR_PS1_RUN_MODE     (0x0 << 2) /*    Run mode */
-#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /*    Standby mode */
-#define IMPMSR_PS0              (0x3 << 0) /* Bank 0 Power Status: */
-#define IMPMSR_PS0_RUN_MODE     (0x0 << 0) /*    Run mode */
-#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /*    Standby mode */
-#endif
-/* PWRMODE register M field values */
-#define PWRMODE_IDLE            0x1
-#define PWRMODE_STANDBY         0x2
-#define PWRMODE_SLEEP           0x3
-#define PWRMODE_DEEPSLEEP       0x7
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
index 6ef1dd09970b..d83393e25273 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
@@ -365,4 +365,9 @@
 #define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_IN)
 #define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
+/*
+ * Handy routine to set GPIO alternate functions
+ */
+extern int pxa_gpio_mode( int gpio_mode );
 #endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 806ecfea44bf..77102d695cc7 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -49,6 +49,11 @@
 #define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
 #define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
+#define MDCNFG_DE0      (1 << 0)        /* SDRAM Bank 0 Enable */
+#define MDCNFG_DE1      (1 << 1)        /* SDRAM Bank 1 Enable */
+#define MDCNFG_DE2      (1 << 16)       /* SDRAM Bank 2 Enable */
+#define MDCNFG_DE3      (1 << 17)       /* SDRAM Bank 3 Enable */
 #define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
 #define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
 #define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
@@ -243,4 +248,11 @@
 #define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
 #define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
+/* PWRMODE register M field values */
+#define PWRMODE_IDLE            0x1
+#define PWRMODE_STANDBY         0x2
+#define PWRMODE_SLEEP           0x3
+#define PWRMODE_DEEPSLEEP       0x7
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index cbda4d35c421..6932720ba04e 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -48,6 +48,7 @@
 #define LCD_MONO_DSTN_8BPP      ((8  << 4) | LCD_TYPE_MONO_DSTN)
 #define LCD_COLOR_STN_8BPP      ((8  << 4) | LCD_TYPE_COLOR_STN)
 #define LCD_COLOR_DSTN_16BPP    ((16 << 4) | LCD_TYPE_COLOR_DSTN)
+#define LCD_COLOR_TFT_8BPP      ((8  << 4) | LCD_TYPE_COLOR_TFT)
 #define LCD_COLOR_TFT_16BPP     ((16 << 4) | LCD_TYPE_COLOR_TFT)
 #define LCD_COLOR_TFT_18BPP     ((18 << 4) | LCD_TYPE_COLOR_TFT)
 #define LCD_SMART_PANEL_8BPP    ((8  << 4) | LCD_TYPE_SMART_PANEL)
@@ -94,6 +95,10 @@ struct pxafb_mode_info {
         *    in pxa27x and pxa3xx, initialize them to the same value or
         *    the larger one will be used
         * 3. same to {rd,wr}_pulse_width
+         *
+         * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
+         * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
+         * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
         */
        unsigned        a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
        unsigned        a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
@@ -108,6 +113,7 @@ struct pxafb_mach_info {
        unsigned int num_modes;
        unsigned int    lcd_conn;
+        unsigned long   video_mem_size;
        u_int           fixed_modes:1,
                        cmap_inverse:1,
diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h
new file mode 100644
index 000000000000..e41b9d202b8c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h
@@ -0,0 +1,99 @@
+#ifndef __ASM_ARCH_REGS_AC97_H
+#define __ASM_ARCH_REGS_AC97_H
+/*
+ * AC97 Controller registers
+ */
+#define POCR            __REG(0x40500000)  /* PCM Out Control Register */
+#define POCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define POCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define PICR            __REG(0x40500004)  /* PCM In Control Register */
+#define PICR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define PICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define MCCR            __REG(0x40500008)  /* Mic In Control Register */
+#define MCCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define MCCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define GCR             __REG(0x4050000C)  /* Global Control Register */
+#ifdef CONFIG_PXA3xx
+#define GCR_CLKBPB      (1 << 31)       /* Internal clock enable */
+#endif
+#define GCR_nDMAEN      (1 << 24)       /* non DMA Enable */
+#define GCR_CDONE_IE    (1 << 19)       /* Command Done Interrupt Enable */
+#define GCR_SDONE_IE    (1 << 18)       /* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN  (1 << 9)        /* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN  (1 << 8)        /* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN  (1 << 5)        /* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN  (1 << 4)        /* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF  (1 << 3)        /* AC-link Shut Off */
+#define GCR_WARM_RST    (1 << 2)        /* AC97 Warm Reset */
+#define GCR_COLD_RST    (1 << 1)        /* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE         (1 << 0)        /* Codec GPI Interrupt Enable */
+#define POSR            __REG(0x40500010)  /* PCM Out Status Register */
+#define POSR_FIFOE      (1 << 4)        /* FIFO error */
+#define POSR_FSR        (1 << 2)        /* FIFO Service Request */
+#define PISR            __REG(0x40500014)  /* PCM In Status Register */
+#define PISR_FIFOE      (1 << 4)        /* FIFO error */
+#define PISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define PISR_FSR        (1 << 2)        /* FIFO Service Request */
+#define MCSR            __REG(0x40500018)  /* Mic In Status Register */
+#define MCSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MCSR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MCSR_FSR        (1 << 2)        /* FIFO Service Request */
+#define GSR             __REG(0x4050001C)  /* Global Status Register */
+#define GSR_CDONE       (1 << 19)       /* Command Done */
+#define GSR_SDONE       (1 << 18)       /* Status Done */
+#define GSR_RDCS        (1 << 15)       /* Read Completion Status */
+#define GSR_BIT3SLT12   (1 << 14)       /* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12   (1 << 13)       /* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12   (1 << 12)       /* Bit 1 of slot 12 */
+#define GSR_SECRES      (1 << 11)       /* Secondary Resume Interrupt */
+#define GSR_PRIRES      (1 << 10)       /* Primary Resume Interrupt */
+#define GSR_SCR         (1 << 9)        /* Secondary Codec Ready */
+#define GSR_PCR         (1 << 8)        /*  Primary Codec Ready */
+#define GSR_MCINT       (1 << 7)        /* Mic In Interrupt */
+#define GSR_POINT       (1 << 6)        /* PCM Out Interrupt */
+#define GSR_PIINT       (1 << 5)        /* PCM In Interrupt */
+#define GSR_ACOFFD      (1 << 3)        /* AC-link Shut Off Done */
+#define GSR_MOINT       (1 << 2)        /* Modem Out Interrupt */
+#define GSR_MIINT       (1 << 1)        /* Modem In Interrupt */
+#define GSR_GSCI        (1 << 0)        /* Codec GPI Status Change Interrupt */
+#define CAR             __REG(0x40500020)  /* CODEC Access Register */
+#define CAR_CAIP        (1 << 0)        /* Codec Access In Progress */
+#define PCDR            __REG(0x40500040)  /* PCM FIFO Data Register */
+#define MCDR            __REG(0x40500060)  /* Mic-in FIFO Data Register */
+#define MOCR            __REG(0x40500100)  /* Modem Out Control Register */
+#define MOCR_FEIE       (1 << 3)        /* FIFO Error */
+#define MOCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define MICR            __REG(0x40500108)  /* Modem In Control Register */
+#define MICR_FEIE       (1 << 3)        /* FIFO Error */
+#define MICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define MOSR            __REG(0x40500110)  /* Modem Out Status Register */
+#define MOSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MOSR_FSR        (1 << 2)        /* FIFO Service Request */
+#define MISR            __REG(0x40500118)  /* Modem In Status Register */
+#define MISR_FIFOE      (1 << 4)        /* FIFO error */
+#define MISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MISR_FSR        (1 << 2)        /* FIFO Service Request */
+#define MODR            __REG(0x40500140)  /* Modem FIFO Data Register */
+#define PAC_REG_BASE    __REG(0x40500200)  /* Primary Audio Codec */
+#define SAC_REG_BASE    __REG(0x40500300)  /* Secondary Audio Codec */
+#define PMC_REG_BASE    __REG(0x40500400)  /* Primary Modem Codec */
+#define SMC_REG_BASE    __REG(0x40500500)  /* Secondary Modem Codec */
+#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
index c689c4ea769c..f82dcea792d9 100644
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -12,27 +12,29 @@
 #define LCCR3           (0x00C) /* LCD Controller Control Register 3 */
 #define LCCR4           (0x010) /* LCD Controller Control Register 4 */
 #define LCCR5           (0x014) /* LCD Controller Control Register 5 */
-#define DFBR0           (0x020) /* DMA Channel 0 Frame Branch Register */
+#define LCSR            (0x038) /* LCD Controller Status Register 0 */
-#define DFBR1           (0x024) /* DMA Channel 1 Frame Branch Register */
+#define LCSR1           (0x034) /* LCD Controller Status Register 1 */
-#define LCSR            (0x038) /* LCD Controller Status Register */
 #define LIIDR           (0x03C) /* LCD Controller Interrupt ID Register */
 #define TMEDRGBR        (0x040) /* TMED RGB Seed Register */
 #define TMEDCR          (0x044) /* TMED Control Register */
+#define FBR0            (0x020) /* DMA Channel 0 Frame Branch Register */
+#define FBR1            (0x024) /* DMA Channel 1 Frame Branch Register */
+#define FBR2            (0x028) /* DMA Channel 2 Frame Branch Register */
+#define FBR3            (0x02C) /* DMA Channel 2 Frame Branch Register */
+#define FBR4            (0x030) /* DMA Channel 2 Frame Branch Register */
+#define FBR5            (0x110) /* DMA Channel 2 Frame Branch Register */
+#define FBR6            (0x114) /* DMA Channel 2 Frame Branch Register */
+#define OVL1C1          (0x050) /* Overlay 1 Control Register 1 */
+#define OVL1C2          (0x060) /* Overlay 1 Control Register 2 */
+#define OVL2C1          (0x070) /* Overlay 2 Control Register 1 */
+#define OVL2C2          (0x080) /* Overlay 2 Control Register 2 */
 #define CMDCR           (0x100) /* Command Control Register */
 #define PRSR            (0x104) /* Panel Read Status Register */
-#define LCCR3_1BPP      (0 << 24)
+#define LCCR3_BPP(x)    ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))
-#define LCCR3_2BPP      (1 << 24)
-#define LCCR3_4BPP      (2 << 24)
-#define LCCR3_8BPP      (3 << 24)
-#define LCCR3_16BPP     (4 << 24)
-#define LCCR3_18BPP     (5 << 24)
-#define LCCR3_18BPP_P   (6 << 24)
-#define LCCR3_19BPP     (7 << 24)
-#define LCCR3_19BPP_P   (1 << 29)
-#define LCCR3_24BPP     ((1 << 29) | (1 << 24))
-#define LCCR3_25BPP     ((1 << 29) | (2 << 24))
 #define LCCR3_PDFOR_0   (0 << 30)
 #define LCCR3_PDFOR_1   (1 << 30)
@@ -42,19 +44,16 @@
 #define LCCR4_PAL_FOR_0 (0 << 15)
 #define LCCR4_PAL_FOR_1 (1 << 15)
 #define LCCR4_PAL_FOR_2 (2 << 15)
+#define LCCR4_PAL_FOR_3 (3 << 15)
 #define LCCR4_PAL_FOR_MASK      (3 << 15)
 #define FDADR0          (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
-#define FSADR0          (0x204) /* DMA Channel 0 Frame Source Address Register */
-#define FIDR0           (0x208) /* DMA Channel 0 Frame ID Register */
-#define LDCMD0          (0x20C) /* DMA Channel 0 Command Register */
 #define FDADR1          (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
-#define FSADR1          (0x214) /* DMA Channel 1 Frame Source Address Register */
+#define FDADR2          (0x220) /* DMA Channel 2 Frame Descriptor Address Register */
-#define FIDR1           (0x218) /* DMA Channel 1 Frame ID Register */
+#define FDADR3          (0x230) /* DMA Channel 3 Frame Descriptor Address Register */
-#define LDCMD1          (0x21C) /* DMA Channel 1 Command Register */
+#define FDADR4          (0x240) /* DMA Channel 4 Frame Descriptor Address Register */
+#define FDADR5          (0x250) /* DMA Channel 5 Frame Descriptor Address Register */
 #define FDADR6          (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
-#define FSADR6          (0x264) /* DMA Channel 6 Frame Source Address Register */
-#define FIDR6           (0x268) /* DMA Channel 6 Frame ID Register */
 #define LCCR0_ENB       (1 << 0)        /* LCD Controller enable */
 #define LCCR0_CMS       (1 << 1)        /* Color/Monochrome Display Select */
@@ -126,9 +125,6 @@
 #define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
 #define LCCR3_PixClkDiv(Div)    (((Div) << FShft (LCCR3_PCD)))
-#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
-#define LCCR3_Bpp(Bpp)  (((Bpp) << FShft (LCCR3_BPP)))
 #define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
 #define LCCR3_Acb(Acb)  (((Acb) << FShft (LCCR3_ACB)))
@@ -157,8 +153,22 @@
 #define LCSR_RD_ST      (1 << 11)       /* read status */
 #define LCSR_CMD_INT    (1 << 12)       /* command interrupt */
+#define LCSR1_IU(x)     (1 << ((x) + 23)) /* Input FIFO underrun */
+#define LCSR1_BS(x)     (1 << ((x) + 15)) /* Branch Status */
+#define LCSR1_EOF(x)    (1 << ((x) + 7))  /* End of Frame Status */
+#define LCSR1_SOF(x)    (1 << ((x) - 1))  /* Start of Frame Status */
 #define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
+/* overlay control registers */
+#define OVLxC1_PPL(x)   ((((x) - 1) & 0x3ff) << 0)      /* Pixels Per Line */
+#define OVLxC1_LPO(x)   ((((x) - 1) & 0x3ff) << 10)     /* Number of Lines */
+#define OVLxC1_BPP(x)   (((x) & 0xf) << 20)     /* Bits Per Pixel */
+#define OVLxC1_OEN      (1 << 31)               /* Enable bit for Overlay */
+#define OVLxC2_XPOS(x)  (((x) & 0x3ff) << 0)    /* Horizontal Position */
+#define OVLxC2_YPOS(x)  (((x) & 0x3ff) << 10)   /* Vertical Position */
+#define OVL2C2_PFOR(x)  (((x) & 0x7) << 20)     /* Pixel Format */
 /* smartpanel related */
 #define PRSR_DATA(x)    ((x) & 0xff)    /* Panel Data */
 #define PRSR_A0         (1 << 8)        /* Read Data Source */
@@ -177,4 +187,11 @@
 #define SMART_CMD(x)    (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
 #define SMART_DAT(x)    (SMART_CMD_WRITE_DATA | ((x) & 0xff))
+/* SMART_DELAY() is introduced for software controlled delay primitive which
+ * can be inserted between command sequences, unused command 0x6 is used here
+ * and delay ranges from 0ms ~ 255ms
+ */
+#define SMART_CMD_DELAY         (0x6 << 9)
+#define SMART_DELAY(ms)         (SMART_CMD_DELAY | ((ms) & 0xff))
 #endif /* __ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h
new file mode 100644
index 000000000000..55aeb7fb72f6
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-uart.h
@@ -0,0 +1,143 @@
+#ifndef __ASM_ARCH_REGS_UART_H
+#define __ASM_ARCH_REGS_UART_H
+/*
+ * UARTs
+ */
+/* Full Function UART (FFUART) */
+#define FFUART          FFRBR
+#define FFRBR           __REG(0x40100000)  /* Receive Buffer Register (read only) */
+#define FFTHR           __REG(0x40100000)  /* Transmit Holding Register (write only) */
+#define FFIER           __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
+#define FFIIR           __REG(0x40100008)  /* Interrupt ID Register (read only) */
+#define FFFCR           __REG(0x40100008)  /* FIFO Control Register (write only) */
+#define FFLCR           __REG(0x4010000C)  /* Line Control Register (read/write) */
+#define FFMCR           __REG(0x40100010)  /* Modem Control Register (read/write) */
+#define FFLSR           __REG(0x40100014)  /* Line Status Register (read only) */
+#define FFMSR           __REG(0x40100018)  /* Modem Status Register (read only) */
+#define FFSPR           __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
+#define FFISR           __REG(0x40100020)  /* Infrared Selection Register (read/write) */
+#define FFDLL           __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH           __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+/* Bluetooth UART (BTUART) */
+#define BTUART          BTRBR
+#define BTRBR           __REG(0x40200000)  /* Receive Buffer Register (read only) */
+#define BTTHR           __REG(0x40200000)  /* Transmit Holding Register (write only) */
+#define BTIER           __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
+#define BTIIR           __REG(0x40200008)  /* Interrupt ID Register (read only) */
+#define BTFCR           __REG(0x40200008)  /* FIFO Control Register (write only) */
+#define BTLCR           __REG(0x4020000C)  /* Line Control Register (read/write) */
+#define BTMCR           __REG(0x40200010)  /* Modem Control Register (read/write) */
+#define BTLSR           __REG(0x40200014)  /* Line Status Register (read only) */
+#define BTMSR           __REG(0x40200018)  /* Modem Status Register (read only) */
+#define BTSPR           __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
+#define BTISR           __REG(0x40200020)  /* Infrared Selection Register (read/write) */
+#define BTDLL           __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH           __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+/* Standard UART (STUART) */
+#define STUART          STRBR
+#define STRBR           __REG(0x40700000)  /* Receive Buffer Register (read only) */
+#define STTHR           __REG(0x40700000)  /* Transmit Holding Register (write only) */
+#define STIER           __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
+#define STIIR           __REG(0x40700008)  /* Interrupt ID Register (read only) */
+#define STFCR           __REG(0x40700008)  /* FIFO Control Register (write only) */
+#define STLCR           __REG(0x4070000C)  /* Line Control Register (read/write) */
+#define STMCR           __REG(0x40700010)  /* Modem Control Register (read/write) */
+#define STLSR           __REG(0x40700014)  /* Line Status Register (read only) */
+#define STMSR           __REG(0x40700018)  /* Reserved */
+#define STSPR           __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
+#define STISR           __REG(0x40700020)  /* Infrared Selection Register (read/write) */
+#define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+/* Hardware UART (HWUART) */
+#define HWUART          HWRBR
+#define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
+#define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
+#define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
+#define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
+#define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
+#define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
+#define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
+#define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
+#define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
+#define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
+#define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
+#define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
+#define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
+#define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
+#define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
+#define IER_UUE         (1 << 6)        /* UART Unit Enable */
+#define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
+#define IER_RTIOE       (1 << 4)        /* Receiver Time Out Interrupt Enable */
+#define IER_MIE         (1 << 3)        /* Modem Interrupt Enable */
+#define IER_RLSE        (1 << 2)        /* Receiver Line Status Interrupt Enable */
+#define IER_TIE         (1 << 1)        /* Transmit Data request Interrupt Enable */
+#define IER_RAVIE       (1 << 0)        /* Receiver Data Available Interrupt Enable */
+#define IIR_FIFOES1     (1 << 7)        /* FIFO Mode Enable Status */
+#define IIR_FIFOES0     (1 << 6)        /* FIFO Mode Enable Status */
+#define IIR_TOD         (1 << 3)        /* Time Out Detected */
+#define IIR_IID2        (1 << 2)        /* Interrupt Source Encoded */
+#define IIR_IID1        (1 << 1)        /* Interrupt Source Encoded */
+#define IIR_IP          (1 << 0)        /* Interrupt Pending (active low) */
+#define FCR_ITL2        (1 << 7)        /* Interrupt Trigger Level */
+#define FCR_ITL1        (1 << 6)        /* Interrupt Trigger Level */
+#define FCR_RESETTF     (1 << 2)        /* Reset Transmitter FIFO */
+#define FCR_RESETRF     (1 << 1)        /* Reset Receiver FIFO */
+#define FCR_TRFIFOE     (1 << 0)        /* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1       (0)
+#define FCR_ITL_8       (FCR_ITL1)
+#define FCR_ITL_16      (FCR_ITL2)
+#define FCR_ITL_32      (FCR_ITL2|FCR_ITL1)
+#define LCR_DLAB        (1 << 7)        /* Divisor Latch Access Bit */
+#define LCR_SB          (1 << 6)        /* Set Break */
+#define LCR_STKYP       (1 << 5)        /* Sticky Parity */
+#define LCR_EPS         (1 << 4)        /* Even Parity Select */
+#define LCR_PEN         (1 << 3)        /* Parity Enable */
+#define LCR_STB         (1 << 2)        /* Stop Bit */
+#define LCR_WLS1        (1 << 1)        /* Word Length Select */
+#define LCR_WLS0        (1 << 0)        /* Word Length Select */
+#define LSR_FIFOE       (1 << 7)        /* FIFO Error Status */
+#define LSR_TEMT        (1 << 6)        /* Transmitter Empty */
+#define LSR_TDRQ        (1 << 5)        /* Transmit Data Request */
+#define LSR_BI          (1 << 4)        /* Break Interrupt */
+#define LSR_FE          (1 << 3)        /* Framing Error */
+#define LSR_PE          (1 << 2)        /* Parity Error */
+#define LSR_OE          (1 << 1)        /* Overrun Error */
+#define LSR_DR          (1 << 0)        /* Data Ready */
+#define MCR_LOOP        (1 << 4)
+#define MCR_OUT2        (1 << 3)        /* force MSR_DCD in loopback mode */
+#define MCR_OUT1        (1 << 2)        /* force MSR_RI in loopback mode */
+#define MCR_RTS         (1 << 1)        /* Request to Send */
+#define MCR_DTR         (1 << 0)        /* Data Terminal Ready */
+#define MSR_DCD         (1 << 7)        /* Data Carrier Detect */
+#define MSR_RI          (1 << 6)        /* Ring Indicator */
+#define MSR_DSR         (1 << 5)        /* Data Set Ready */
+#define MSR_CTS         (1 << 4)        /* Clear To Send */
+#define MSR_DDCD        (1 << 3)        /* Delta Data Carrier Detect */
+#define MSR_TERI        (1 << 2)        /* Trailing Edge Ring Indicator */
+#define MSR_DDSR        (1 << 1)        /* Delta Data Set Ready */
+#define MSR_DCTS        (1 << 0)        /* Delta Clear To Send */
+/*
+ * IrSR (Infrared Selection Register)
+ */
+#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
+#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
+#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
+#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
+#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
+#endif /* __ASM_ARCH_REGS_UART_H */
diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h
index b05fc6683c47..af6760a50e1a 100644
--- a/arch/arm/mach-pxa/include/mach/timex.h
+++ b/arch/arm/mach-pxa/include/mach/timex.h
@@ -10,6 +10,14 @@
 * published by the Free Software Foundation.
 */
+/* Various drivers are still using the constant of CLOCK_TICK_RATE, for
+ * those drivers to at least work, the definition is provided here.
+ *
+ * NOTE: this is no longer accurate when multiple processors and boards
+ * are selected, newer drivers should not depend on this any more.  Use
+ * either the clocksource/clockevent or get this at run-time by calling
+ * get_clock_tick_rate() (as defined in generic.c).
+ */
 #if defined(CONFIG_PXA25x)
 /* PXA250/210 timer base */
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 21e3e890af98..f4b029c03957 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -10,7 +10,7 @@
 */
 #include <linux/serial_reg.h>
-#include <mach/pxa-regs.h>
+#include <mach/regs-uart.h>
 #include <asm/mach-types.h>
 #define __REG(x)       ((volatile unsigned long *)x)
@@ -35,7 +35,7 @@ static inline void flush(void)
 static inline void arch_decomp_setup(void)
 {
-        if (machine_is_littleton())
+        if (machine_is_littleton() || machine_is_intelmote2())
                UART = STUART;
 }
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index b4d00aba0e31..31da7f3c06f6 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -20,8 +20,13 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/smc91x.h>
+#include <linux/i2c.h>
+#include <linux/leds.h>
+#include <linux/mfd/da903x.h>
+#include <linux/i2c/max732x.h>
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -36,10 +41,10 @@
 #include <mach/pxa-regs.h>
 #include <mach/mfp-pxa300.h>
-#include <mach/gpio.h>
 #include <mach/pxafb.h>
 #include <mach/ssp.h>
 #include <mach/pxa2xx_spi.h>
+#include <mach/i2c.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxa3xx_nand.h>
 #include <mach/littleton.h>
@@ -314,6 +319,73 @@ static void __init littleton_init_nand(void)
 static inline void littleton_init_nand(void) {}
 #endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct led_info littleton_da9034_leds[] = {
+        [0] = {
+                .name   = "littleton:keypad1",
+                .flags  = DA9034_LED_RAMP,
+        },
+        [1] = {
+                .name   = "littleton:keypad2",
+                .flags  = DA9034_LED_RAMP,
+        },
+        [2] = {
+                .name   = "littleton:vibra",
+                .flags  = 0,
+        },
+};
+static struct da903x_subdev_info littleton_da9034_subdevs[] = {
+        {
+                .name           = "da903x-led",
+                .id             = DA9034_ID_LED_1,
+                .platform_data  = &littleton_da9034_leds[0],
+        }, {
+                .name           = "da903x-led",
+                .id             = DA9034_ID_LED_2,
+                .platform_data  = &littleton_da9034_leds[1],
+        }, {
+                .name           = "da903x-led",
+                .id             = DA9034_ID_VIBRA,
+                .platform_data  = &littleton_da9034_leds[2],
+        }, {
+                .name           = "da903x-backlight",
+                .id             = DA9034_ID_WLED,
+        },
+};
+static struct da903x_platform_data littleton_da9034_info = {
+        .num_subdevs    = ARRAY_SIZE(littleton_da9034_subdevs),
+        .subdevs        = littleton_da9034_subdevs,
+};
+static struct max732x_platform_data littleton_max7320_info = {
+        .gpio_base      = EXT0_GPIO_BASE,
+};
+static struct i2c_board_info littleton_i2c_info[] = {
+        [0] = {
+                .type           = "da9034",
+                .addr           = 0x34,
+                .platform_data  = &littleton_da9034_info,
+                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)),
+        },
+        [1] = {
+                .type           = "max7320",
+                .addr           = 0x50,
+                .platform_data  = &littleton_max7320_info,
+        },
+};
+static void __init littleton_init_i2c(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(littleton_i2c_info));
+}
+#else
+static inline void littleton_init_i2c(void) {}
+#endif /* CONFIG_I2C_PXA || CONFIG_I2C_PXA_MODULE */
 static void __init littleton_init(void)
 {
        /* initialize MFP configurations */
@@ -326,6 +398,7 @@ static void __init littleton_init(void)
        platform_device_register(&smc91x_device);
        littleton_init_spi();
+        littleton_init_i2c();
        littleton_init_lcd();
        littleton_init_keypad();
        littleton_init_nand();
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 519138bc5f85..21b821e1a60d 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -123,6 +123,10 @@ static unsigned long magician_pin_config[] __initdata = {
        GPIO107_GPIO,   /* DS1WM_IRQ */
        GPIO108_GPIO,   /* GSM_READY */
        GPIO115_GPIO,   /* nPEN_IRQ */
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
 };
 /*
@@ -332,8 +336,7 @@ static struct pxafb_mach_info toppoly_info = {
        .modes           = toppoly_modes,
        .num_modes       = 1,
        .fixed_modes     = 1,
-        .lccr0           = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lcd_conn       = LCD_COLOR_TFT_16BPP,
-        .lccr3           = LCCR3_PixRsEdg,
        .pxafb_lcd_power = toppoly_lcd_power,
 };
@@ -341,8 +344,8 @@ static struct pxafb_mach_info samsung_info = {
        .modes           = samsung_modes,
        .num_modes       = 1,
        .fixed_modes     = 1,
-        .lccr0           = LCCR0_LDDALT | LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lcd_conn        = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |\
-        .lccr3           = LCCR3_PixFlEdg,
+                           LCD_ALTERNATE_MAPPING,
        .pxafb_lcd_power = samsung_lcd_power,
 };
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index f2c7ad8f2b6b..5f224968043c 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -128,6 +128,10 @@ static unsigned long mainstone_pin_config[] = {
        GPIO108_KP_MKOUT_5,
        GPIO96_KP_MKOUT_6,
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
        /* GPIO */
        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
 };
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 2061c00c8ead..33626de8cbf6 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -38,12 +38,13 @@ struct gpio_desc {
        unsigned        valid           : 1;
        unsigned        can_wakeup      : 1;
        unsigned        keypad_gpio     : 1;
+        unsigned        dir_inverted    : 1;
        unsigned int    mask; /* bit mask in PWER or PKWR */
+        unsigned int    mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
        unsigned long   config;
 };
 static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
-static int gpio_nr;
 static unsigned long gpdr_lpm[4];
@@ -54,7 +55,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
        int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
        int shft = (gpio & 0xf) << 1;
        int fn = MFP_AF(c);
-        int dir = c & MFP_DIR_OUT;
+        int is_out = (c & MFP_DIR_OUT) ? 1 : 0;
        if (fn > 3)
                return -EINVAL;
@@ -68,7 +69,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
        else
                GAFR_U(bank) = gafr;
-        if (dir == MFP_DIR_OUT)
+        if (is_out ^ gpio_desc[gpio].dir_inverted)
                GPDR(gpio) |= mask;
        else
                GPDR(gpio) &= ~mask;
@@ -77,11 +78,11 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
        switch (c & MFP_LPM_STATE_MASK) {
        case MFP_LPM_DRIVE_HIGH:
                PGSR(bank) |= mask;
-                dir = MFP_DIR_OUT;
+                is_out = 1;
                break;
        case MFP_LPM_DRIVE_LOW:
                PGSR(bank) &= ~mask;
-                dir = MFP_DIR_OUT;
+                is_out = 1;
                break;
        case MFP_LPM_DEFAULT:
                break;
@@ -92,7 +93,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
                break;
        }
-        if (dir == MFP_DIR_OUT)
+        if (is_out ^ gpio_desc[gpio].dir_inverted)
                gpdr_lpm[bank] |= mask;
        else
                gpdr_lpm[bank] &= ~mask;
@@ -106,7 +107,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
                return -EINVAL;
        }
-        if ((c & MFP_LPM_CAN_WAKEUP) && (dir == MFP_DIR_OUT)) {
+        if ((c & MFP_LPM_CAN_WAKEUP) && is_out) {
                pr_warning("%s: output GPIO%d unable to wakeup\n",
                                __func__, gpio);
                return -EINVAL;
@@ -169,7 +170,7 @@ void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
 int gpio_set_wake(unsigned int gpio, unsigned int on)
 {
        struct gpio_desc *d;
-        unsigned long c;
+        unsigned long c, mux_taken;
        if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
                return -EINVAL;
@@ -183,9 +184,13 @@ int gpio_set_wake(unsigned int gpio, unsigned int on)
        if (d->keypad_gpio)
                return -EINVAL;
+        mux_taken = (PWER & d->mux_mask) & (~d->mask);
+        if (on && mux_taken)
+                return -EBUSY;
        if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
                if (on) {
-                        PWER |= d->mask;
+                        PWER = (PWER & ~d->mux_mask) | d->mask;
                        if (c & MFP_LPM_EDGE_RISE)
                                PRER |= d->mask;
@@ -210,7 +215,7 @@ static void __init pxa25x_mfp_init(void)
 {
        int i;
-        for (i = 0; i <= 84; i++)
+        for (i = 0; i <= pxa_last_gpio; i++)
                gpio_desc[i].valid = 1;
        for (i = 0; i <= 15; i++) {
@@ -218,7 +223,11 @@ static void __init pxa25x_mfp_init(void)
                gpio_desc[i].mask = GPIO_bit(i);
        }
-        gpio_nr = 85;
+        /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the
+         * direction bit inverted in GPDR2. See PXA26x DM 4.1.1.
+         */
+        for (i = 86; i <= pxa_last_gpio; i++)
+                gpio_desc[i].dir_inverted = 1;
 }
 #else
 static inline void pxa25x_mfp_init(void) {}
@@ -251,11 +260,27 @@ int keypad_set_wake(unsigned int on)
        return 0;
 }
+#define PWER_WEMUX2_GPIO38      (1 << 16)
+#define PWER_WEMUX2_GPIO53      (2 << 16)
+#define PWER_WEMUX2_GPIO40      (3 << 16)
+#define PWER_WEMUX2_GPIO36      (4 << 16)
+#define PWER_WEMUX2_MASK        (7 << 16)
+#define PWER_WEMUX3_GPIO31      (1 << 19)
+#define PWER_WEMUX3_GPIO113     (2 << 19)
+#define PWER_WEMUX3_MASK        (3 << 19)
+#define INIT_GPIO_DESC_MUXED(mux, gpio)                         \
+do {                                                            \
+        gpio_desc[(gpio)].can_wakeup = 1;                       \
+        gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio;  \
+        gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK;     \
+} while (0)
 static void __init pxa27x_mfp_init(void)
 {
        int i, gpio;
-        for (i = 0; i <= 120; i++) {
+        for (i = 0; i <= pxa_last_gpio; i++) {
                /* skip GPIO2, 5, 6, 7, 8, they are not
                 * valid pins allow configuration
                 */
@@ -286,7 +311,12 @@ static void __init pxa27x_mfp_init(void)
        gpio_desc[35].can_wakeup = 1;
        gpio_desc[35].mask = PWER_WE35;
-        gpio_nr = 121;
+        INIT_GPIO_DESC_MUXED(WEMUX3, 31);
+        INIT_GPIO_DESC_MUXED(WEMUX3, 113);
+        INIT_GPIO_DESC_MUXED(WEMUX2, 38);
+        INIT_GPIO_DESC_MUXED(WEMUX2, 53);
+        INIT_GPIO_DESC_MUXED(WEMUX2, 40);
+        INIT_GPIO_DESC_MUXED(WEMUX2, 36);
 }
 #else
 static inline void pxa27x_mfp_init(void) {}
@@ -300,7 +330,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state)
 {
        int i;
-        for (i = 0; i <= gpio_to_bank(gpio_nr); i++) {
+        for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
                saved_gafr[0][i] = GAFR_L(i);
                saved_gafr[1][i] = GAFR_U(i);
@@ -315,7 +345,7 @@ static int pxa2xx_mfp_resume(struct sys_device *d)
 {
        int i;
-        for (i = 0; i <= gpio_to_bank(gpio_nr); i++) {
+        for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
                GAFR_L(i) = saved_gafr[0][i];
                GAFR_U(i) = saved_gafr[1][i];
                GPDR(i * 32) = saved_gpdr[i];
@@ -348,7 +378,7 @@ static int __init pxa2xx_mfp_init(void)
                pxa27x_mfp_init();
        /* initialize gafr_run[], pgsr_lpm[] from existing values */
-        for (i = 0; i <= gpio_to_bank(gpio_nr); i++)
+        for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
                gpdr_lpm[i] = GPDR(i * 32);
        return sysdev_class_register(&pxa2xx_mfp_sysclass);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 782903fe9c6c..2b427e015b6f 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -34,7 +34,7 @@
 #include <linux/irq.h>
 #include <linux/pda_power.h>
 #include <linux/power_supply.h>
-#include <linux/wm97xx.h>
+#include <linux/wm97xx_batt.h>
 #include <linux/mtd/physmap.h>
 #include <asm/mach-types.h>
@@ -46,6 +46,9 @@
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
+#include <mach/i2c.h>
+#include <mach/camera.h>
+#include <media/soc_camera.h>
 #include <mach/mioa701.h>
@@ -54,10 +57,11 @@
 static unsigned long mioa701_pin_config[] = {
        /* Mio global */
-        MIO_CFG_OUT(GPIO9_CHARGE_nEN, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO9_CHARGE_EN, AF0, DRIVE_LOW),
        MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW),
        MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH),
        MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH),
+        MIO_CFG_IN(GPIO80_MAYBE_CHARGE_VDROP, AF0),
        /* Backlight PWM 0 */
        GPIO16_PWM0_OUT,
@@ -74,7 +78,7 @@ static unsigned long mioa701_pin_config[] = {
        MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW),
        /* USB */
-        MIO_CFG_IN(GPIO13_USB_DETECT, AF0),
+        MIO_CFG_IN(GPIO13_nUSB_DETECT, AF0),
        MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW),
        /* LCD */
@@ -98,12 +102,29 @@ static unsigned long mioa701_pin_config[] = {
        GPIO75_LCD_LCLK,
        GPIO76_LCD_PCLK,
+        /* QCI */
+        GPIO12_CIF_DD_7,
+        GPIO17_CIF_DD_6,
+        GPIO50_CIF_DD_3,
+        GPIO51_CIF_DD_2,
+        GPIO52_CIF_DD_4,
+        GPIO53_CIF_MCLK,
+        GPIO54_CIF_PCLK,
+        GPIO55_CIF_DD_1,
+        GPIO81_CIF_DD_0,
+        GPIO82_CIF_DD_5,
+        GPIO84_CIF_FV,
+        GPIO85_CIF_LV,
        /* Bluetooth */
+        MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0),
        GPIO44_BTUART_CTS,
        GPIO42_BTUART_RXD,
        GPIO45_BTUART_RTS,
        GPIO43_BTUART_TXD,
        MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO77_BT_UNKNOWN1, AF0, DRIVE_HIGH),
+        MIO_CFG_OUT(GPIO86_BT_MAYBE_nRESET, AF0, DRIVE_HIGH),
        /* GPS */
        MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW),
@@ -151,16 +172,16 @@ static unsigned long mioa701_pin_config[] = {
        GPIO104_KP_MKOUT_1,
        GPIO105_KP_MKOUT_2,
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
        /* Unknown */
-        MFP_CFG_IN(GPIO14, AF0),
        MFP_CFG_IN(GPIO20, AF0),
        MFP_CFG_IN(GPIO21, AF0),
        MFP_CFG_IN(GPIO33, AF0),
        MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH),
        MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH),
-        MFP_CFG_OUT(GPIO77, AF0, DRIVE_HIGH),
-        MFP_CFG_IN(GPIO80, AF0),
-        MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH),
        MFP_CFG_IN(GPIO96, AF0),
        MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH),
 };
@@ -407,7 +428,7 @@ static void udc_power_command(int cmd)
 static int is_usb_connected(void)
 {
-        return !!gpio_get_value(GPIO13_USB_DETECT);
+        return !gpio_get_value(GPIO13_nUSB_DETECT);
 }
 static struct pxa2xx_udc_mach_info mioa701_udc_info = {
@@ -659,13 +680,19 @@ static char *supplicants[] = {
        "mioa701_battery"
 };
+static int is_ac_connected(void)
+{
+        return gpio_get_value(GPIO96_AC_DETECT);
+}
 static void mioa701_set_charge(int flags)
 {
-        gpio_set_value(GPIO9_CHARGE_nEN, !flags);
+        gpio_set_value(GPIO9_CHARGE_EN, (flags == PDA_POWER_CHARGE_USB));
 }
 static struct pda_power_pdata power_pdata = {
-        .is_ac_online   = is_usb_connected,
+        .is_ac_online   = is_ac_connected,
+        .is_usb_online  = is_usb_connected,
        .set_charge = mioa701_set_charge,
        .supplied_to = supplicants,
        .num_supplicants = ARRAY_SIZE(supplicants),
@@ -674,8 +701,15 @@ static struct pda_power_pdata power_pdata = {
 static struct resource power_resources[] = {
        [0] = {
                .name   = "ac",
-                .start  = gpio_to_irq(GPIO13_USB_DETECT),
+                .start  = gpio_to_irq(GPIO96_AC_DETECT),
-                .end    = gpio_to_irq(GPIO13_USB_DETECT),
+                .end    = gpio_to_irq(GPIO96_AC_DETECT),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
+                IORESOURCE_IRQ_LOWEDGE,
+        },
+        [1] = {
+                .name   = "usb",
+                .start  = gpio_to_irq(GPIO13_nUSB_DETECT),
+                .end    = gpio_to_irq(GPIO13_nUSB_DETECT),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                IORESOURCE_IRQ_LOWEDGE,
        },
@@ -691,120 +725,43 @@ static struct platform_device power_dev = {
        },
 };
-#if defined(CONFIG_PDA_POWER) && defined(CONFIG_TOUCHSCREEN_WM97XX)
+static struct wm97xx_batt_info mioa701_battery_data = {
-static struct wm97xx *battery_wm;
+        .batt_aux       = WM97XX_AUX_ID1,
+        .temp_aux       = -1,
-static enum power_supply_property battery_props[] = {
+        .charge_gpio    = -1,
-        POWER_SUPPLY_PROP_STATUS,
+        .min_voltage    = 0xc00,
-        POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+        .max_voltage    = 0xfc0,
-        POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+        .batt_tech      = POWER_SUPPLY_TECHNOLOGY_LION,
-        POWER_SUPPLY_PROP_VOLTAGE_NOW,
+        .batt_div       = 1,
-        POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,   /* Necessary for apm */
+        .batt_mult      = 1,
+        .batt_name      = "mioa701_battery",
 };
-static int get_battery_voltage(void)
+/*
-{
+ * Camera interface
-        int adc = -1;
+ */
+struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
-        if (battery_wm)
+        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
-                adc = wm97xx_read_aux_adc(battery_wm, WM97XX_AUX_ID1);
+                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
-        return adc;
+        .mclk_10khz = 5000,
-}
-static int get_battery_status(struct power_supply *b)
-{
-        int status;
-        if (is_usb_connected())
-                status = POWER_SUPPLY_STATUS_CHARGING;
-        else
-                status = POWER_SUPPLY_STATUS_DISCHARGING;
-        return status;
-}
-static int get_property(struct power_supply *b,
-                        enum power_supply_property psp,
-                        union power_supply_propval *val)
-{
-        int rc = 0;
-        switch (psp) {
-        case POWER_SUPPLY_PROP_STATUS:
-                val->intval = get_battery_status(b);
-                break;
-        case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
-                val->intval = 0xfd0;
-                break;
-        case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
-                val->intval = 0xc00;
-                break;
-        case POWER_SUPPLY_PROP_VOLTAGE_NOW:
-                val->intval = get_battery_voltage();
-                break;
-        case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
-                val->intval = 100;
-                break;
-        default:
-                val->intval = -1;
-                rc = -1;
-        }
-        return rc;
 };
-static struct power_supply battery_ps = {
+static struct soc_camera_link iclink = {
-        .name = "mioa701_battery",
+        .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */
-        .type = POWER_SUPPLY_TYPE_BATTERY,
-        .get_property = get_property,
-        .properties = battery_props,
-        .num_properties = ARRAY_SIZE(battery_props),
 };
-static int battery_probe(struct platform_device *pdev)
+/* Board I2C devices. */
-{
+static struct i2c_board_info __initdata mioa701_i2c_devices[] = {
-        struct wm97xx *wm = platform_get_drvdata(pdev);
+        {
-        int rc;
+                /* Must initialize before the camera(s) */
+                I2C_BOARD_INFO("mt9m111", 0x5d),
-        battery_wm = wm;
+                .platform_data = &iclink,
-        rc = power_supply_register(NULL, &battery_ps);
-        if (rc)
-                dev_err(&pdev->dev,
-                "Could not register mioa701 battery -> %d\n", rc);
-        return rc;
-}
-static int battery_remove(struct platform_device *pdev)
-{
-        battery_wm = NULL;
-        return 0;
-}
-static struct platform_driver mioa701_battery_driver = {
-        .driver = {
-                .name = "wm97xx-battery",
        },
-        .probe = battery_probe,
-        .remove = battery_remove
 };
-static int __init mioa701_battery_init(void)
+struct i2c_pxa_platform_data i2c_pdata = {
-{
+        .fast_mode = 1,
-        int rc;
+};
-        rc = platform_driver_register(&mioa701_battery_driver);
-        if (rc)
-                printk(KERN_ERR "Could not register mioa701 battery driver\n");
-        return rc;
-}
-#else
-static int __init mioa701_battery_init(void)
-{
-        return 0;
-}
-#endif
 /*
 * Mio global
@@ -851,17 +808,17 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
        mioa701_machine_exit();
-        gpio_set_value(GPIO18_POWEROFF, 1);
+        arm_machine_restart('s');
 }
 static void mioa701_restart(char c)
 {
        mioa701_machine_exit();
-        arm_machine_restart(c);
+        arm_machine_restart('s');
 }
 struct gpio_ress global_gpios[] = {
-        MIO_GPIO_OUT(GPIO9_CHARGE_nEN, 1, "Charger enable"),
+        MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"),
        MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"),
        MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power")
 };
@@ -879,12 +836,16 @@ static void __init mioa701_machine_init(void)
        set_pxa_fb_info(&mioa701_pxafb_info);
        pxa_set_mci_info(&mioa701_mci_info);
        pxa_set_keypad_info(&mioa701_keypad_info);
+        wm97xx_bat_set_pdata(&mioa701_battery_data);
        udc_init();
        pm_power_off = mioa701_poweroff;
        arm_pm_restart = mioa701_restart;
        platform_add_devices(devices, ARRAY_SIZE(devices));
        gsm_init();
-        mioa701_battery_init();
+        pxa_set_i2c_info(&i2c_pdata);
+        pxa_set_camera_info(&mioa701_pxacamera_platform_data);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices));
 }
 static void mioa701_machine_exit(void)
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index b36cec5c9eed..34841c72815f 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -55,6 +55,10 @@ static unsigned long pcm990_pin_config[] __initdata = {
        GPIO89_USBH1_PEN,
        /* PWM0 */
        GPIO16_PWM0_OUT,
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
 };
 /*
@@ -100,8 +104,7 @@ static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
 static struct pxafb_mach_info pcm990_fbinfo __initdata = {
        .modes                  = &fb_info_sharp_lq084v1dg21,
        .num_modes              = 1,
-        .lccr0                  = LCCR0_PAS,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-        .lccr3                  = LCCR3_PCP,
        .pxafb_lcd_power        = pcm990_lcd_power,
 };
 #elif defined(CONFIG_PCM990_DISPLAY_NEC)
@@ -123,8 +126,7 @@ struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
 static struct pxafb_mach_info pcm990_fbinfo __initdata = {
        .modes                  = &fb_info_nec_nl6448bc20_18d,
        .num_modes              = 1,
-        .lccr0                  = LCCR0_Act,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-        .lccr3                  = LCCR3_PixFlEdg,
        .pxafb_lcd_power        = pcm990_lcd_power,
 };
 #endif
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 2e3bd8b1523b..ae88855bf974 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -20,6 +20,7 @@
 #include <linux/fb.h>
 #include <linux/pm.h>
 #include <linux/delay.h>
+#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -413,9 +414,40 @@ static struct pxafb_mach_info poodle_fb_info = {
        .lcd_conn       = LCD_COLOR_TFT_16BPP,
 };
+static struct mtd_partition sharpsl_rom_parts[] = {
+        {
+                .name   ="Boot PROM Filesystem",
+                .offset = 0x00120000,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data sharpsl_rom_data = {
+        .width          = 2,
+        .nr_parts       = ARRAY_SIZE(sharpsl_rom_parts),
+        .parts          = sharpsl_rom_parts,
+};
+static struct resource sharpsl_rom_resources[] = {
+        {
+                .start  = 0x00000000,
+                .end    = 0x007fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device sharpsl_rom_device = {
+        .name   = "physmap-flash",
+        .id     = -1,
+        .resource = sharpsl_rom_resources,
+        .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
+        .dev.platform_data = &sharpsl_rom_data,
+};
 static struct platform_device *devices[] __initdata = {
        &poodle_locomo_device,
        &poodle_scoop_device,
+        &sharpsl_rom_device,
 };
 static void poodle_poweroff(void)
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c
index 74e2ead8cee8..3ca7ffc6904b 100644
--- a/arch/arm/mach-pxa/pwm.c
+++ b/arch/arm/mach-pxa/pwm.c
@@ -173,7 +173,7 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev,
                return ERR_PTR(-ENOMEM);
        }
-        pwm->clk = clk_get(&pdev->dev, "PWMCLK");
+        pwm->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(pwm->clk)) {
                ret = PTR_ERR(pwm->clk);
                goto err_free;
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 25d17a1dab78..6c57522e2469 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -36,12 +36,6 @@
 #include "devices.h"
 #include "clock.h"
-int cpu_is_pxa26x(void)
-{
-        return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0);
-}
-EXPORT_SYMBOL_GPL(cpu_is_pxa26x);
 /*
 * Various clock factors driven by the CCCR register.
 */
@@ -167,36 +161,51 @@ static const struct clkops clk_pxa25x_gpio11_ops = {
 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 */
-static struct clk pxa25x_hwuart_clk =
+static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
-        INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
-;
+static struct clk_lookup pxa25x_hwuart_clkreg =
+        INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
 /*
 * PXA 2xx clock declarations.
 */
-static struct clk pxa25x_clks[] = {
+static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
-        INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
+static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
-        INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
+static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
-        INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
+static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1);
-        INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
+static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5);
-        INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
+static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
-        INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL),
+static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
-        INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL),
+static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0);
-        INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
+static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0);
-        INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
+static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0);
+static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
-        INIT_CKEN("SSPCLK",  SSP, 3686400, 0, &pxa25x_device_ssp.dev),
+static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0);
-        INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
+static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
-        INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
+static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
-        INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
+static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0);
-        INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
+static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0);
+static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0);
-        INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
+static struct clk_lookup pxa25x_clkregs[] = {
-        /*
+        INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
-        INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
+        INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
-        */
+        INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
-        INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
+        INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
+        INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
+        INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
+        INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
+        INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
+        INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
+        INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
+        INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
+        INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
+        INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
+        INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
+        INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
+        INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
 };
 #ifdef CONFIG_PM
@@ -304,13 +313,21 @@ void __init pxa25x_init_irq(void)
        pxa_init_gpio(85, pxa25x_set_wake);
 }
+#ifdef CONFIG_CPU_PXA26x
+void __init pxa26x_init_irq(void)
+{
+        pxa_init_irq(32, pxa25x_set_wake);
+        pxa_init_gpio(90, pxa25x_set_wake);
+}
+#endif
 static struct platform_device *pxa25x_devices[] __initdata = {
        &pxa25x_device_udc,
        &pxa_device_ffuart,
        &pxa_device_btuart,
        &pxa_device_stuart,
        &pxa_device_i2s,
-        &pxa_device_rtc,
+        &sa1100_device_rtc,
        &pxa25x_device_ssp,
        &pxa25x_device_nssp,
        &pxa25x_device_assp,
@@ -336,7 +353,7 @@ static int __init pxa25x_init(void)
                reset_status = RCSR;
-                clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
+                clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
                if ((ret = pxa_init_dma(16)))
                        return ret;
@@ -356,8 +373,8 @@ static int __init pxa25x_init(void)
        }
        /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
-        if (cpu_is_pxa255() || cpu_is_pxa26x()) {
+        if (cpu_is_pxa255()) {
-                clks_register(&pxa25x_hwuart_clk, 1);
+                clks_register(&pxa25x_hwuart_clkreg, 1);
                ret = platform_device_register(&pxa_device_hwuart);
        }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 3e4ab2279c99..411bec54fdc4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -144,40 +144,59 @@ static const struct clkops clk_pxa27x_lcd_ops = {
        .getrate        = clk_pxa27x_lcd_getrate,
 };
-static struct clk pxa27x_clks[] = {
+static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
-        INIT_CK("LCDCLK", LCD,    &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
+static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
-        INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
+static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
+static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
-        INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
+static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
-        INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
+static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
-        INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
+static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
+static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
-        INIT_CKEN("I2SCLK",  I2S,  14682000, 0, &pxa_device_i2s.dev),
+static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
-        INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
+static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
-        INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa27x_device_udc.dev),
+static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
-        INIT_CKEN("MMCCLK",  MMC,  19500000, 0, &pxa_device_mci.dev),
+static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
-        INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
+static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
+static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
-        INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
+static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
-        INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
+static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
-        INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
+static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
+static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
-        INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
+static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
-        INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
+static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
-        INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
+static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
-        INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
+static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
-        INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
+static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
+static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
-        INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
+static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
-        INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
+static struct clk_lookup pxa27x_clkregs[] = {
-        /*
+        INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
-        INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
+        INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
-        INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
+        INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
-        INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
+        INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
-        INIT_CKEN("IMCLK",   IM,   0, 0, NULL),
+        INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
-        INIT_CKEN("MEMCLK",  MEMC, 0, 0, NULL),
+        INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
-        */
+        INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
+        INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
+        INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
+        INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
+        INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
+        INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
+        INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
+        INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
+        INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
+        INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
+        INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
+        INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
+        INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
+        INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
+        INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
+        INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
+        INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
+        INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
 };
 #ifdef CONFIG_PM
@@ -313,38 +332,18 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 void __init pxa27x_init_irq(void)
 {
        pxa_init_irq(34, pxa27x_set_wake);
-        pxa_init_gpio(128, pxa27x_set_wake);
+        pxa_init_gpio(121, pxa27x_set_wake);
 }
 /*
 * device registration specific to PXA27x.
 */
-static struct resource i2c_power_resources[] = {
-        {
-                .start  = 0x40f00180,
-                .end    = 0x40f001a3,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_PWRI2C,
-                .end    = IRQ_PWRI2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device pxa27x_device_i2c_power = {
-        .name           = "pxa2xx-i2c",
-        .id             = 1,
-        .resource       = i2c_power_resources,
-        .num_resources  = ARRAY_SIZE(i2c_power_resources),
-};
 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 {
        local_irq_disable();
        PCFR |= PCFR_PI2CEN;
        local_irq_enable();
-        pxa27x_device_i2c_power.dev.platform_data = info;
+        pxa_register_device(&pxa27x_device_i2c_power, info);
 }
 static struct platform_device *devices[] __initdata = {
@@ -353,8 +352,8 @@ static struct platform_device *devices[] __initdata = {
        &pxa_device_btuart,
        &pxa_device_stuart,
        &pxa_device_i2s,
+        &sa1100_device_rtc,
        &pxa_device_rtc,
-        &pxa27x_device_i2c_power,
        &pxa27x_device_ssp1,
        &pxa27x_device_ssp2,
        &pxa27x_device_ssp3,
@@ -380,7 +379,7 @@ static int __init pxa27x_init(void)
                reset_status = RCSR;
-                clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
+                clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
                if ((ret = pxa_init_dma(32)))
                        return ret;
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 9adc7fc4618a..f735e58e6669 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -85,14 +85,16 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
        MFP_ADDR_END,
 };
-static struct clk common_clks[] = {
+static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
-        PXA3xx_CKEN("NANDCLK", NAND, 156000000, 0, &pxa3xx_device_nand.dev),
+static struct clk_lookup common_clkregs[] = {
+        INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", "NANDCLK"),
 };
-static struct clk pxa310_clks[] = {
+static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
-#ifdef CONFIG_CPU_PXA310
-        PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
+static struct clk_lookup pxa310_clkregs[] = {
-#endif
+        INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", "MMCCLK"),
 };
 static int __init pxa300_init(void)
@@ -100,12 +102,12 @@ static int __init pxa300_init(void)
        if (cpu_is_pxa300() || cpu_is_pxa310()) {
                pxa3xx_init_mfp();
                pxa3xx_mfp_init_addr(pxa300_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(common_clks));
+                clks_register(ARRAY_AND_SIZE(common_clkregs));
        }
        if (cpu_is_pxa310()) {
                pxa3xx_mfp_init_addr(pxa310_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(pxa310_clks));
+                clks_register(ARRAY_AND_SIZE(pxa310_clkregs));
        }
        return 0;
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 016eb18f01a3..effe408c186f 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -80,8 +80,10 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
        MFP_ADDR_END,
 };
-static struct clk pxa320_clks[] = {
+static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
-        PXA3xx_CKEN("NANDCLK", NAND, 104000000, 0, &pxa3xx_device_nand.dev),
+static struct clk_lookup pxa320_clkregs[] = {
+        INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", "NANDCLK"),
 };
 static int __init pxa320_init(void)
@@ -89,7 +91,7 @@ static int __init pxa320_init(void)
        if (cpu_is_pxa320()) {
                pxa3xx_init_mfp();
                pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(pxa320_clks));
+                clks_register(ARRAY_AND_SIZE(pxa320_clkregs));
        }
        return 0;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index b3cd5d0b0f35..490893824e78 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -29,6 +29,7 @@
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/ssp.h>
+#include <mach/i2c.h>
 #include "generic.h"
 #include "devices.h"
@@ -216,43 +217,58 @@ static const struct clkops clk_dummy_ops = {
        .disable        = clk_dummy_disable,
 };
-static struct clk pxa3xx_clks[] = {
+static struct clk clk_pxa3xx_pout = {
-        {
+        .ops            = &clk_pout_ops,
-                .name           = "CLK_POUT",
+        .rate           = 13000000,
-                .ops            = &clk_pout_ops,
+        .delay          = 70,
-                .rate           = 13000000,
+};
-                .delay          = 70,
-        },
-        /* Power I2C clock is always on */
-        {
-                .name           = "I2CCLK",
-                .ops            = &clk_dummy_ops,
-                .dev            = &pxa3xx_device_i2c_power.dev,
-        },
-        PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
-        PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
-        PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
-        PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
-        PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
-        PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
-        PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
-        PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa27x_device_udc.dev),
-        PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
-        PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
-        PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
+static struct clk clk_dummy = {
-        PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
+        .ops            = &clk_dummy_ops,
-        PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
+};
-        PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
-        PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
-        PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
-        PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
+static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
-        PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
+static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
+static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
+static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
+static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
+static struct clk_lookup pxa3xx_clkregs[] = {
+        INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
+        /* Power I2C clock is always on */
+        INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
+        INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
+        INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
+        INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
+        INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
+        INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
+        INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
+        INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
+        INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
+        INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
+        INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
 };
 #ifdef CONFIG_PM
@@ -529,28 +545,9 @@ void __init pxa3xx_init_irq(void)
 * device registration specific to PXA3xx.
 */
-static struct resource i2c_power_resources[] = {
-        {
-                .start  = 0x40f500c0,
-                .end    = 0x40f500d3,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_PWRI2C,
-                .end    = IRQ_PWRI2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device pxa3xx_device_i2c_power = {
-        .name           = "pxa2xx-i2c",
-        .id             = 1,
-        .resource       = i2c_power_resources,
-        .num_resources  = ARRAY_SIZE(i2c_power_resources),
-};
 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 {
-        pxa3xx_device_i2c_power.dev.platform_data = info;
+        pxa_register_device(&pxa3xx_device_i2c_power, info);
 }
 static struct platform_device *devices[] __initdata = {
@@ -559,6 +556,7 @@ static struct platform_device *devices[] __initdata = {
        &pxa_device_btuart,
        &pxa_device_stuart,
        &pxa_device_i2s,
+        &sa1100_device_rtc,
        &pxa_device_rtc,
        &pxa27x_device_ssp1,
        &pxa27x_device_ssp2,
@@ -566,7 +564,6 @@ static struct platform_device *devices[] __initdata = {
        &pxa3xx_device_ssp4,
        &pxa27x_device_pwm0,
        &pxa27x_device_pwm1,
-        &pxa3xx_device_i2c_power,
 };
 static struct sys_device pxa3xx_sysdev[] = {
@@ -595,7 +592,7 @@ static int __init pxa3xx_init(void)
                 */
                ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
-                clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
+                clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
                if ((ret = pxa_init_dma(32)))
                        return ret;
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index e7ea91ce7f02..5d02a7325586 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -17,19 +17,44 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/i2c.h>
 #include <linux/smc91x.h>
+#include <linux/mfd/da903x.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/hardware.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa930.h>
+#include <mach/i2c.h>
+#include <mach/regs-lcd.h>
+#include <mach/pxafb.h>
 #include "devices.h"
 #include "generic.h"
+#define GPIO_LCD_RESET  (16)
 /* SAAR MFP configurations */
 static mfp_cfg_t saar_mfp_cfg[] __initdata = {
+        /* LCD */
+        GPIO23_LCD_DD0,
+        GPIO24_LCD_DD1,
+        GPIO25_LCD_DD2,
+        GPIO26_LCD_DD3,
+        GPIO27_LCD_DD4,
+        GPIO28_LCD_DD5,
+        GPIO29_LCD_DD6,
+        GPIO44_LCD_DD7,
+        GPIO21_LCD_CS,
+        GPIO22_LCD_VSYNC,
+        GPIO17_LCD_FCLK_RD,
+        GPIO18_LCD_LCLK_A0,
+        GPIO19_LCD_PCLK_WR,
+        GPIO16_GPIO, /* LCD reset */
        /* Ethernet */
        DF_nCS1_nCS3,
        GPIO97_GPIO,
@@ -64,12 +89,408 @@ static struct platform_device smc91x_device = {
        },
 };
+#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULE)
+static uint16_t lcd_power_on[] = {
+        /* single frame */
+        SMART_CMD_NOOP,
+        SMART_CMD(0x00),
+        SMART_DELAY(0),
+        SMART_CMD_NOOP,
+        SMART_CMD(0x00),
+        SMART_DELAY(0),
+        SMART_CMD_NOOP,
+        SMART_CMD(0x00),
+        SMART_DELAY(0),
+        SMART_CMD_NOOP,
+        SMART_CMD(0x00),
+        SMART_DELAY(10),
+        /* calibration control */
+        SMART_CMD(0x00),
+        SMART_CMD(0xA4),
+        SMART_DAT(0x80),
+        SMART_DAT(0x01),
+        SMART_DELAY(150),
+        /*Power-On Init sequence*/
+        SMART_CMD(0x00),        /* output ctrl */
+        SMART_CMD(0x01),
+        SMART_DAT(0x01),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),        /* wave ctrl */
+        SMART_CMD(0x02),
+        SMART_DAT(0x07),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x03),        /* entry mode */
+        SMART_DAT(0xD0),
+        SMART_DAT(0x30),
+        SMART_CMD(0x00),
+        SMART_CMD(0x08),        /* display ctrl 2 */
+        SMART_DAT(0x08),
+        SMART_DAT(0x08),
+        SMART_CMD(0x00),
+        SMART_CMD(0x09),        /* display ctrl 3 */
+        SMART_DAT(0x04),
+        SMART_DAT(0x2F),
+        SMART_CMD(0x00),
+        SMART_CMD(0x0A),        /* display ctrl 4 */
+        SMART_DAT(0x00),
+        SMART_DAT(0x08),
+        SMART_CMD(0x00),
+        SMART_CMD(0x0D),        /* Frame Marker position */
+        SMART_DAT(0x00),
+        SMART_DAT(0x08),
+        SMART_CMD(0x00),
+        SMART_CMD(0x60),        /* Driver output control */
+        SMART_DAT(0x27),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x61),        /* Base image display control */
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_CMD(0x00),
+        SMART_CMD(0x30),        /* Y settings 30h-3Dh */
+        SMART_DAT(0x07),
+        SMART_DAT(0x07),
+        SMART_CMD(0x00),
+        SMART_CMD(0x31),
+        SMART_DAT(0x00),
+        SMART_DAT(0x07),
+        SMART_CMD(0x00),
+        SMART_CMD(0x32),        /* Timing(3), ASW HOLD=0.5CLK */
+        SMART_DAT(0x04),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x33),        /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
+        SMART_DAT(0x03),
+        SMART_DAT(0x03),
+        SMART_CMD(0x00),
+        SMART_CMD(0x34),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x35),
+        SMART_DAT(0x02),
+        SMART_DAT(0x05),
+        SMART_CMD(0x00),
+        SMART_CMD(0x36),
+        SMART_DAT(0x1F),
+        SMART_DAT(0x1F),
+        SMART_CMD(0x00),
+        SMART_CMD(0x37),
+        SMART_DAT(0x07),
+        SMART_DAT(0x07),
+        SMART_CMD(0x00),
+        SMART_CMD(0x38),
+        SMART_DAT(0x00),
+        SMART_DAT(0x07),
+        SMART_CMD(0x00),
+        SMART_CMD(0x39),
+        SMART_DAT(0x04),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x3A),
+        SMART_DAT(0x03),
+        SMART_DAT(0x03),
+        SMART_CMD(0x00),
+        SMART_CMD(0x3B),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x3C),
+        SMART_DAT(0x02),
+        SMART_DAT(0x05),
+        SMART_CMD(0x00),
+        SMART_CMD(0x3D),
+        SMART_DAT(0x1F),
+        SMART_DAT(0x1F),
+        SMART_CMD(0x00),        /* Display control 1 */
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_CMD(0x00),        /* Power control 5 */
+        SMART_CMD(0x17),
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_CMD(0x00),        /* Power control 1 */
+        SMART_CMD(0x10),
+        SMART_DAT(0x10),
+        SMART_DAT(0xB0),
+        SMART_CMD(0x00),        /* Power control 2 */
+        SMART_CMD(0x11),
+        SMART_DAT(0x01),
+        SMART_DAT(0x30),
+        SMART_CMD(0x00),        /* Power control 3 */
+        SMART_CMD(0x12),
+        SMART_DAT(0x01),
+        SMART_DAT(0x9E),
+        SMART_CMD(0x00),        /* Power control 4 */
+        SMART_CMD(0x13),
+        SMART_DAT(0x17),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),        /* Power control 3 */
+        SMART_CMD(0x12),
+        SMART_DAT(0x01),
+        SMART_DAT(0xBE),
+        SMART_DELAY(100),
+        /* display mode : 240*320 */
+        SMART_CMD(0x00),        /* RAM address set(H) 0*/
+        SMART_CMD(0x20),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),        /* RAM address set(V)   4*/
+        SMART_CMD(0x21),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),        /* Start of Window RAM address set(H) 8*/
+        SMART_CMD(0x50),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),        /* End of Window RAM address set(H) 12*/
+        SMART_CMD(0x51),
+        SMART_DAT(0x00),
+        SMART_DAT(0xEF),
+        SMART_CMD(0x00),        /* Start of Window RAM address set(V) 16*/
+        SMART_CMD(0x52),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),        /* End of Window RAM address set(V) 20*/
+        SMART_CMD(0x53),
+        SMART_DAT(0x01),
+        SMART_DAT(0x3F),
+        SMART_CMD(0x00),        /* Panel interface control 1 */
+        SMART_CMD(0x90),
+        SMART_DAT(0x00),
+        SMART_DAT(0x1A),
+        SMART_CMD(0x00),        /* Panel interface control 2 */
+        SMART_CMD(0x92),
+        SMART_DAT(0x04),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),        /* Panel interface control 3 */
+        SMART_CMD(0x93),
+        SMART_DAT(0x00),
+        SMART_DAT(0x05),
+        SMART_DELAY(20),
+};
+static uint16_t lcd_panel_on[] = {
+        SMART_CMD(0x00),
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0x21),
+        SMART_DELAY(1),
+        SMART_CMD(0x00),
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0x61),
+        SMART_DELAY(100),
+        SMART_CMD(0x00),
+        SMART_CMD(0x07),
+        SMART_DAT(0x01),
+        SMART_DAT(0x73),
+        SMART_DELAY(1),
+};
+static uint16_t lcd_panel_off[] = {
+        SMART_CMD(0x00),
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0x72),
+        SMART_DELAY(40),
+        SMART_CMD(0x00),
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_DELAY(1),
+        SMART_CMD(0x00),
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_DELAY(1),
+};
+static uint16_t lcd_power_off[] = {
+        SMART_CMD(0x00),
+        SMART_CMD(0x10),
+        SMART_DAT(0x00),
+        SMART_DAT(0x80),
+        SMART_CMD(0x00),
+        SMART_CMD(0x11),
+        SMART_DAT(0x01),
+        SMART_DAT(0x60),
+        SMART_CMD(0x00),
+        SMART_CMD(0x12),
+        SMART_DAT(0x01),
+        SMART_DAT(0xAE),
+        SMART_DELAY(40),
+        SMART_CMD(0x00),
+        SMART_CMD(0x10),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+};
+static uint16_t update_framedata[] = {
+        /* set display ram: 240*320 */
+        SMART_CMD(0x00), /* RAM address set(H) 0*/
+        SMART_CMD(0x20),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00), /* RAM address set(V) 4*/
+        SMART_CMD(0x21),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */
+        SMART_CMD(0x50),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */
+        SMART_CMD(0x51),
+        SMART_DAT(0x00),
+        SMART_DAT(0xEF),
+        SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */
+        SMART_CMD(0x52),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */
+        SMART_CMD(0x53),
+        SMART_DAT(0x01),
+        SMART_DAT(0x3F),
+        /* wait for vsync cmd before transferring frame data */
+        SMART_CMD_WAIT_FOR_VSYNC,
+        /* write ram */
+        SMART_CMD(0x00),
+        SMART_CMD(0x22),
+        /* write frame data */
+        SMART_CMD_WRITE_FRAME,
+};
+static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var)
+{
+        static int pin_requested = 0;
+        struct fb_info *info = container_of(var, struct fb_info, var);
+        int err;
+        if (!pin_requested) {
+                err = gpio_request(GPIO_LCD_RESET, "lcd reset");
+                if (err) {
+                        pr_err("failed to request gpio for LCD reset\n");
+                        return;
+                }
+                gpio_direction_output(GPIO_LCD_RESET, 0);
+                pin_requested = 1;
+        }
+        if (on) {
+                gpio_set_value(GPIO_LCD_RESET, 0); msleep(100);
+                gpio_set_value(GPIO_LCD_RESET, 1); msleep(10);
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on));
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on));
+        } else {
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off));
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off));
+        }
+        err = pxafb_smart_flush(info);
+        if (err)
+                pr_err("%s: timed out\n", __func__);
+}
+static void ltm022a97a_update(struct fb_info *info)
+{
+        pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
+        pxafb_smart_flush(info);
+}
+static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = {
+        [0] = {
+                .xres                   = 240,
+                .yres                   = 320,
+                .bpp                    = 16,
+                .a0csrd_set_hld         = 30,
+                .a0cswr_set_hld         = 30,
+                .wr_pulse_width         = 30,
+                .rd_pulse_width         = 30,
+                .op_hold_time           = 30,
+                .cmd_inh_time           = 60,
+                /* L_LCLK_A0 and L_LCLK_RD active low */
+                .sync                   = FB_SYNC_HOR_HIGH_ACT |
+                                          FB_SYNC_VERT_HIGH_ACT,
+        },
+};
+static struct pxafb_mach_info saar_lcd_info = {
+        .modes                  = toshiba_ltm022a97a_modes,
+        .num_modes              = 1,
+        .lcd_conn               = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
+        .pxafb_lcd_power        = ltm022a97a_lcd_power,
+        .smart_update           = ltm022a97a_update,
+};
+static void __init saar_init_lcd(void)
+{
+        set_pxa_fb_info(&saar_lcd_info);
+}
+#else
+static inline void saar_init_lcd(void) {}
+#endif
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct da903x_subdev_info saar_da9034_subdevs[] = {
+        [0] = {
+                .name           = "da903x-backlight",
+                .id             = DA9034_ID_WLED,
+        },
+};
+static struct da903x_platform_data saar_da9034_info = {
+        .num_subdevs    = ARRAY_SIZE(saar_da9034_subdevs),
+        .subdevs        = saar_da9034_subdevs,
+};
+static struct i2c_board_info saar_i2c_info[] = {
+        [0] = {
+                .type           = "da9034",
+                .addr           = 0x34,
+                .platform_data  = &saar_da9034_info,
+                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+        },
+};
+static void __init saar_init_i2c(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info));
+}
+#else
+static inline void saar_init_i2c(void) {}
+#endif
 static void __init saar_init(void)
 {
        /* initialize MFP configurations */
        pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
        platform_device_register(&smc91x_device);
+        saar_init_i2c();
+        saar_init_lcd();
 }
 MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index ad346addc028..d6f6904132a6 100644
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -8,6 +8,8 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
+#include <mach/hardware.h>
 #define SMEMC_PHYS_BASE (0x4A000000)
 #define SMEMC_PHYS_SIZE (0x90)
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 3be76ee2bdbf..7299d87a1cb3 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -22,6 +22,7 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <linux/mmc/host.h>
+#include <linux/mtd/physmap.h>
 #include <linux/pm.h>
 #include <linux/backlight.h>
 #include <linux/io.h>
@@ -122,6 +123,10 @@ static unsigned long spitz_pin_config[] __initdata = {
        GPIO105_GPIO,   /* SPITZ_GPIO_CF_IRQ */
        GPIO106_GPIO,   /* SPITZ_GPIO_CF2_IRQ */
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
 };
@@ -609,10 +614,41 @@ static struct pxafb_mach_info spitz_pxafb_info = {
 };
+static struct mtd_partition sharpsl_rom_parts[] = {
+        {
+                .name   ="Boot PROM Filesystem",
+                .offset = 0x00140000,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data sharpsl_rom_data = {
+        .width          = 2,
+        .nr_parts       = ARRAY_SIZE(sharpsl_rom_parts),
+        .parts          = sharpsl_rom_parts,
+};
+static struct resource sharpsl_rom_resources[] = {
+        {
+                .start  = 0x00000000,
+                .end    = 0x007fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device sharpsl_rom_device = {
+        .name   = "physmap-flash",
+        .id     = -1,
+        .resource = sharpsl_rom_resources,
+        .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
+        .dev.platform_data = &sharpsl_rom_data,
+};
 static struct platform_device *devices[] __initdata = {
        &spitzscoop_device,
        &spitzkbd_device,
        &spitzled_device,
+        &sharpsl_rom_device,
 };
 static void spitz_poweroff(void)
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index 2c31ec725688..6f42004db3ed 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -356,7 +356,7 @@ static int __devinit ssp_probe(struct platform_device *pdev, int type)
        }
        ssp->pdev = pdev;
-        ssp->clk = clk_get(&pdev->dev, "SSPCLK");
+        ssp->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(ssp->clk)) {
                ret = PTR_ERR(ssp->clk);
                goto err_free;
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 589d32b4fc46..58ef08a5224b 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -18,12 +18,15 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/smc91x.h>
+#include <linux/pwm_backlight.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/hardware.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa930.h>
+#include <mach/pxafb.h>
+#include <mach/pxa27x_keypad.h>
 #include "devices.h"
 #include "generic.h"
@@ -33,6 +36,45 @@ static mfp_cfg_t tavorevb_mfp_cfg[] __initdata = {
        /* Ethernet */
        DF_nCS1_nCS3,
        GPIO47_GPIO,
+        /* LCD */
+        GPIO23_LCD_DD0,
+        GPIO24_LCD_DD1,
+        GPIO25_LCD_DD2,
+        GPIO26_LCD_DD3,
+        GPIO27_LCD_DD4,
+        GPIO28_LCD_DD5,
+        GPIO29_LCD_DD6,
+        GPIO44_LCD_DD7,
+        GPIO21_LCD_CS,
+        GPIO22_LCD_CS2,
+        GPIO17_LCD_FCLK_RD,
+        GPIO18_LCD_LCLK_A0,
+        GPIO19_LCD_PCLK_WR,
+        /* LCD Backlight */
+        GPIO43_PWM3,    /* primary backlight */
+        GPIO32_PWM0,    /* secondary backlight */
+        /* Keypad */
+        GPIO0_KP_MKIN_0,
+        GPIO2_KP_MKIN_1,
+        GPIO4_KP_MKIN_2,
+        GPIO6_KP_MKIN_3,
+        GPIO8_KP_MKIN_4,
+        GPIO10_KP_MKIN_5,
+        GPIO12_KP_MKIN_6,
+        GPIO1_KP_MKOUT_0,
+        GPIO3_KP_MKOUT_1,
+        GPIO5_KP_MKOUT_2,
+        GPIO7_KP_MKOUT_3,
+        GPIO9_KP_MKOUT_4,
+        GPIO11_KP_MKOUT_5,
+        GPIO13_KP_MKOUT_6,
+        GPIO14_KP_DKIN_2,
+        GPIO15_KP_DKIN_3,
 };
 #define TAVOREVB_ETH_PHYS       (0x14000000)
@@ -64,12 +106,382 @@ static struct platform_device smc91x_device = {
        },
 };
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
+static unsigned int tavorevb_matrix_key_map[] = {
+        /* KEY(row, col, key_code) */
+        KEY(0, 4, KEY_A), KEY(0, 5, KEY_B), KEY(0, 6, KEY_C),
+        KEY(1, 4, KEY_E), KEY(1, 5, KEY_F), KEY(1, 6, KEY_G),
+        KEY(2, 4, KEY_I), KEY(2, 5, KEY_J), KEY(2, 6, KEY_K),
+        KEY(3, 4, KEY_M), KEY(3, 5, KEY_N), KEY(3, 6, KEY_O),
+        KEY(4, 5, KEY_R), KEY(4, 6, KEY_S),
+        KEY(5, 4, KEY_U), KEY(5, 4, KEY_V), KEY(5, 6, KEY_W),
+        KEY(6, 4, KEY_Y), KEY(6, 5, KEY_Z),
+        KEY(0, 3, KEY_0), KEY(2, 0, KEY_1), KEY(2, 1, KEY_2), KEY(2, 2, KEY_3),
+        KEY(2, 3, KEY_4), KEY(1, 0, KEY_5), KEY(1, 1, KEY_6), KEY(1, 2, KEY_7),
+        KEY(1, 3, KEY_8), KEY(0, 2, KEY_9),
+        KEY(6, 6, KEY_SPACE),
+        KEY(0, 0, KEY_KPASTERISK),      /* * */
+        KEY(0, 1, KEY_KPDOT),           /* # */
+        KEY(4, 1, KEY_UP),
+        KEY(4, 3, KEY_DOWN),
+        KEY(4, 0, KEY_LEFT),
+        KEY(4, 2, KEY_RIGHT),
+        KEY(6, 0, KEY_HOME),
+        KEY(3, 2, KEY_END),
+        KEY(6, 1, KEY_DELETE),
+        KEY(5, 2, KEY_BACK),
+        KEY(6, 3, KEY_CAPSLOCK),        /* KEY_LEFTSHIFT), */
+        KEY(4, 4, KEY_ENTER),           /* scroll push */
+        KEY(6, 2, KEY_ENTER),           /* keypad action */
+        KEY(3, 1, KEY_SEND),
+        KEY(5, 3, KEY_RECORD),
+        KEY(5, 0, KEY_VOLUMEUP),
+        KEY(5, 1, KEY_VOLUMEDOWN),
+        KEY(3, 0, KEY_F22),     /* soft1 */
+        KEY(3, 3, KEY_F23),     /* soft2 */
+};
+static struct pxa27x_keypad_platform_data tavorevb_keypad_info = {
+        .matrix_key_rows        = 7,
+        .matrix_key_cols        = 7,
+        .matrix_key_map         = tavorevb_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(tavorevb_matrix_key_map),
+        .debounce_interval      = 30,
+};
+static void __init tavorevb_init_keypad(void)
+{
+        pxa_set_keypad_info(&tavorevb_keypad_info);
+}
+#else
+static inline void tavorevb_init_keypad(void) {}
+#endif /* CONFIG_KEYBOARD_PXA27x || CONFIG_KEYBOARD_PXA27x_MODULE */
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct platform_pwm_backlight_data tavorevb_backlight_data[] = {
+        [0] = {
+                /* primary backlight */
+                .pwm_id         = 2,
+                .max_brightness = 100,
+                .dft_brightness = 100,
+                .pwm_period_ns  = 100000,
+        },
+        [1] = {
+                /* secondary backlight */
+                .pwm_id         = 0,
+                .max_brightness = 100,
+                .dft_brightness = 100,
+                .pwm_period_ns  = 100000,
+        },
+};
+static struct platform_device tavorevb_backlight_devices[] = {
+        [0] = {
+                .name           = "pwm-backlight",
+                .id             = 0,
+                .dev            = {
+                        .platform_data = &tavorevb_backlight_data[0],
+                },
+        },
+        [1] = {
+                .name           = "pwm-backlight",
+                .id             = 1,
+                .dev            = {
+                        .platform_data = &tavorevb_backlight_data[1],
+                },
+        },
+};
+static uint16_t panel_init[] = {
+        /* DSTB OUT */
+        SMART_CMD(0x00),
+        SMART_CMD_NOOP,
+        SMART_DELAY(1),
+        SMART_CMD(0x00),
+        SMART_CMD_NOOP,
+        SMART_DELAY(1),
+        SMART_CMD(0x00),
+        SMART_CMD_NOOP,
+        SMART_DELAY(1),
+        /* STB OUT */
+        SMART_CMD(0x00),
+        SMART_CMD(0x1D),
+        SMART_DAT(0x00),
+        SMART_DAT(0x05),
+        SMART_DELAY(1),
+        /* P-ON Init sequence */
+        SMART_CMD(0x00), /* OSC ON */
+        SMART_CMD(0x00),
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_CMD(0x00),
+        SMART_CMD(0x01), /* SOURCE DRIVER SHIFT DIRECTION and display RAM setting */
+        SMART_DAT(0x01),
+        SMART_DAT(0x27),
+        SMART_CMD(0x00),
+        SMART_CMD(0x02), /* LINE INV */
+        SMART_DAT(0x02),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x03), /* IF mode(1) */
+        SMART_DAT(0x01), /* 8bit smart mode(8-8),high speed write mode */
+        SMART_DAT(0x30),
+        SMART_CMD(0x07),
+        SMART_CMD(0x00), /* RAM Write Mode */
+        SMART_DAT(0x00),
+        SMART_DAT(0x03),
+        SMART_CMD(0x00),
+        /* DISPLAY Setting,  262K, fixed(NO scroll), no split screen */
+        SMART_CMD(0x07),
+        SMART_DAT(0x40), /* 16/18/19 BPP */
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x08), /* BP, FP Seting, BP=2H, FP=3H */
+        SMART_DAT(0x03),
+        SMART_DAT(0x02),
+        SMART_CMD(0x00),
+        SMART_CMD(0x0C), /* IF mode(2), using internal clock & MPU */
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x0D), /* Frame setting, 1Min. Frequence, 16CLK */
+        SMART_DAT(0x00),
+        SMART_DAT(0x10),
+        SMART_CMD(0x00),
+        SMART_CMD(0x12), /* Timing(1),ASW W=4CLK, ASW ST=1CLK */
+        SMART_DAT(0x03),
+        SMART_DAT(0x02),
+        SMART_CMD(0x00),
+        SMART_CMD(0x13), /* Timing(2),OEV ST=0.5CLK, OEV ED=1CLK */
+        SMART_DAT(0x01),
+        SMART_DAT(0x02),
+        SMART_CMD(0x00),
+        SMART_CMD(0x14), /* Timing(3), ASW HOLD=0.5CLK */
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x15), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
+        SMART_DAT(0x20),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x1C),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x03),
+        SMART_CMD(0x00),
+        SMART_DAT(0x04),
+        SMART_DAT(0x03),
+        SMART_CMD(0x03),
+        SMART_CMD(0x01),
+        SMART_DAT(0x03),
+        SMART_DAT(0x04),
+        SMART_CMD(0x03),
+        SMART_CMD(0x02),
+        SMART_DAT(0x04),
+        SMART_DAT(0x03),
+        SMART_CMD(0x03),
+        SMART_CMD(0x03),
+        SMART_DAT(0x03),
+        SMART_DAT(0x03),
+        SMART_CMD(0x03),
+        SMART_CMD(0x04),
+        SMART_DAT(0x01),
+        SMART_DAT(0x01),
+        SMART_CMD(0x03),
+        SMART_CMD(0x05),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x04),
+        SMART_CMD(0x02),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x04),
+        SMART_CMD(0x03),
+        SMART_DAT(0x01),
+        SMART_DAT(0x3F),
+        SMART_DELAY(0),
+        /* DISP RAM setting: 240*320 */
+        SMART_CMD(0x04), /* HADDR, START 0 */
+        SMART_CMD(0x06),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00), /* x1,3 */
+        SMART_CMD(0x04), /* HADDR,  END   4 */
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0xEF), /* x2, 7 */
+        SMART_CMD(0x04), /* VADDR, START 8 */
+        SMART_CMD(0x08),
+        SMART_DAT(0x00), /* y1, 10 */
+        SMART_DAT(0x00), /* y1, 11 */
+        SMART_CMD(0x04), /* VADDR, END 12 */
+        SMART_CMD(0x09),
+        SMART_DAT(0x01), /* y2, 14 */
+        SMART_DAT(0x3F), /* y2, 15 */
+        SMART_CMD(0x02), /* RAM ADDR SETTING 16 */
+        SMART_CMD(0x00),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00), /* x1, 19 */
+        SMART_CMD(0x02), /* RAM ADDR SETTING 20 */
+        SMART_CMD(0x01),
+        SMART_DAT(0x00), /* y1, 22 */
+        SMART_DAT(0x00), /* y1, 23 */
+};
+static uint16_t panel_on[] = {
+        /* Power-IC ON */
+        SMART_CMD(0x01),
+        SMART_CMD(0x02),
+        SMART_DAT(0x07),
+        SMART_DAT(0x7D),
+        SMART_CMD(0x01),
+        SMART_CMD(0x03),
+        SMART_DAT(0x00),
+        SMART_DAT(0x05),
+        SMART_CMD(0x01),
+        SMART_CMD(0x04),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x01),
+        SMART_CMD(0x05),
+        SMART_DAT(0x00),
+        SMART_DAT(0x15),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xC0),
+        SMART_DAT(0x10),
+        SMART_DELAY(30),
+        /* DISP ON */
+        SMART_CMD(0x01),
+        SMART_CMD(0x01),
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xFF),
+        SMART_DAT(0xFE),
+        SMART_DELAY(150),
+};
+static uint16_t panel_off[] = {
+        SMART_CMD(0x00),
+        SMART_CMD(0x1E),
+        SMART_DAT(0x00),
+        SMART_DAT(0x0A),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xFF),
+        SMART_DAT(0xEE),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xF8),
+        SMART_DAT(0x12),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xE8),
+        SMART_DAT(0x11),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xC0),
+        SMART_DAT(0x11),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0x40),
+        SMART_DAT(0x11),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0x00),
+        SMART_DAT(0x10),
+};
+static uint16_t update_framedata[] = {
+        /* write ram */
+        SMART_CMD(0x02),
+        SMART_CMD(0x02),
+        /* write frame data */
+        SMART_CMD_WRITE_FRAME,
+};
+static void ltm020d550_lcd_power(int on, struct fb_var_screeninfo *var)
+{
+        struct fb_info *info = container_of(var, struct fb_info, var);
+        if (on) {
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_init));
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_on));
+        } else {
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_off));
+        }
+        if (pxafb_smart_flush(info))
+                pr_err("%s: timed out\n", __func__);
+}
+static void ltm020d550_update(struct fb_info *info)
+{
+        pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
+        pxafb_smart_flush(info);
+}
+static struct pxafb_mode_info toshiba_ltm020d550_modes[] = {
+        [0] = {
+                .xres                   = 240,
+                .yres                   = 320,
+                .bpp                    = 16,
+                .a0csrd_set_hld         = 30,
+                .a0cswr_set_hld         = 30,
+                .wr_pulse_width         = 30,
+                .rd_pulse_width         = 170,
+                .op_hold_time           = 30,
+                .cmd_inh_time           = 60,
+                /* L_LCLK_A0 and L_LCLK_RD active low */
+                .sync                   = FB_SYNC_HOR_HIGH_ACT |
+                                          FB_SYNC_VERT_HIGH_ACT,
+        },
+};
+static struct pxafb_mach_info tavorevb_lcd_info = {
+        .modes                  = toshiba_ltm020d550_modes,
+        .num_modes              = 1,
+        .lcd_conn               = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
+        .pxafb_lcd_power        = ltm020d550_lcd_power,
+        .smart_update           = ltm020d550_update,
+};
+static void __init tavorevb_init_lcd(void)
+{
+        platform_device_register(&tavorevb_backlight_devices[0]);
+        platform_device_register(&tavorevb_backlight_devices[1]);
+        set_pxa_fb_info(&tavorevb_lcd_info);
+}
+#else
+static inline void tavorevb_init_lcd(void) {}
+#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
 static void __init tavorevb_init(void)
 {
        /* initialize MFP configurations */
        pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg));
        platform_device_register(&smc91x_device);
+        tavorevb_init_lcd();
+        tavorevb_init_keypad();
 }
 MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index bf3c9a4aad50..95656a72268d 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -22,8 +22,8 @@
 #include <asm/div64.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
+#include <mach/hardware.h>
 #include <mach/pxa-regs.h>
-#include <asm/mach-types.h>
 /*
 * This is PXA's sched_clock implementation. This has a resolution
@@ -149,18 +149,11 @@ static struct irqaction pxa_ost0_irq = {
 static void __init pxa_timer_init(void)
 {
-        unsigned long clock_tick_rate;
+        unsigned long clock_tick_rate = get_clock_tick_rate();
        OIER = 0;
        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
-        if (cpu_is_pxa25x())
-                clock_tick_rate = 3686400;
-        else if (machine_is_mainstone())
-                clock_tick_rate = 3249600;
-        else
-                clock_tick_rate = 3250000;
        set_oscr2ns_scale(clock_tick_rate);
        ckevt_pxa_osmr0.mult =
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 224897a67d15..3332e5d0356c 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -25,6 +25,7 @@
 #include <linux/mfd/tmio.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
 #include <linux/pm.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
@@ -733,6 +734,45 @@ static void tosa_tc6393xb_teardown(struct platform_device *dev)
        gpio_free(TOSA_GPIO_CARD_VCC_ON);
 }
+#ifdef CONFIG_MFD_TC6393XB
+static struct fb_videomode tosa_tc6393xb_lcd_mode[] = {
+        {
+                .xres = 480,
+                .yres = 640,
+                .pixclock = 0x002cdf00,/* PLL divisor */
+                .left_margin = 0x004c,
+                .right_margin = 0x005b,
+                .upper_margin = 0x0001,
+                .lower_margin = 0x000d,
+                .hsync_len = 0x0002,
+                .vsync_len = 0x0001,
+                .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+                .vmode = FB_VMODE_NONINTERLACED,
+        },{
+                .xres = 240,
+                .yres = 320,
+                .pixclock = 0x00e7f203,/* PLL divisor */
+                .left_margin = 0x0024,
+                .right_margin = 0x002f,
+                .upper_margin = 0x0001,
+                .lower_margin = 0x000d,
+                .hsync_len = 0x0002,
+                .vsync_len = 0x0001,
+                .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+                .vmode = FB_VMODE_NONINTERLACED,
+        }
+};
+static struct tmio_fb_data tosa_tc6393xb_fb_config = {
+        .lcd_set_power  = tc6393xb_lcd_set_power,
+        .lcd_mode       = tc6393xb_lcd_mode,
+        .num_modes      = ARRAY_SIZE(tosa_tc6393xb_lcd_mode),
+        .modes          = &tosa_tc6393xb_lcd_mode[0],
+        .height         = 82,
+        .width          = 60,
+};
+#endif
 static struct tc6393xb_platform_data tosa_tc6393xb_data = {
        .scr_pll2cr     = 0x0cc1,
        .scr_gper       = 0x3300,
@@ -748,6 +788,9 @@ static struct tc6393xb_platform_data tosa_tc6393xb_data = {
        .resume         = tosa_tc6393xb_resume,
        .nand_data      = &tosa_tc6393xb_nand_config,
+#ifdef CONFIG_MFD_TC6393XB
+        .fb_data        = &tosa_tc6393xb_fb_config,
+#endif
        .resume_restore = 1,
 };
@@ -789,6 +832,36 @@ static struct spi_board_info spi_board_info[] __initdata = {
        },
 };
+static struct mtd_partition sharpsl_rom_parts[] = {
+        {
+                .name   ="Boot PROM Filesystem",
+                .offset = 0x00160000,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data sharpsl_rom_data = {
+        .width          = 2,
+        .nr_parts       = ARRAY_SIZE(sharpsl_rom_parts),
+        .parts          = sharpsl_rom_parts,
+};
+static struct resource sharpsl_rom_resources[] = {
+        {
+                .start  = 0x00000000,
+                .end    = 0x007fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device sharpsl_rom_device = {
+        .name   = "physmap-flash",
+        .id     = -1,
+        .resource = sharpsl_rom_resources,
+        .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
+        .dev.platform_data = &sharpsl_rom_data,
+};
 static struct platform_device *devices[] __initdata = {
        &tosascoop_device,
        &tosascoop_jc_device,
@@ -798,6 +871,7 @@ static struct platform_device *devices[] __initdata = {
        &tosa_gpio_keys_device,
        &tosaled_device,
        &tosa_bt_device,
+        &sharpsl_rom_device,
 };
 static void tosa_poweroff(void)
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 813804433466..218d2001f1df 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -18,6 +18,7 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
 #include <linux/smc91x.h>
@@ -25,7 +26,6 @@
 #include <asm/mach/arch.h>
 #include <mach/hardware.h>
 #include <mach/audio.h>
-#include <mach/gpio.h>
 #include <mach/pxafb.h>
 #include <mach/zylonite.h>
 #include <mach/mmc.h>
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 0f244744daae..28e4e623780b 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -16,8 +16,8 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
-#include <mach/gpio.h>
 #include <mach/mfp-pxa320.h>
 #include <mach/zylonite.h>