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Diffstat (limited to 'arch/arm/mach-pxa/include/mach/regs-intc.h')
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-intc.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
index ad23e74b762f..68464ce1c1ea 100644
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -13,6 +13,7 @@
13#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ 13#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
14#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ 14#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
15#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ 15#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
16#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
16 17
17#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ 18#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
18#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ 19#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
@@ -20,4 +21,14 @@
20#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ 21#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
21#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ 22#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
22 23
24#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */
25#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */
26#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */
27#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
28#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
29
30#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \
31 : (x < 64 ? (0x94 + ((x - 32) << 2)) \
32 : (0x128 + ((x - 64) << 2)))))
33
23#endif /* __ASM_MACH_REGS_INTC_H */ 34#endif /* __ASM_MACH_REGS_INTC_H */