diff options
Diffstat (limited to 'arch/arm/mach-orion5x/include/mach/orion5x.h')
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/orion5x.h | 68 |
1 files changed, 20 insertions, 48 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 67bda31406dd..377a773ae53f 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h | |||
@@ -61,30 +61,10 @@ | |||
61 | #define ORION5X_PCI_MEM_SIZE SZ_128M | 61 | #define ORION5X_PCI_MEM_SIZE SZ_128M |
62 | 62 | ||
63 | /******************************************************************************* | 63 | /******************************************************************************* |
64 | * Supported Devices & Revisions | ||
65 | ******************************************************************************/ | ||
66 | /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ | ||
67 | #define MV88F5181_DEV_ID 0x5181 | ||
68 | #define MV88F5181_REV_B1 3 | ||
69 | #define MV88F5181L_REV_A0 8 | ||
70 | #define MV88F5181L_REV_A1 9 | ||
71 | /* Orion-NAS (88F5182) */ | ||
72 | #define MV88F5182_DEV_ID 0x5182 | ||
73 | #define MV88F5182_REV_A2 2 | ||
74 | /* Orion-2 (88F5281) */ | ||
75 | #define MV88F5281_DEV_ID 0x5281 | ||
76 | #define MV88F5281_REV_D0 4 | ||
77 | #define MV88F5281_REV_D1 5 | ||
78 | #define MV88F5281_REV_D2 6 | ||
79 | /* Orion-1-90 (88F6183) */ | ||
80 | #define MV88F6183_DEV_ID 0x6183 | ||
81 | #define MV88F6183_REV_B0 3 | ||
82 | |||
83 | /******************************************************************************* | ||
84 | * Orion Registers Map | 64 | * Orion Registers Map |
85 | ******************************************************************************/ | 65 | ******************************************************************************/ |
66 | |||
86 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) | 67 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) |
87 | #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) | ||
88 | 68 | ||
89 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) | 69 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) |
90 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) | 70 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) |
@@ -97,34 +77,25 @@ | |||
97 | #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) | 77 | #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) |
98 | 78 | ||
99 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) | 79 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) |
100 | #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) | ||
101 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) | ||
102 | 80 | ||
103 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) | 81 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) |
104 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) | ||
105 | 82 | ||
106 | #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) | 83 | #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) |
107 | #define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) | ||
108 | 84 | ||
109 | #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) | 85 | #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) |
110 | #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) | 86 | #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) |
111 | #define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) | ||
112 | 87 | ||
113 | #define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) | 88 | #define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) |
114 | #define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) | 89 | #define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) |
115 | #define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x)) | ||
116 | 90 | ||
117 | #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) | 91 | #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) |
118 | #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) | 92 | #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) |
119 | #define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) | ||
120 | 93 | ||
121 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) | 94 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) |
122 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) | 95 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) |
123 | #define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) | ||
124 | 96 | ||
125 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) | 97 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) |
126 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) | 98 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) |
127 | #define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) | ||
128 | 99 | ||
129 | /******************************************************************************* | 100 | /******************************************************************************* |
130 | * Device Bus Registers | 101 | * Device Bus Registers |
@@ -142,23 +113,24 @@ | |||
142 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) | 113 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) |
143 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) | 114 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) |
144 | 115 | ||
145 | /*************************************************************************** | 116 | /******************************************************************************* |
146 | * Orion CPU Bridge Registers | 117 | * Supported Devices & Revisions |
147 | **************************************************************************/ | 118 | ******************************************************************************/ |
148 | #define CPU_CONF ORION5X_BRIDGE_REG(0x100) | 119 | /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ |
149 | #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) | 120 | #define MV88F5181_DEV_ID 0x5181 |
150 | #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) | 121 | #define MV88F5181_REV_B1 3 |
151 | #define WDT_RESET 0x0002 | 122 | #define MV88F5181L_REV_A0 8 |
152 | #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) | 123 | #define MV88F5181L_REV_A1 9 |
153 | #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) | 124 | /* Orion-NAS (88F5182) */ |
154 | #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) | 125 | #define MV88F5182_DEV_ID 0x5182 |
155 | #define WDT_INT_REQ 0x0008 | 126 | #define MV88F5182_REV_A2 2 |
156 | #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) | 127 | /* Orion-2 (88F5281) */ |
157 | #define BRIDGE_INT_TIMER0 0x0002 | 128 | #define MV88F5281_DEV_ID 0x5281 |
158 | #define BRIDGE_INT_TIMER1 0x0004 | 129 | #define MV88F5281_REV_D0 4 |
159 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | 130 | #define MV88F5281_REV_D1 5 |
160 | #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) | 131 | #define MV88F5281_REV_D2 6 |
161 | #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) | 132 | /* Orion-1-90 (88F6183) */ |
162 | 133 | #define MV88F6183_DEV_ID 0x6183 | |
134 | #define MV88F6183_REV_B0 3 | ||
163 | 135 | ||
164 | #endif | 136 | #endif |