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1/*
2 * arch/arm/mach-orion/addr-map.c
3 *
4 * Address map functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <asm/hardware.h>
16#include "common.h"
17
18/*
19 * The Orion has fully programable address map. There's a separate address
20 * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
21 * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
22 * address decode windows that allow it to access any of the Orion resources.
23 *
24 * CPU address decoding --
25 * Linux assumes that it is the boot loader that already setup the access to
26 * DDR and internal registers.
27 * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
28 * Setup access to various devices located on the device bus interface (e.g.
29 * flashes, RTC, etc) should be issued by machine-setup.c according to
30 * specific board population (by using orion_setup_cpu_win()).
31 *
32 * Non-CPU Masters address decoding --
33 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
34 * banks only (the typical use case).
35 * Setup access for each master to DDR is issued by common.c.
36 *
37 * Note: although orion_setbits() and orion_clrbits() are not atomic
38 * no locking is necessary here since code in this file is only called
39 * at boot time when there is no concurrency issues.
40 */
41
42/*
43 * Generic Address Decode Windows bit settings
44 */
45#define TARGET_DDR 0
46#define TARGET_PCI 3
47#define TARGET_PCIE 4
48#define TARGET_DEV_BUS 1
49#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
50 ((n) == 1) ? 0xd : \
51 ((n) == 2) ? 0xb : \
52 ((n) == 3) ? 0x7 : 0xf)
53#define ATTR_PCIE_MEM 0x59
54#define ATTR_PCIE_IO 0x51
55#define ATTR_PCI_MEM 0x59
56#define ATTR_PCI_IO 0x51
57#define ATTR_DEV_CS0 0x1e
58#define ATTR_DEV_CS1 0x1d
59#define ATTR_DEV_CS2 0x1b
60#define ATTR_DEV_BOOT 0xf
61#define WIN_EN 1
62
63/*
64 * Helpers to get DDR banks info
65 */
66#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
67#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))
68#define DDR_MAX_CS 4
69#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
70#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
71#define DDR_BANK_EN 1
72
73/*
74 * CPU Address Decode Windows registers
75 */
76#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4))
77#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4))
78#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4))
79#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4))
80#define CPU_MAX_WIN 8
81
82/*
83 * Use this CPU address decode windows allocation
84 */
85#define CPU_WIN_PCIE_IO 0
86#define CPU_WIN_PCI_IO 1
87#define CPU_WIN_PCIE_MEM 2
88#define CPU_WIN_PCI_MEM 3
89#define CPU_WIN_DEV_BOOT 4
90#define CPU_WIN_DEV_CS0 5
91#define CPU_WIN_DEV_CS1 6
92#define CPU_WIN_DEV_CS2 7
93
94/*
95 * PCIE Address Decode Windows registers
96 */
97#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
98#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
99#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
100#define PCIE_WIN_CTRL(n) ORION_PCIE_REG(0x1820 + ((n) << 4))
101#define PCIE_WIN_BASE(n) ORION_PCIE_REG(0x1824 + ((n) << 4))
102#define PCIE_WIN_REMAP(n) ORION_PCIE_REG(0x182c + ((n) << 4))
103#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0)
104#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0)
105#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4)
106#define PCIE_MAX_BARS 3
107#define PCIE_MAX_WINS 5
108
109/*
110 * Use PCIE BAR '1' for all DDR banks
111 */
112#define PCIE_DRAM_BAR 1
113
114/*
115 * PCI Address Decode Windows registers
116 */
117#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
118 ((n) == 1) ? ORION_PCI_REG(0xd08) : \
119 ((n) == 2) ? ORION_PCI_REG(0xc0c) : \
120 ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
121#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
122 ((n) == 1) ? ORION_PCI_REG(0xd48) : \
123 ((n) == 2) ? ORION_PCI_REG(0xc4c) : \
124 ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
125#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
126#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4))
127#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4))
128#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4))
129#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
130
131/*
132 * PCI configuration heleprs for BAR settings
133 */
134#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
135#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
136#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
137
138/*
139 * Gigabit Ethernet Address Decode Windows registers
140 */
141#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8))
142#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8))
143#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4))
144#define ETH_WIN_EN ORION_ETH_REG(0x290)
145#define ETH_WIN_PROT ORION_ETH_REG(0x294)
146#define ETH_MAX_WIN 6
147#define ETH_MAX_REMAP_WIN 4
148
149/*
150 * USB Address Decode Windows registers
151 */
152#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
153 : ORION_USB1_REG(0x320 + ((w) << 4)))
154#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
155 : ORION_USB1_REG(0x324 + ((w) << 4)))
156#define USB_MAX_WIN 4
157
158/*
159 * SATA Address Decode Windows registers
160 */
161#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10))
162#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
163#define SATA_MAX_WIN 4
164
165static int __init orion_cpu_win_can_remap(u32 win)
166{
167 u32 dev, rev;
168
169 orion_pcie_id(&dev, &rev);
170 if ((dev == MV88F5281_DEV_ID && win < 4)
171 || (dev == MV88F5182_DEV_ID && win < 2)
172 || (dev == MV88F5181_DEV_ID && win < 2))
173 return 1;
174
175 return 0;
176}
177
178void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
179{
180 u32 win, attr, ctrl;
181
182 switch (target) {
183 case ORION_PCIE_IO:
184 target = TARGET_PCIE;
185 attr = ATTR_PCIE_IO;
186 win = CPU_WIN_PCIE_IO;
187 break;
188 case ORION_PCI_IO:
189 target = TARGET_PCI;
190 attr = ATTR_PCI_IO;
191 win = CPU_WIN_PCI_IO;
192 break;
193 case ORION_PCIE_MEM:
194 target = TARGET_PCIE;
195 attr = ATTR_PCIE_MEM;
196 win = CPU_WIN_PCIE_MEM;
197 break;
198 case ORION_PCI_MEM:
199 target = TARGET_PCI;
200 attr = ATTR_PCI_MEM;
201 win = CPU_WIN_PCI_MEM;
202 break;
203 case ORION_DEV_BOOT:
204 target = TARGET_DEV_BUS;
205 attr = ATTR_DEV_BOOT;
206 win = CPU_WIN_DEV_BOOT;
207 break;
208 case ORION_DEV0:
209 target = TARGET_DEV_BUS;
210 attr = ATTR_DEV_CS0;
211 win = CPU_WIN_DEV_CS0;
212 break;
213 case ORION_DEV1:
214 target = TARGET_DEV_BUS;
215 attr = ATTR_DEV_CS1;
216 win = CPU_WIN_DEV_CS1;
217 break;
218 case ORION_DEV2:
219 target = TARGET_DEV_BUS;
220 attr = ATTR_DEV_CS2;
221 win = CPU_WIN_DEV_CS2;
222 break;
223 case ORION_DDR:
224 case ORION_REGS:
225 /*
226 * Must be mapped by bootloader.
227 */
228 default:
229 target = attr = win = -1;
230 BUG();
231 }
232
233 base &= 0xffff0000;
234 ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
235 (target << 4) | WIN_EN);
236
237 orion_write(CPU_WIN_BASE(win), base);
238 orion_write(CPU_WIN_CTRL(win), ctrl);
239
240 if (orion_cpu_win_can_remap(win)) {
241 if (remap >= 0) {
242 orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
243 orion_write(CPU_WIN_REMAP_HI(win), 0);
244 } else {
245 orion_write(CPU_WIN_REMAP_LO(win), base);
246 orion_write(CPU_WIN_REMAP_HI(win), 0);
247 }
248 }
249}
250
251void __init orion_setup_cpu_wins(void)
252{
253 int i;
254
255 /*
256 * First, disable and clear windows
257 */
258 for (i = 0; i < CPU_MAX_WIN; i++) {
259 orion_write(CPU_WIN_BASE(i), 0);
260 orion_write(CPU_WIN_CTRL(i), 0);
261 if (orion_cpu_win_can_remap(i)) {
262 orion_write(CPU_WIN_REMAP_LO(i), 0);
263 orion_write(CPU_WIN_REMAP_HI(i), 0);
264 }
265 }
266
267 /*
268 * Setup windows for PCI+PCIE IO+MAM space
269 */
270 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
271 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
272 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
273 ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
274 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
275 ORION_PCIE_MEM_SIZE, -1);
276 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
277 ORION_PCI_MEM_SIZE, -1);
278}
279
280/*
281 * Setup PCIE BARs and Address Decode Wins:
282 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
283 * WIN[0-3] -> DRAM bank[0-3]
284 */
285void __init orion_setup_pcie_wins(void)
286{
287 u32 base, size, i;
288
289 /*
290 * First, disable and clear BARs and windows
291 */
292 for (i = 1; i < PCIE_MAX_BARS; i++) {
293 orion_write(PCIE_BAR_CTRL(i), 0);
294 orion_write(PCIE_BAR_LO(i), 0);
295 orion_write(PCIE_BAR_HI(i), 0);
296 }
297
298 for (i = 0; i < PCIE_MAX_WINS; i++) {
299 orion_write(PCIE_WIN_CTRL(i), 0);
300 orion_write(PCIE_WIN_BASE(i), 0);
301 orion_write(PCIE_WIN_REMAP(i), 0);
302 }
303
304 /*
305 * Setup windows for DDR banks. Count total DDR size on the fly.
306 */
307 base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
308 size = 0;
309 for (i = 0; i < DDR_MAX_CS; i++) {
310 u32 bank_base, bank_size;
311 bank_size = orion_read(DDR_SIZE_CS(i));
312 bank_base = orion_read(DDR_BASE_CS(i));
313 if (bank_size & DDR_BANK_EN) {
314 bank_size = DDR_REG_TO_SIZE(bank_size);
315 bank_base = DDR_REG_TO_BASE(bank_base);
316 orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
317 orion_write(PCIE_WIN_REMAP(i), 0);
318 orion_write(PCIE_WIN_CTRL(i),
319 ((bank_size-1) & 0xffff0000) |
320 (ATTR_DDR_CS(i) << 8) |
321 (TARGET_DDR << 4) |
322 (PCIE_DRAM_BAR << 1) | WIN_EN);
323 size += bank_size;
324 }
325 }
326
327 /*
328 * Setup BAR[1] to all DRAM banks
329 */
330 orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
331 orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
332 orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
333 ((size - 1) & 0xffff0000) | WIN_EN);
334}
335
336void __init orion_setup_pci_wins(void)
337{
338 u32 base, size, i;
339
340 /*
341 * First, disable windows
342 */
343 orion_write(PCI_BAR_ENABLE, 0xffffffff);
344
345 /*
346 * Setup windows for DDR banks.
347 */
348 for (i = 0; i < DDR_MAX_CS; i++) {
349 base = orion_read(DDR_BASE_CS(i));
350 size = orion_read(DDR_SIZE_CS(i));
351 if (size & DDR_BANK_EN) {
352 u32 bus, dev, func, reg, val;
353 size = DDR_REG_TO_SIZE(size);
354 base = DDR_REG_TO_BASE(base);
355 bus = orion_pci_local_bus_nr();
356 dev = orion_pci_local_dev_nr();
357 func = PCI_CONF_FUNC_BAR_CS(i);
358 reg = PCI_CONF_REG_BAR_LO_CS(i);
359 orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
360 orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
361 (base & 0xfffff000) | (val & 0xfff));
362 reg = PCI_CONF_REG_BAR_HI_CS(i);
363 orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
364 orion_write(PCI_BAR_SIZE_DDR_CS(i),
365 (size - 1) & 0xfffff000);
366 orion_write(PCI_BAR_REMAP_DDR_CS(i),
367 base & 0xfffff000);
368 orion_clrbits(PCI_BAR_ENABLE, (1 << i));
369 }
370 }
371
372 /*
373 * Disable automatic update of address remaping when writing to BARs
374 */
375 orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
376}
377
378void __init orion_setup_usb_wins(void)
379{
380 int i;
381 u32 usb_if, dev, rev;
382 u32 max_usb_if = 1;
383
384 orion_pcie_id(&dev, &rev);
385 if (dev == MV88F5182_DEV_ID)
386 max_usb_if = 2;
387
388 for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
389 /*
390 * First, disable and clear windows
391 */
392 for (i = 0; i < USB_MAX_WIN; i++) {
393 orion_write(USB_WIN_BASE(usb_if, i), 0);
394 orion_write(USB_WIN_CTRL(usb_if, i), 0);
395 }
396
397 /*
398 * Setup windows for DDR banks.
399 */
400 for (i = 0; i < DDR_MAX_CS; i++) {
401 u32 base, size;
402 size = orion_read(DDR_SIZE_CS(i));
403 base = orion_read(DDR_BASE_CS(i));
404 if (size & DDR_BANK_EN) {
405 base = DDR_REG_TO_BASE(base);
406 size = DDR_REG_TO_SIZE(size);
407 orion_write(USB_WIN_CTRL(usb_if, i),
408 ((size-1) & 0xffff0000) |
409 (ATTR_DDR_CS(i) << 8) |
410 (TARGET_DDR << 4) | WIN_EN);
411 orion_write(USB_WIN_BASE(usb_if, i),
412 base & 0xffff0000);
413 }
414 }
415 }
416}
417
418void __init orion_setup_eth_wins(void)
419{
420 int i;
421
422 /*
423 * First, disable and clear windows
424 */
425 for (i = 0; i < ETH_MAX_WIN; i++) {
426 orion_write(ETH_WIN_BASE(i), 0);
427 orion_write(ETH_WIN_SIZE(i), 0);
428 orion_setbits(ETH_WIN_EN, 1 << i);
429 orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
430 if (i < ETH_MAX_REMAP_WIN)
431 orion_write(ETH_WIN_REMAP(i), 0);
432 }
433
434 /*
435 * Setup windows for DDR banks.
436 */
437 for (i = 0; i < DDR_MAX_CS; i++) {
438 u32 base, size;
439 size = orion_read(DDR_SIZE_CS(i));
440 base = orion_read(DDR_BASE_CS(i));
441 if (size & DDR_BANK_EN) {
442 base = DDR_REG_TO_BASE(base);
443 size = DDR_REG_TO_SIZE(size);
444 orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
445 orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
446 (ATTR_DDR_CS(i) << 8) |
447 TARGET_DDR);
448 orion_clrbits(ETH_WIN_EN, 1 << i);
449 orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
450 }
451 }
452}
453
454void __init orion_setup_sata_wins(void)
455{
456 int i;
457
458 /*
459 * First, disable and clear windows
460 */
461 for (i = 0; i < SATA_MAX_WIN; i++) {
462 orion_write(SATA_WIN_BASE(i), 0);
463 orion_write(SATA_WIN_CTRL(i), 0);
464 }
465
466 /*
467 * Setup windows for DDR banks.
468 */
469 for (i = 0; i < DDR_MAX_CS; i++) {
470 u32 base, size;
471 size = orion_read(DDR_SIZE_CS(i));
472 base = orion_read(DDR_BASE_CS(i));
473 if (size & DDR_BANK_EN) {
474 base = DDR_REG_TO_BASE(base);
475 size = DDR_REG_TO_SIZE(size);
476 orion_write(SATA_WIN_CTRL(i),
477 ((size-1) & 0xffff0000) |
478 (ATTR_DDR_CS(i) << 8) |
479 (TARGET_DDR << 4) | WIN_EN);
480 orion_write(SATA_WIN_BASE(i),
481 base & 0xffff0000);
482 }
483 }
484}
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