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-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c283
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c313
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c175
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c687
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c517
-rw-r--r--arch/arm/mach-omap2/clock.c17
-rw-r--r--arch/arm/mach-omap2/clock.h20
-rw-r--r--arch/arm/mach-omap2/devices.c149
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c36
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c81
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c92
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c172
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h4
15 files changed, 1409 insertions, 1141 deletions
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 0f0a97c1fcc0..3662f4d4c8ea 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1739 1739
1740static struct omap_clk omap2420_clks[] = { 1740static struct omap_clk omap2420_clks[] = {
1741 /* external root sources */ 1741 /* external root sources */
1742 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), 1742 CLK(NULL, "func_32k_ck", &func_32k_ck),
1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), 1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1744 CLK(NULL, "osc_ck", &osc_ck, CK_242X), 1744 CLK(NULL, "osc_ck", &osc_ck),
1745 CLK(NULL, "sys_ck", &sys_ck, CK_242X), 1745 CLK(NULL, "sys_ck", &sys_ck),
1746 CLK(NULL, "alt_ck", &alt_ck, CK_242X), 1746 CLK(NULL, "alt_ck", &alt_ck),
1747 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), 1747 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1748 /* internal analog sources */ 1748 /* internal analog sources */
1749 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), 1749 CLK(NULL, "dpll_ck", &dpll_ck),
1750 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), 1750 CLK(NULL, "apll96_ck", &apll96_ck),
1751 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), 1751 CLK(NULL, "apll54_ck", &apll54_ck),
1752 /* internal prcm root sources */ 1752 /* internal prcm root sources */
1753 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), 1753 CLK(NULL, "func_54m_ck", &func_54m_ck),
1754 CLK(NULL, "core_ck", &core_ck, CK_242X), 1754 CLK(NULL, "core_ck", &core_ck),
1755 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), 1755 CLK(NULL, "func_96m_ck", &func_96m_ck),
1756 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), 1756 CLK(NULL, "func_48m_ck", &func_48m_ck),
1757 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), 1757 CLK(NULL, "func_12m_ck", &func_12m_ck),
1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), 1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1759 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), 1759 CLK(NULL, "sys_clkout", &sys_clkout),
1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), 1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src),
1761 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), 1761 CLK(NULL, "sys_clkout2", &sys_clkout2),
1762 CLK(NULL, "emul_ck", &emul_ck, CK_242X), 1762 CLK(NULL, "emul_ck", &emul_ck),
1763 /* mpu domain clocks */ 1763 /* mpu domain clocks */
1764 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), 1764 CLK(NULL, "mpu_ck", &mpu_ck),
1765 /* dsp domain clocks */ 1765 /* dsp domain clocks */
1766 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), 1766 CLK(NULL, "dsp_fck", &dsp_fck),
1767 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), 1767 CLK(NULL, "dsp_ick", &dsp_ick),
1768 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), 1768 CLK(NULL, "iva1_ifck", &iva1_ifck),
1769 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), 1769 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
1770 /* GFX domain clocks */ 1770 /* GFX domain clocks */
1771 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), 1771 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1772 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), 1772 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1773 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), 1773 CLK(NULL, "gfx_ick", &gfx_ick),
1774 /* DSS domain clocks */ 1774 /* DSS domain clocks */
1775 CLK("omapdss_dss", "ick", &dss_ick, CK_242X), 1775 CLK("omapdss_dss", "ick", &dss_ick),
1776 CLK(NULL, "dss_ick", &dss_ick, CK_242X), 1776 CLK(NULL, "dss_ick", &dss_ick),
1777 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), 1777 CLK(NULL, "dss1_fck", &dss1_fck),
1778 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), 1778 CLK(NULL, "dss2_fck", &dss2_fck),
1779 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), 1779 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1780 /* L3 domain clocks */ 1780 /* L3 domain clocks */
1781 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), 1781 CLK(NULL, "core_l3_ck", &core_l3_ck),
1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), 1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), 1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1784 /* L4 domain clocks */ 1784 /* L4 domain clocks */
1785 CLK(NULL, "l4_ck", &l4_ck, CK_242X), 1785 CLK(NULL, "l4_ck", &l4_ck),
1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), 1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1787 /* virtual meta-group clock */ 1787 /* virtual meta-group clock */
1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), 1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1789 /* general l4 interface ck, multi-parent functional clk */ 1789 /* general l4 interface ck, multi-parent functional clk */
1790 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), 1790 CLK(NULL, "gpt1_ick", &gpt1_ick),
1791 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), 1791 CLK(NULL, "gpt1_fck", &gpt1_fck),
1792 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), 1792 CLK(NULL, "gpt2_ick", &gpt2_ick),
1793 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), 1793 CLK(NULL, "gpt2_fck", &gpt2_fck),
1794 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), 1794 CLK(NULL, "gpt3_ick", &gpt3_ick),
1795 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), 1795 CLK(NULL, "gpt3_fck", &gpt3_fck),
1796 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), 1796 CLK(NULL, "gpt4_ick", &gpt4_ick),
1797 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), 1797 CLK(NULL, "gpt4_fck", &gpt4_fck),
1798 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), 1798 CLK(NULL, "gpt5_ick", &gpt5_ick),
1799 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), 1799 CLK(NULL, "gpt5_fck", &gpt5_fck),
1800 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), 1800 CLK(NULL, "gpt6_ick", &gpt6_ick),
1801 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), 1801 CLK(NULL, "gpt6_fck", &gpt6_fck),
1802 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), 1802 CLK(NULL, "gpt7_ick", &gpt7_ick),
1803 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), 1803 CLK(NULL, "gpt7_fck", &gpt7_fck),
1804 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), 1804 CLK(NULL, "gpt8_ick", &gpt8_ick),
1805 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), 1805 CLK(NULL, "gpt8_fck", &gpt8_fck),
1806 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), 1806 CLK(NULL, "gpt9_ick", &gpt9_ick),
1807 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), 1807 CLK(NULL, "gpt9_fck", &gpt9_fck),
1808 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), 1808 CLK(NULL, "gpt10_ick", &gpt10_ick),
1809 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), 1809 CLK(NULL, "gpt10_fck", &gpt10_fck),
1810 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), 1810 CLK(NULL, "gpt11_ick", &gpt11_ick),
1811 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), 1811 CLK(NULL, "gpt11_fck", &gpt11_fck),
1812 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), 1812 CLK(NULL, "gpt12_ick", &gpt12_ick),
1813 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), 1813 CLK(NULL, "gpt12_fck", &gpt12_fck),
1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), 1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1815 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), 1815 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1816 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), 1816 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1817 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), 1817 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1818 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), 1818 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1819 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), 1819 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1820 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), 1820 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1821 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), 1821 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1822 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), 1822 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1823 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), 1823 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1824 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), 1824 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1825 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), 1825 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1826 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), 1826 CLK(NULL, "uart1_ick", &uart1_ick),
1827 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), 1827 CLK(NULL, "uart1_fck", &uart1_fck),
1828 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), 1828 CLK(NULL, "uart2_ick", &uart2_ick),
1829 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), 1829 CLK(NULL, "uart2_fck", &uart2_fck),
1830 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), 1830 CLK(NULL, "uart3_ick", &uart3_ick),
1831 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), 1831 CLK(NULL, "uart3_fck", &uart3_fck),
1832 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), 1832 CLK(NULL, "gpios_ick", &gpios_ick),
1833 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), 1833 CLK(NULL, "gpios_fck", &gpios_fck),
1834 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), 1834 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1835 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), 1835 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1836 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), 1836 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1837 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), 1837 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1838 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), 1838 CLK(NULL, "wdt1_ick", &wdt1_ick),
1839 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), 1839 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1840 CLK("omap24xxcam", "fck", &cam_fck, CK_242X), 1840 CLK("omap24xxcam", "fck", &cam_fck),
1841 CLK(NULL, "cam_fck", &cam_fck, CK_242X), 1841 CLK(NULL, "cam_fck", &cam_fck),
1842 CLK("omap24xxcam", "ick", &cam_ick, CK_242X), 1842 CLK("omap24xxcam", "ick", &cam_ick),
1843 CLK(NULL, "cam_ick", &cam_ick, CK_242X), 1843 CLK(NULL, "cam_ick", &cam_ick),
1844 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), 1844 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1845 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), 1845 CLK(NULL, "wdt4_ick", &wdt4_ick),
1846 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), 1846 CLK(NULL, "wdt4_fck", &wdt4_fck),
1847 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), 1847 CLK(NULL, "wdt3_ick", &wdt3_ick),
1848 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), 1848 CLK(NULL, "wdt3_fck", &wdt3_fck),
1849 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), 1849 CLK(NULL, "mspro_ick", &mspro_ick),
1850 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), 1850 CLK(NULL, "mspro_fck", &mspro_fck),
1851 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), 1851 CLK("mmci-omap.0", "ick", &mmc_ick),
1852 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), 1852 CLK(NULL, "mmc_ick", &mmc_ick),
1853 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), 1853 CLK("mmci-omap.0", "fck", &mmc_fck),
1854 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), 1854 CLK(NULL, "mmc_fck", &mmc_fck),
1855 CLK(NULL, "fac_ick", &fac_ick, CK_242X), 1855 CLK(NULL, "fac_ick", &fac_ick),
1856 CLK(NULL, "fac_fck", &fac_fck, CK_242X), 1856 CLK(NULL, "fac_fck", &fac_fck),
1857 CLK(NULL, "eac_ick", &eac_ick, CK_242X), 1857 CLK(NULL, "eac_ick", &eac_ick),
1858 CLK(NULL, "eac_fck", &eac_fck, CK_242X), 1858 CLK(NULL, "eac_fck", &eac_fck),
1859 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), 1859 CLK("omap_hdq.0", "ick", &hdq_ick),
1860 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), 1860 CLK(NULL, "hdq_ick", &hdq_ick),
1861 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), 1861 CLK("omap_hdq.0", "fck", &hdq_fck),
1862 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), 1862 CLK(NULL, "hdq_fck", &hdq_fck),
1863 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), 1863 CLK("omap_i2c.1", "ick", &i2c1_ick),
1864 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), 1864 CLK(NULL, "i2c1_ick", &i2c1_ick),
1865 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), 1865 CLK(NULL, "i2c1_fck", &i2c1_fck),
1866 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), 1866 CLK("omap_i2c.2", "ick", &i2c2_ick),
1867 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), 1867 CLK(NULL, "i2c2_ick", &i2c2_ick),
1868 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), 1868 CLK(NULL, "i2c2_fck", &i2c2_fck),
1869 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), 1869 CLK(NULL, "gpmc_fck", &gpmc_fck),
1870 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), 1870 CLK(NULL, "sdma_fck", &sdma_fck),
1871 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), 1871 CLK(NULL, "sdma_ick", &sdma_ick),
1872 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), 1872 CLK(NULL, "sdrc_ick", &sdrc_ick),
1873 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), 1873 CLK(NULL, "vlynq_ick", &vlynq_ick),
1874 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), 1874 CLK(NULL, "vlynq_fck", &vlynq_fck),
1875 CLK(NULL, "des_ick", &des_ick, CK_242X), 1875 CLK(NULL, "des_ick", &des_ick),
1876 CLK("omap-sham", "ick", &sha_ick, CK_242X), 1876 CLK("omap-sham", "ick", &sha_ick),
1877 CLK(NULL, "sha_ick", &sha_ick, CK_242X), 1877 CLK(NULL, "sha_ick", &sha_ick),
1878 CLK("omap_rng", "ick", &rng_ick, CK_242X), 1878 CLK("omap_rng", "ick", &rng_ick),
1879 CLK(NULL, "rng_ick", &rng_ick, CK_242X), 1879 CLK(NULL, "rng_ick", &rng_ick),
1880 CLK("omap-aes", "ick", &aes_ick, CK_242X), 1880 CLK("omap-aes", "ick", &aes_ick),
1881 CLK(NULL, "aes_ick", &aes_ick, CK_242X), 1881 CLK(NULL, "aes_ick", &aes_ick),
1882 CLK(NULL, "pka_ick", &pka_ick, CK_242X), 1882 CLK(NULL, "pka_ick", &pka_ick),
1883 CLK(NULL, "usb_fck", &usb_fck, CK_242X), 1883 CLK(NULL, "usb_fck", &usb_fck),
1884 CLK("musb-hdrc", "fck", &osc_ck, CK_242X), 1884 CLK("musb-hdrc", "fck", &osc_ck),
1885 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), 1885 CLK(NULL, "timer_32k_ck", &func_32k_ck),
1886 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), 1886 CLK(NULL, "timer_sys_ck", &sys_ck),
1887 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), 1887 CLK(NULL, "timer_ext_ck", &alt_ck),
1888 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), 1888 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
1889}; 1889};
1890 1890
1891 1891
@@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = {
1904 1904
1905int __init omap2420_clk_init(void) 1905int __init omap2420_clk_init(void)
1906{ 1906{
1907 struct omap_clk *c;
1908
1909 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; 1907 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1910 cpu_mask = RATE_IN_242X; 1908 cpu_mask = RATE_IN_242X;
1911 rate_table = omap2420_rate_table; 1909 rate_table = omap2420_rate_table;
@@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void)
1914 1912
1915 omap2xxx_clkt_vps_check_bootloader_rates(); 1913 omap2xxx_clkt_vps_check_bootloader_rates();
1916 1914
1917 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); 1915 omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
1918 c++) {
1919 clkdev_add(&c->lk);
1920 if (!__clk_init(NULL, c->lk.clk))
1921 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1922 }
1923 1916
1924 omap2xxx_clkt_vps_late_init(); 1917 omap2xxx_clkt_vps_late_init();
1925 1918
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index aed8f74ca076..5e4b037bb24c 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1840,168 +1840,170 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1840 1840
1841static struct omap_clk omap2430_clks[] = { 1841static struct omap_clk omap2430_clks[] = {
1842 /* external root sources */ 1842 /* external root sources */
1843 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), 1843 CLK(NULL, "func_32k_ck", &func_32k_ck),
1844 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), 1844 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1845 CLK(NULL, "osc_ck", &osc_ck, CK_243X), 1845 CLK(NULL, "osc_ck", &osc_ck),
1846 CLK("twl", "fck", &osc_ck, CK_243X), 1846 CLK("twl", "fck", &osc_ck),
1847 CLK(NULL, "sys_ck", &sys_ck, CK_243X), 1847 CLK(NULL, "sys_ck", &sys_ck),
1848 CLK(NULL, "alt_ck", &alt_ck, CK_243X), 1848 CLK(NULL, "alt_ck", &alt_ck),
1849 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), 1849 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1850 /* internal analog sources */ 1850 /* internal analog sources */
1851 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), 1851 CLK(NULL, "dpll_ck", &dpll_ck),
1852 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), 1852 CLK(NULL, "apll96_ck", &apll96_ck),
1853 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), 1853 CLK(NULL, "apll54_ck", &apll54_ck),
1854 /* internal prcm root sources */ 1854 /* internal prcm root sources */
1855 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), 1855 CLK(NULL, "func_54m_ck", &func_54m_ck),
1856 CLK(NULL, "core_ck", &core_ck, CK_243X), 1856 CLK(NULL, "core_ck", &core_ck),
1857 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), 1857 CLK(NULL, "func_96m_ck", &func_96m_ck),
1858 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), 1858 CLK(NULL, "func_48m_ck", &func_48m_ck),
1859 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), 1859 CLK(NULL, "func_12m_ck", &func_12m_ck),
1860 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), 1860 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1861 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), 1861 CLK(NULL, "sys_clkout", &sys_clkout),
1862 CLK(NULL, "emul_ck", &emul_ck, CK_243X), 1862 CLK(NULL, "emul_ck", &emul_ck),
1863 /* mpu domain clocks */ 1863 /* mpu domain clocks */
1864 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), 1864 CLK(NULL, "mpu_ck", &mpu_ck),
1865 /* dsp domain clocks */ 1865 /* dsp domain clocks */
1866 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), 1866 CLK(NULL, "dsp_fck", &dsp_fck),
1867 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), 1867 CLK(NULL, "iva2_1_ick", &iva2_1_ick),
1868 /* GFX domain clocks */ 1868 /* GFX domain clocks */
1869 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), 1869 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1870 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), 1870 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1871 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), 1871 CLK(NULL, "gfx_ick", &gfx_ick),
1872 /* Modem domain clocks */ 1872 /* Modem domain clocks */
1873 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), 1873 CLK(NULL, "mdm_ick", &mdm_ick),
1874 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), 1874 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck),
1875 /* DSS domain clocks */ 1875 /* DSS domain clocks */
1876 CLK("omapdss_dss", "ick", &dss_ick, CK_243X), 1876 CLK("omapdss_dss", "ick", &dss_ick),
1877 CLK(NULL, "dss_ick", &dss_ick, CK_243X), 1877 CLK(NULL, "dss_ick", &dss_ick),
1878 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), 1878 CLK(NULL, "dss1_fck", &dss1_fck),
1879 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), 1879 CLK(NULL, "dss2_fck", &dss2_fck),
1880 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), 1880 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1881 /* L3 domain clocks */ 1881 /* L3 domain clocks */
1882 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), 1882 CLK(NULL, "core_l3_ck", &core_l3_ck),
1883 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), 1883 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1884 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), 1884 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1885 /* L4 domain clocks */ 1885 /* L4 domain clocks */
1886 CLK(NULL, "l4_ck", &l4_ck, CK_243X), 1886 CLK(NULL, "l4_ck", &l4_ck),
1887 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), 1887 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1888 /* virtual meta-group clock */ 1888 /* virtual meta-group clock */
1889 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), 1889 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1890 /* general l4 interface ck, multi-parent functional clk */ 1890 /* general l4 interface ck, multi-parent functional clk */
1891 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), 1891 CLK(NULL, "gpt1_ick", &gpt1_ick),
1892 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), 1892 CLK(NULL, "gpt1_fck", &gpt1_fck),
1893 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), 1893 CLK(NULL, "gpt2_ick", &gpt2_ick),
1894 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), 1894 CLK(NULL, "gpt2_fck", &gpt2_fck),
1895 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), 1895 CLK(NULL, "gpt3_ick", &gpt3_ick),
1896 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), 1896 CLK(NULL, "gpt3_fck", &gpt3_fck),
1897 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), 1897 CLK(NULL, "gpt4_ick", &gpt4_ick),
1898 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), 1898 CLK(NULL, "gpt4_fck", &gpt4_fck),
1899 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), 1899 CLK(NULL, "gpt5_ick", &gpt5_ick),
1900 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), 1900 CLK(NULL, "gpt5_fck", &gpt5_fck),
1901 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), 1901 CLK(NULL, "gpt6_ick", &gpt6_ick),
1902 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), 1902 CLK(NULL, "gpt6_fck", &gpt6_fck),
1903 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), 1903 CLK(NULL, "gpt7_ick", &gpt7_ick),
1904 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), 1904 CLK(NULL, "gpt7_fck", &gpt7_fck),
1905 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), 1905 CLK(NULL, "gpt8_ick", &gpt8_ick),
1906 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), 1906 CLK(NULL, "gpt8_fck", &gpt8_fck),
1907 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), 1907 CLK(NULL, "gpt9_ick", &gpt9_ick),
1908 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), 1908 CLK(NULL, "gpt9_fck", &gpt9_fck),
1909 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), 1909 CLK(NULL, "gpt10_ick", &gpt10_ick),
1910 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), 1910 CLK(NULL, "gpt10_fck", &gpt10_fck),
1911 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), 1911 CLK(NULL, "gpt11_ick", &gpt11_ick),
1912 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), 1912 CLK(NULL, "gpt11_fck", &gpt11_fck),
1913 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), 1913 CLK(NULL, "gpt12_ick", &gpt12_ick),
1914 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), 1914 CLK(NULL, "gpt12_fck", &gpt12_fck),
1915 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), 1915 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1916 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), 1916 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1917 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), 1917 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1918 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), 1918 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1919 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), 1919 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1920 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), 1920 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1921 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), 1921 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
1922 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), 1922 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
1923 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), 1923 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
1924 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), 1924 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
1925 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), 1925 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
1926 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), 1926 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
1927 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), 1927 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
1928 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), 1928 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
1929 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), 1929 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
1930 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), 1930 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1931 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), 1931 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1932 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), 1932 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1933 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), 1933 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1934 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), 1934 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1935 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), 1935 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1936 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), 1936 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
1937 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), 1937 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
1938 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), 1938 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
1939 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), 1939 CLK(NULL, "uart1_ick", &uart1_ick),
1940 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), 1940 CLK(NULL, "uart1_fck", &uart1_fck),
1941 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), 1941 CLK(NULL, "uart2_ick", &uart2_ick),
1942 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), 1942 CLK(NULL, "uart2_fck", &uart2_fck),
1943 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), 1943 CLK(NULL, "uart3_ick", &uart3_ick),
1944 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), 1944 CLK(NULL, "uart3_fck", &uart3_fck),
1945 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), 1945 CLK(NULL, "gpios_ick", &gpios_ick),
1946 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), 1946 CLK(NULL, "gpios_fck", &gpios_fck),
1947 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), 1947 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1948 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), 1948 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1949 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), 1949 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1950 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), 1950 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1951 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), 1951 CLK(NULL, "wdt1_ick", &wdt1_ick),
1952 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), 1952 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1953 CLK(NULL, "icr_ick", &icr_ick, CK_243X), 1953 CLK(NULL, "icr_ick", &icr_ick),
1954 CLK("omap24xxcam", "fck", &cam_fck, CK_243X), 1954 CLK("omap24xxcam", "fck", &cam_fck),
1955 CLK(NULL, "cam_fck", &cam_fck, CK_243X), 1955 CLK(NULL, "cam_fck", &cam_fck),
1956 CLK("omap24xxcam", "ick", &cam_ick, CK_243X), 1956 CLK("omap24xxcam", "ick", &cam_ick),
1957 CLK(NULL, "cam_ick", &cam_ick, CK_243X), 1957 CLK(NULL, "cam_ick", &cam_ick),
1958 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), 1958 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1959 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), 1959 CLK(NULL, "wdt4_ick", &wdt4_ick),
1960 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), 1960 CLK(NULL, "wdt4_fck", &wdt4_fck),
1961 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), 1961 CLK(NULL, "mspro_ick", &mspro_ick),
1962 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), 1962 CLK(NULL, "mspro_fck", &mspro_fck),
1963 CLK(NULL, "fac_ick", &fac_ick, CK_243X), 1963 CLK(NULL, "fac_ick", &fac_ick),
1964 CLK(NULL, "fac_fck", &fac_fck, CK_243X), 1964 CLK(NULL, "fac_fck", &fac_fck),
1965 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), 1965 CLK("omap_hdq.0", "ick", &hdq_ick),
1966 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), 1966 CLK(NULL, "hdq_ick", &hdq_ick),
1967 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), 1967 CLK("omap_hdq.1", "fck", &hdq_fck),
1968 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), 1968 CLK(NULL, "hdq_fck", &hdq_fck),
1969 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), 1969 CLK("omap_i2c.1", "ick", &i2c1_ick),
1970 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), 1970 CLK(NULL, "i2c1_ick", &i2c1_ick),
1971 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), 1971 CLK(NULL, "i2chs1_fck", &i2chs1_fck),
1972 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), 1972 CLK("omap_i2c.2", "ick", &i2c2_ick),
1973 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), 1973 CLK(NULL, "i2c2_ick", &i2c2_ick),
1974 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), 1974 CLK(NULL, "i2chs2_fck", &i2chs2_fck),
1975 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), 1975 CLK(NULL, "gpmc_fck", &gpmc_fck),
1976 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), 1976 CLK(NULL, "sdma_fck", &sdma_fck),
1977 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), 1977 CLK(NULL, "sdma_ick", &sdma_ick),
1978 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), 1978 CLK(NULL, "sdrc_ick", &sdrc_ick),
1979 CLK(NULL, "des_ick", &des_ick, CK_243X), 1979 CLK(NULL, "des_ick", &des_ick),
1980 CLK("omap-sham", "ick", &sha_ick, CK_243X), 1980 CLK("omap-sham", "ick", &sha_ick),
1981 CLK("omap_rng", "ick", &rng_ick, CK_243X), 1981 CLK(NULL, "sha_ick", &sha_ick),
1982 CLK(NULL, "rng_ick", &rng_ick, CK_243X), 1982 CLK("omap_rng", "ick", &rng_ick),
1983 CLK("omap-aes", "ick", &aes_ick, CK_243X), 1983 CLK(NULL, "rng_ick", &rng_ick),
1984 CLK(NULL, "pka_ick", &pka_ick, CK_243X), 1984 CLK("omap-aes", "ick", &aes_ick),
1985 CLK(NULL, "usb_fck", &usb_fck, CK_243X), 1985 CLK(NULL, "aes_ick", &aes_ick),
1986 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), 1986 CLK(NULL, "pka_ick", &pka_ick),
1987 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), 1987 CLK(NULL, "usb_fck", &usb_fck),
1988 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), 1988 CLK("musb-omap2430", "ick", &usbhs_ick),
1989 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), 1989 CLK(NULL, "usbhs_ick", &usbhs_ick),
1990 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), 1990 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
1991 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), 1991 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
1992 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), 1992 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
1993 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), 1993 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
1994 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), 1994 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
1995 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), 1995 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
1996 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 1996 CLK(NULL, "gpio5_ick", &gpio5_ick),
1997 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), 1997 CLK(NULL, "gpio5_fck", &gpio5_fck),
1998 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), 1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick),
1999 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), 1999 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck),
2000 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), 2000 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck),
2001 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), 2001 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck),
2002 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), 2002 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck),
2003 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), 2003 CLK(NULL, "timer_32k_ck", &func_32k_ck),
2004 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), 2004 CLK(NULL, "timer_sys_ck", &sys_ck),
2005 CLK(NULL, "timer_ext_ck", &alt_ck),
2006 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
2005}; 2007};
2006 2008
2007static const char *enable_init_clks[] = { 2009static const char *enable_init_clks[] = {
@@ -2019,8 +2021,6 @@ static const char *enable_init_clks[] = {
2019 2021
2020int __init omap2430_clk_init(void) 2022int __init omap2430_clk_init(void)
2021{ 2023{
2022 struct omap_clk *c;
2023
2024 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; 2024 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2025 cpu_mask = RATE_IN_243X; 2025 cpu_mask = RATE_IN_243X;
2026 rate_table = omap2430_rate_table; 2026 rate_table = omap2430_rate_table;
@@ -2029,12 +2029,7 @@ int __init omap2430_clk_init(void)
2029 2029
2030 omap2xxx_clkt_vps_check_bootloader_rates(); 2030 omap2xxx_clkt_vps_check_bootloader_rates();
2031 2031
2032 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); 2032 omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
2033 c++) {
2034 clkdev_add(&c->lk);
2035 if (!__clk_init(NULL, c->lk.clk))
2036 omap2_init_clk_hw_omap_clocks(c->lk.clk);
2037 }
2038 2033
2039 omap2xxx_clkt_vps_late_init(); 2034 omap2xxx_clkt_vps_late_init();
2040 2035
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b82066cb6..c8dcc523c31a 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -413,6 +413,14 @@ static struct clk smartreflex1_fck;
413DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); 413DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
414DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); 414DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
415 415
416static struct clk sha0_fck;
417DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
418DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
419
420static struct clk aes0_fck;
421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423
416/* 424/*
417 * Modules clock nodes 425 * Modules clock nodes
418 * 426 *
@@ -838,80 +846,82 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
838 * clkdev 846 * clkdev
839 */ 847 */
840static struct omap_clk am33xx_clks[] = { 848static struct omap_clk am33xx_clks[] = {
841 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), 849 CLK(NULL, "clk_32768_ck", &clk_32768_ck),
842 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), 850 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
843 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), 851 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
844 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), 852 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
845 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), 853 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
846 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), 854 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
847 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), 855 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
848 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), 856 CLK(NULL, "tclkin_ck", &tclkin_ck),
849 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), 857 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
850 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), 858 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
851 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), 859 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
852 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), 860 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
853 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), 861 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
854 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), 862 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
855 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), 863 CLK("cpu0", NULL, &dpll_mpu_ck),
856 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), 864 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
857 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), 865 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
858 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), 866 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
859 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), 867 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
860 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), 868 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
861 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), 869 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
862 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), 870 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
863 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), 871 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
864 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), 872 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
865 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), 873 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
866 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), 874 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
867 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), 875 CLK(NULL, "cefuse_fck", &cefuse_fck),
868 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX), 876 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
869 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), 877 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
870 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), 878 CLK(NULL, "dcan0_fck", &dcan0_fck),
871 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), 879 CLK("481cc000.d_can", NULL, &dcan0_fck),
872 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), 880 CLK(NULL, "dcan1_fck", &dcan1_fck),
873 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), 881 CLK("481d0000.d_can", NULL, &dcan1_fck),
874 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), 882 CLK(NULL, "debugss_ick", &debugss_ick),
875 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), 883 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
876 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), 884 CLK(NULL, "mcasp0_fck", &mcasp0_fck),
877 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), 885 CLK(NULL, "mcasp1_fck", &mcasp1_fck),
878 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), 886 CLK(NULL, "mmu_fck", &mmu_fck),
879 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), 887 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
880 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), 888 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
881 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), 889 CLK(NULL, "sha0_fck", &sha0_fck),
882 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), 890 CLK(NULL, "aes0_fck", &aes0_fck),
883 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), 891 CLK(NULL, "timer1_fck", &timer1_fck),
884 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), 892 CLK(NULL, "timer2_fck", &timer2_fck),
885 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), 893 CLK(NULL, "timer3_fck", &timer3_fck),
886 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), 894 CLK(NULL, "timer4_fck", &timer4_fck),
887 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), 895 CLK(NULL, "timer5_fck", &timer5_fck),
888 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), 896 CLK(NULL, "timer6_fck", &timer6_fck),
889 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), 897 CLK(NULL, "timer7_fck", &timer7_fck),
890 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), 898 CLK(NULL, "usbotg_fck", &usbotg_fck),
891 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), 899 CLK(NULL, "ieee5000_fck", &ieee5000_fck),
892 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), 900 CLK(NULL, "wdt1_fck", &wdt1_fck),
893 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), 901 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
894 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), 902 CLK(NULL, "l3_gclk", &l3_gclk),
895 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), 903 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
896 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), 904 CLK(NULL, "l4hs_gclk", &l4hs_gclk),
897 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), 905 CLK(NULL, "l3s_gclk", &l3s_gclk),
898 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), 906 CLK(NULL, "l4fw_gclk", &l4fw_gclk),
899 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), 907 CLK(NULL, "l4ls_gclk", &l4ls_gclk),
900 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), 908 CLK(NULL, "clk_24mhz", &clk_24mhz),
901 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), 909 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
902 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), 910 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
903 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), 911 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
904 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), 912 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
905 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), 913 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
906 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), 914 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
907 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), 915 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
908 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), 916 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
909 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), 917 CLK(NULL, "lcd_gclk", &lcd_gclk),
910 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), 918 CLK(NULL, "mmc_clk", &mmc_clk),
911 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), 919 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
912 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), 920 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
913 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), 921 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
914 CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), 922 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
923 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
924 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
915}; 925};
916 926
917 927
@@ -926,21 +936,10 @@ static const char *enable_init_clks[] = {
926 936
927int __init am33xx_clk_init(void) 937int __init am33xx_clk_init(void)
928{ 938{
929 struct omap_clk *c; 939 if (soc_is_am33xx())
930 u32 cpu_clkflg;
931
932 if (soc_is_am33xx()) {
933 cpu_mask = RATE_IN_AM33XX; 940 cpu_mask = RATE_IN_AM33XX;
934 cpu_clkflg = CK_AM33XX; 941
935 } 942 omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
936
937 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
938 if (c->cpu & cpu_clkflg) {
939 clkdev_add(&c->lk);
940 if (!__clk_init(NULL, c->lk.clk))
941 omap2_init_clk_hw_omap_clocks(c->lk.clk);
942 }
943 }
944 943
945 omap2_clk_disable_autoidle_all(); 944 omap2_clk_disable_autoidle_all();
946 945
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 4579c3c5338f..45cd26430d1f 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3219,289 +3219,327 @@ static struct clk_hw_omap wdt3_ick_hw = {
3219DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops); 3219DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3220 3220
3221/* 3221/*
3222 * clkdev 3222 * clocks specific to omap3430es1
3223 */
3224static struct omap_clk omap3430es1_clks[] = {
3225 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
3226 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
3227 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
3228 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
3229 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
3230 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
3231 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
3232 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
3233 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
3234 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
3235 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
3236 CLK(NULL, "fac_ick", &fac_ick),
3237 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
3238 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
3239 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
3240 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
3241 CLK(NULL, "dss_ick", &dss_ick_3430es1),
3242};
3243
3244/*
3245 * clocks specific to am35xx
3246 */
3247static struct omap_clk am35xx_clks[] = {
3248 CLK(NULL, "ipss_ick", &ipss_ick),
3249 CLK(NULL, "rmii_ck", &rmii_ck),
3250 CLK(NULL, "pclk_ck", &pclk_ck),
3251 CLK(NULL, "emac_ick", &emac_ick),
3252 CLK(NULL, "emac_fck", &emac_fck),
3253 CLK("davinci_emac.0", NULL, &emac_ick),
3254 CLK("davinci_mdio.0", NULL, &emac_fck),
3255 CLK("vpfe-capture", "master", &vpfe_ick),
3256 CLK("vpfe-capture", "slave", &vpfe_fck),
3257 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
3258 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
3259 CLK(NULL, "hecc_ck", &hecc_ck),
3260 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
3261 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
3262};
3263
3264/*
3265 * clocks specific to omap36xx
3266 */
3267static struct omap_clk omap36xx_clks[] = {
3268 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3269 CLK(NULL, "uart4_fck", &uart4_fck),
3270};
3271
3272/*
3273 * clocks common to omap36xx omap34xx
3274 */
3275static struct omap_clk omap34xx_omap36xx_clks[] = {
3276 CLK(NULL, "aes1_ick", &aes1_ick),
3277 CLK("omap_rng", "ick", &rng_ick),
3278 CLK(NULL, "sha11_ick", &sha11_ick),
3279 CLK(NULL, "des1_ick", &des1_ick),
3280 CLK(NULL, "cam_mclk", &cam_mclk),
3281 CLK(NULL, "cam_ick", &cam_ick),
3282 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
3283 CLK(NULL, "security_l3_ick", &security_l3_ick),
3284 CLK(NULL, "pka_ick", &pka_ick),
3285 CLK(NULL, "icr_ick", &icr_ick),
3286 CLK("omap-aes", "ick", &aes2_ick),
3287 CLK("omap-sham", "ick", &sha12_ick),
3288 CLK(NULL, "des2_ick", &des2_ick),
3289 CLK(NULL, "mspro_ick", &mspro_ick),
3290 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
3291 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
3292 CLK(NULL, "sr1_fck", &sr1_fck),
3293 CLK(NULL, "sr2_fck", &sr2_fck),
3294 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
3295 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
3296 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
3297 CLK(NULL, "dpll2_fck", &dpll2_fck),
3298 CLK(NULL, "iva2_ck", &iva2_ck),
3299 CLK(NULL, "modem_fck", &modem_fck),
3300 CLK(NULL, "sad2d_ick", &sad2d_ick),
3301 CLK(NULL, "mad2d_ick", &mad2d_ick),
3302 CLK(NULL, "mspro_fck", &mspro_fck),
3303 CLK(NULL, "dpll2_ck", &dpll2_ck),
3304 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
3305};
3306
3307/*
3308 * clocks common to omap36xx and omap3430es2plus
3309 */
3310static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3311 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
3312 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
3313 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
3314 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
3315 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
3316 CLK(NULL, "usim_fck", &usim_fck),
3317 CLK(NULL, "usim_ick", &usim_ick),
3318};
3319
3320/*
3321 * clocks common to am35xx omap36xx and omap3430es2plus
3322 */
3323static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3324 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
3325 CLK(NULL, "dpll5_ck", &dpll5_ck),
3326 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
3327 CLK(NULL, "sgx_fck", &sgx_fck),
3328 CLK(NULL, "sgx_ick", &sgx_ick),
3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3330 CLK(NULL, "ts_fck", &ts_fck),
3331 CLK(NULL, "usbtll_fck", &usbtll_fck),
3332 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
3333 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
3334 CLK(NULL, "usbtll_ick", &usbtll_ick),
3335 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
3336 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
3337 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3338 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3339 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
3340 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
3341 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
3342 CLK(NULL, "dss_ick", &dss_ick_3430es2),
3343 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3344 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3345 CLK(NULL, "usbhost_ick", &usbhost_ick),
3346 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
3347};
3348
3349/*
3350 * common clocks
3223 */ 3351 */
3224static struct omap_clk omap3xxx_clks[] = { 3352static struct omap_clk omap3xxx_clks[] = {
3225 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), 3353 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
3226 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), 3354 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
3227 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3355 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
3228 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3356 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
3229 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3357 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
3230 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX), 3358 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
3231 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), 3359 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
3232 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), 3360 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
3233 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3361 CLK("twl", "fck", &osc_sys_ck),
3234 CLK("twl", "fck", &osc_sys_ck, CK_3XXX), 3362 CLK(NULL, "sys_ck", &sys_ck),
3235 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3363 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3236 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), 3364 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
3237 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), 3365 CLK(NULL, "sys_altclk", &sys_altclk),
3238 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), 3366 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
3239 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3367 CLK(NULL, "sys_clkout1", &sys_clkout1),
3240 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), 3368 CLK(NULL, "dpll1_ck", &dpll1_ck),
3241 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), 3369 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
3242 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), 3370 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3243 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), 3371 CLK(NULL, "dpll3_ck", &dpll3_ck),
3244 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), 3372 CLK(NULL, "core_ck", &core_ck),
3245 CLK(NULL, "core_ck", &core_ck, CK_3XXX), 3373 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
3246 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), 3374 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
3247 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), 3375 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3248 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), 3376 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
3249 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), 3377 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3250 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), 3378 CLK(NULL, "dpll4_ck", &dpll4_ck),
3251 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), 3379 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
3252 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), 3380 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
3253 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), 3381 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
3254 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), 3382 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
3255 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), 3383 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
3256 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), 3384 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
3257 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), 3385 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
3258 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), 3386 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3259 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), 3387 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
3260 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), 3388 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3261 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), 3389 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
3262 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), 3390 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3263 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), 3391 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
3264 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), 3392 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3265 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), 3393 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
3266 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), 3394 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3267 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), 3395 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
3268 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), 3396 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
3269 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), 3397 CLK(NULL, "sys_clkout2", &sys_clkout2),
3270 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), 3398 CLK(NULL, "corex2_fck", &corex2_fck),
3271 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), 3399 CLK(NULL, "dpll1_fck", &dpll1_fck),
3272 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3400 CLK(NULL, "mpu_ck", &mpu_ck),
3273 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3401 CLK(NULL, "arm_fck", &arm_fck),
3274 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), 3402 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3275 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), 3403 CLK(NULL, "l3_ick", &l3_ick),
3276 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), 3404 CLK(NULL, "l4_ick", &l4_ick),
3277 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), 3405 CLK(NULL, "rm_ick", &rm_ick),
3278 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), 3406 CLK(NULL, "gpt10_fck", &gpt10_fck),
3279 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), 3407 CLK(NULL, "gpt11_fck", &gpt11_fck),
3280 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), 3408 CLK(NULL, "core_96m_fck", &core_96m_fck),
3281 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), 3409 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
3282 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), 3410 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
3283 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), 3411 CLK(NULL, "i2c3_fck", &i2c3_fck),
3284 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), 3412 CLK(NULL, "i2c2_fck", &i2c2_fck),
3285 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), 3413 CLK(NULL, "i2c1_fck", &i2c1_fck),
3286 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), 3414 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
3287 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), 3415 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
3288 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), 3416 CLK(NULL, "core_48m_fck", &core_48m_fck),
3289 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), 3417 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
3290 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), 3418 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
3291 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3419 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
3292 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3420 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
3293 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), 3421 CLK(NULL, "uart2_fck", &uart2_fck),
3294 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), 3422 CLK(NULL, "uart1_fck", &uart1_fck),
3295 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), 3423 CLK(NULL, "core_12m_fck", &core_12m_fck),
3296 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), 3424 CLK("omap_hdq.0", "fck", &hdq_fck),
3297 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), 3425 CLK(NULL, "hdq_fck", &hdq_fck),
3298 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), 3426 CLK(NULL, "core_l3_ick", &core_l3_ick),
3299 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3427 CLK(NULL, "sdrc_ick", &sdrc_ick),
3300 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3428 CLK(NULL, "gpmc_fck", &gpmc_fck),
3301 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3429 CLK(NULL, "core_l4_ick", &core_l4_ick),
3302 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3430 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
3303 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3431 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
3304 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3432 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
3305 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3433 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
3306 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), 3434 CLK("omap_hdq.0", "ick", &hdq_ick),
3307 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), 3435 CLK(NULL, "hdq_ick", &hdq_ick),
3308 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), 3436 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
3309 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), 3437 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
3310 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), 3438 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
3311 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), 3439 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
3312 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), 3440 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
3313 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), 3441 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
3314 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), 3442 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
3315 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), 3443 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
3316 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), 3444 CLK("omap_i2c.3", "ick", &i2c3_ick),
3317 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), 3445 CLK("omap_i2c.2", "ick", &i2c2_ick),
3318 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), 3446 CLK("omap_i2c.1", "ick", &i2c1_ick),
3319 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), 3447 CLK(NULL, "i2c3_ick", &i2c3_ick),
3320 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), 3448 CLK(NULL, "i2c2_ick", &i2c2_ick),
3321 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), 3449 CLK(NULL, "i2c1_ick", &i2c1_ick),
3322 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), 3450 CLK(NULL, "uart2_ick", &uart2_ick),
3323 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), 3451 CLK(NULL, "uart1_ick", &uart1_ick),
3324 CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), 3452 CLK(NULL, "gpt11_ick", &gpt11_ick),
3325 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), 3453 CLK(NULL, "gpt10_ick", &gpt10_ick),
3326 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), 3454 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
3327 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), 3455 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
3328 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), 3456 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
3329 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), 3457 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
3330 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3458 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
3331 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), 3459 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
3332 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3460 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
3333 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), 3461 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
3334 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), 3462 CLK(NULL, "utmi_p1_gfclk", &dummy_ck),
3335 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), 3463 CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
3336 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), 3464 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
3337 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), 3465 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
3338 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3466 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
3339 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3467 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
3340 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3468 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3341 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3469 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3342 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3470 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3343 CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3471 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3344 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), 3472 CLK(NULL, "init_60m_fclk", &dummy_ck),
3345 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), 3473 CLK(NULL, "gpt1_fck", &gpt1_fck),
3346 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), 3474 CLK(NULL, "aes2_ick", &aes2_ick),
3347 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), 3475 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
3348 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), 3476 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
3349 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), 3477 CLK(NULL, "sha12_ick", &sha12_ick),
3350 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), 3478 CLK(NULL, "wdt2_fck", &wdt2_fck),
3351 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), 3479 CLK("omap_wdt", "ick", &wdt2_ick),
3352 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), 3480 CLK(NULL, "wdt2_ick", &wdt2_ick),
3353 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3481 CLK(NULL, "wdt1_ick", &wdt1_ick),
3354 CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), 3482 CLK(NULL, "gpio1_ick", &gpio1_ick),
3355 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3483 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
3356 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), 3484 CLK(NULL, "gpt12_ick", &gpt12_ick),
3357 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), 3485 CLK(NULL, "gpt1_ick", &gpt1_ick),
3358 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), 3486 CLK(NULL, "per_96m_fck", &per_96m_fck),
3359 CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), 3487 CLK(NULL, "per_48m_fck", &per_48m_fck),
3360 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), 3488 CLK(NULL, "uart3_fck", &uart3_fck),
3361 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), 3489 CLK(NULL, "gpt2_fck", &gpt2_fck),
3362 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), 3490 CLK(NULL, "gpt3_fck", &gpt3_fck),
3363 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), 3491 CLK(NULL, "gpt4_fck", &gpt4_fck),
3364 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), 3492 CLK(NULL, "gpt5_fck", &gpt5_fck),
3365 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), 3493 CLK(NULL, "gpt6_fck", &gpt6_fck),
3366 CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), 3494 CLK(NULL, "gpt7_fck", &gpt7_fck),
3367 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), 3495 CLK(NULL, "gpt8_fck", &gpt8_fck),
3368 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), 3496 CLK(NULL, "gpt9_fck", &gpt9_fck),
3369 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), 3497 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
3370 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), 3498 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
3371 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), 3499 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
3372 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), 3500 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
3373 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), 3501 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
3374 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), 3502 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
3375 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), 3503 CLK(NULL, "wdt3_fck", &wdt3_fck),
3376 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), 3504 CLK(NULL, "per_l4_ick", &per_l4_ick),
3377 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), 3505 CLK(NULL, "gpio6_ick", &gpio6_ick),
3378 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), 3506 CLK(NULL, "gpio5_ick", &gpio5_ick),
3379 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), 3507 CLK(NULL, "gpio4_ick", &gpio4_ick),
3380 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), 3508 CLK(NULL, "gpio3_ick", &gpio3_ick),
3381 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), 3509 CLK(NULL, "gpio2_ick", &gpio2_ick),
3382 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), 3510 CLK(NULL, "wdt3_ick", &wdt3_ick),
3383 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), 3511 CLK(NULL, "uart3_ick", &uart3_ick),
3384 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), 3512 CLK(NULL, "uart4_ick", &uart4_ick),
3385 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), 3513 CLK(NULL, "gpt9_ick", &gpt9_ick),
3386 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), 3514 CLK(NULL, "gpt8_ick", &gpt8_ick),
3387 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), 3515 CLK(NULL, "gpt7_ick", &gpt7_ick),
3388 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), 3516 CLK(NULL, "gpt6_ick", &gpt6_ick),
3389 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), 3517 CLK(NULL, "gpt5_ick", &gpt5_ick),
3390 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3518 CLK(NULL, "gpt4_ick", &gpt4_ick),
3391 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), 3519 CLK(NULL, "gpt3_ick", &gpt3_ick),
3392 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), 3520 CLK(NULL, "gpt2_ick", &gpt2_ick),
3393 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), 3521 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
3394 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), 3522 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
3395 CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), 3523 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
3396 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3524 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
3397 CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3525 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
3398 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), 3526 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
3399 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), 3527 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
3400 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), 3528 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
3401 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3529 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
3402 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3530 CLK("etb", "emu_src_ck", &emu_src_ck),
3403 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3531 CLK(NULL, "emu_src_ck", &emu_src_ck),
3404 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3532 CLK(NULL, "pclk_fck", &pclk_fck),
3405 CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX), 3533 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
3406 CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX), 3534 CLK(NULL, "atclk_fck", &atclk_fck),
3407 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), 3535 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
3408 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), 3536 CLK(NULL, "traceclk_fck", &traceclk_fck),
3409 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), 3537 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
3410 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), 3538 CLK(NULL, "gpt12_fck", &gpt12_fck),
3411 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), 3539 CLK(NULL, "wdt1_fck", &wdt1_fck),
3412 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), 3540 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
3413 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), 3541 CLK(NULL, "timer_sys_ck", &sys_ck),
3414 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), 3542 CLK(NULL, "cpufreq_ck", &dpll1_ck),
3415 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3416 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3417 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3418 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3419 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3420 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3421 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3422 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3423 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3424 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
3425 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3426 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3427 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3428 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3429 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3430 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3431 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3432 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3433 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3434 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3435 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3436 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3437 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3438 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3439 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3440 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3441 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3442 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3443 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3444 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3445 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3446 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3447 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3448 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3449 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3450 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3451 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3452 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3453 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3454 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3455 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3456 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3457 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3458 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3459 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3460 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3461 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3462 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3463 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3464 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3465 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3466 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3467 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3468 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3469 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3470 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
3471 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
3472 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
3473 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3474 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3475 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3476 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3477 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
3478 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3479 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3480 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3481 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3482 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3483 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3484 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3485 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3486 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3487 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3488 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3489 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3490 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3491 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3492 CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
3493 CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
3494 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3495 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3496 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3497 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3498 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3499 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3500 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3501 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3502 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3503 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3504 CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
3505}; 3543};
3506 3544
3507static const char *enable_init_clks[] = { 3545static const char *enable_init_clks[] = {
@@ -3512,8 +3550,27 @@ static const char *enable_init_clks[] = {
3512 3550
3513int __init omap3xxx_clk_init(void) 3551int __init omap3xxx_clk_init(void)
3514{ 3552{
3515 struct omap_clk *c; 3553 if (omap3_has_192mhz_clk())
3516 u32 cpu_clkflg = 0; 3554 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3555
3556 if (cpu_is_omap3630()) {
3557 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3558 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3559 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3560 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3561 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3562 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3563 }
3564
3565 /*
3566 * XXX This type of dynamic rewriting of the clock tree is
3567 * deprecated and should be revised soon.
3568 */
3569 if (cpu_is_omap3630())
3570 dpll4_dd = dpll4_dd_3630;
3571 else
3572 dpll4_dd = dpll4_dd_34xx;
3573
3517 3574
3518 /* 3575 /*
3519 * 3505 must be tested before 3517, since 3517 returns true 3576 * 3505 must be tested before 3517, since 3517 returns true
@@ -3523,13 +3580,20 @@ int __init omap3xxx_clk_init(void)
3523 */ 3580 */
3524 if (soc_is_am35xx()) { 3581 if (soc_is_am35xx()) {
3525 cpu_mask = RATE_IN_34XX; 3582 cpu_mask = RATE_IN_34XX;
3526 cpu_clkflg = CK_AM35XX; 3583 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3584 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3585 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3586 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3527 } else if (cpu_is_omap3630()) { 3587 } else if (cpu_is_omap3630()) {
3528 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); 3588 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3529 cpu_clkflg = CK_36XX; 3589 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3530 } else if (cpu_is_ti816x()) { 3590 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3531 cpu_mask = RATE_IN_TI816X; 3591 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3532 cpu_clkflg = CK_TI816X; 3592 omap_clocks_register(omap34xx_omap36xx_clks,
3593 ARRAY_SIZE(omap34xx_omap36xx_clks));
3594 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3595 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3596 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3533 } else if (soc_is_am33xx()) { 3597 } else if (soc_is_am33xx()) {
3534 cpu_mask = RATE_IN_AM33XX; 3598 cpu_mask = RATE_IN_AM33XX;
3535 } else if (cpu_is_ti814x()) { 3599 } else if (cpu_is_ti814x()) {
@@ -3537,49 +3601,32 @@ int __init omap3xxx_clk_init(void)
3537 } else if (cpu_is_omap34xx()) { 3601 } else if (cpu_is_omap34xx()) {
3538 if (omap_rev() == OMAP3430_REV_ES1_0) { 3602 if (omap_rev() == OMAP3430_REV_ES1_0) {
3539 cpu_mask = RATE_IN_3430ES1; 3603 cpu_mask = RATE_IN_3430ES1;
3540 cpu_clkflg = CK_3430ES1; 3604 omap_clocks_register(omap3430es1_clks,
3605 ARRAY_SIZE(omap3430es1_clks));
3606 omap_clocks_register(omap34xx_omap36xx_clks,
3607 ARRAY_SIZE(omap34xx_omap36xx_clks));
3608 omap_clocks_register(omap3xxx_clks,
3609 ARRAY_SIZE(omap3xxx_clks));
3541 } else { 3610 } else {
3542 /* 3611 /*
3543 * Assume that anything that we haven't matched yet 3612 * Assume that anything that we haven't matched yet
3544 * has 3430ES2-type clocks. 3613 * has 3430ES2-type clocks.
3545 */ 3614 */
3546 cpu_mask = RATE_IN_3430ES2PLUS; 3615 cpu_mask = RATE_IN_3430ES2PLUS;
3547 cpu_clkflg = CK_3430ES2PLUS; 3616 omap_clocks_register(omap34xx_omap36xx_clks,
3617 ARRAY_SIZE(omap34xx_omap36xx_clks));
3618 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3619 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3620 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3621 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3622 omap_clocks_register(omap3xxx_clks,
3623 ARRAY_SIZE(omap3xxx_clks));
3548 } 3624 }
3549 } else { 3625 } else {
3550 WARN(1, "clock: could not identify OMAP3 variant\n"); 3626 WARN(1, "clock: could not identify OMAP3 variant\n");
3551 } 3627 }
3552 3628
3553 if (omap3_has_192mhz_clk()) 3629 omap2_clk_disable_autoidle_all();
3554 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3555
3556 if (cpu_is_omap3630()) {
3557 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3558 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3559 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3560 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3561 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3562 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3563 }
3564
3565 /*
3566 * XXX This type of dynamic rewriting of the clock tree is
3567 * deprecated and should be revised soon.
3568 */
3569 if (cpu_is_omap3630())
3570 dpll4_dd = dpll4_dd_3630;
3571 else
3572 dpll4_dd = dpll4_dd_34xx;
3573
3574 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3575 c++)
3576 if (c->cpu & cpu_clkflg) {
3577 clkdev_add(&c->lk);
3578 if (!__clk_init(NULL, c->lk.clk))
3579 omap2_init_clk_hw_omap_clocks(c->lk.clk);
3580 }
3581
3582 omap2_clk_disable_autoidle_all();
3583 3630
3584 omap2_clk_enable_init_clocks(enable_init_clks, 3631 omap2_clk_enable_init_clocks(enable_init_clks,
3585 ARRAY_SIZE(enable_init_clks)); 3632 ARRAY_SIZE(enable_init_clks));
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 0c6834ae1fc4..88e37a474334 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1424,284 +1424,285 @@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1424 0x0, NULL); 1424 0x0, NULL);
1425 1425
1426/* 1426/*
1427 * clkdev 1427 * clocks specific to omap4460
1428 */ 1428 */
1429static struct omap_clk omap446x_clks[] = {
1430 CLK(NULL, "div_ts_ck", &div_ts_ck),
1431 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
1432};
1433
1434/*
1435 * clocks specific to omap4430
1436 */
1437static struct omap_clk omap443x_clks[] = {
1438 CLK(NULL, "bandgap_fclk", &bandgap_fclk),
1439};
1429 1440
1441/*
1442 * clocks common to omap44xx
1443 */
1430static struct omap_clk omap44xx_clks[] = { 1444static struct omap_clk omap44xx_clks[] = {
1431 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), 1445 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
1432 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), 1446 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
1433 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), 1447 CLK(NULL, "pad_clks_ck", &pad_clks_ck),
1434 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), 1448 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
1435 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), 1449 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
1436 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), 1450 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
1437 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), 1451 CLK(NULL, "slimbus_clk", &slimbus_clk),
1438 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), 1452 CLK(NULL, "sys_32k_ck", &sys_32k_ck),
1439 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), 1453 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
1440 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), 1454 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
1441 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), 1455 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
1442 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), 1456 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
1443 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), 1457 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
1444 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), 1458 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
1445 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), 1459 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
1446 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), 1460 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
1447 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), 1461 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
1448 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), 1462 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
1449 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), 1463 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
1450 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), 1464 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
1451 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), 1465 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
1452 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), 1466 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
1453 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), 1467 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
1454 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), 1468 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
1455 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), 1469 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
1456 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), 1470 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
1457 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), 1471 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
1458 CLK(NULL, "abe_clk", &abe_clk, CK_443X), 1472 CLK(NULL, "abe_clk", &abe_clk),
1459 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), 1473 CLK(NULL, "aess_fclk", &aess_fclk),
1460 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), 1474 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
1461 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), 1475 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
1462 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), 1476 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
1463 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), 1477 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
1464 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), 1478 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
1465 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), 1479 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
1466 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), 1480 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
1467 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), 1481 CLK(NULL, "ddrphy_ck", &ddrphy_ck),
1468 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), 1482 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
1469 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), 1483 CLK(NULL, "div_core_ck", &div_core_ck),
1470 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), 1484 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
1471 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), 1485 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
1472 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), 1486 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
1473 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), 1487 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
1474 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), 1488 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
1475 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), 1489 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
1476 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), 1490 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
1477 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), 1491 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
1478 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), 1492 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
1479 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), 1493 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
1480 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), 1494 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
1481 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), 1495 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
1482 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), 1496 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
1483 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), 1497 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
1484 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), 1498 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
1485 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), 1499 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
1486 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), 1500 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
1487 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), 1501 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
1488 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), 1502 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
1489 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), 1503 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
1490 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), 1504 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
1491 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), 1505 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
1492 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), 1506 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
1493 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), 1507 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
1494 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), 1508 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
1495 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), 1509 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
1496 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), 1510 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
1497 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), 1511 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
1498 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), 1512 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
1499 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), 1513 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
1500 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), 1514 CLK(NULL, "func_12m_fclk", &func_12m_fclk),
1501 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), 1515 CLK(NULL, "func_24m_clk", &func_24m_clk),
1502 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), 1516 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
1503 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), 1517 CLK(NULL, "func_48m_fclk", &func_48m_fclk),
1504 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), 1518 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
1505 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), 1519 CLK(NULL, "func_64m_fclk", &func_64m_fclk),
1506 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), 1520 CLK(NULL, "func_96m_fclk", &func_96m_fclk),
1507 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), 1521 CLK(NULL, "init_60m_fclk", &init_60m_fclk),
1508 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), 1522 CLK(NULL, "l3_div_ck", &l3_div_ck),
1509 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), 1523 CLK(NULL, "l4_div_ck", &l4_div_ck),
1510 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), 1524 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
1511 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), 1525 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
1512 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), 1526 CLK("smp_twd", NULL, &mpu_periphclk),
1513 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), 1527 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
1514 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), 1528 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
1515 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), 1529 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
1516 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 1530 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
1517 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 1531 CLK(NULL, "aes1_fck", &aes1_fck),
1518 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 1532 CLK(NULL, "aes2_fck", &aes2_fck),
1519 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 1533 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
1520 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), 1534 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
1521 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), 1535 CLK(NULL, "dss_sys_clk", &dss_sys_clk),
1522 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 1536 CLK(NULL, "dss_tv_clk", &dss_tv_clk),
1523 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X), 1537 CLK(NULL, "dss_dss_clk", &dss_dss_clk),
1524 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), 1538 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
1525 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), 1539 CLK(NULL, "dss_fck", &dss_fck),
1526 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), 1540 CLK("omapdss_dss", "ick", &dss_fck),
1527 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), 1541 CLK(NULL, "fdif_fck", &fdif_fck),
1528 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 1542 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
1529 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 1543 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
1530 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 1544 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
1531 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), 1545 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
1532 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), 1546 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
1533 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), 1547 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
1534 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), 1548 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
1535 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), 1549 CLK(NULL, "hsi_fck", &hsi_fck),
1536 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), 1550 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
1537 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X), 1551 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
1538 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 1552 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
1539 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 1553 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
1540 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 1554 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
1541 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X), 1555 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
1542 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 1556 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
1543 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X), 1557 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
1544 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 1558 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
1545 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X), 1559 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
1546 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 1560 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
1547 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X), 1561 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
1548 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 1562 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
1549 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), 1563 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m),
1550 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), 1564 CLK(NULL, "sha2md5_fck", &sha2md5_fck),
1551 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), 1565 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
1552 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), 1566 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
1553 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 1567 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
1554 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 1568 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
1555 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 1569 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
1556 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), 1570 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
1557 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), 1571 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
1558 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), 1572 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
1559 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), 1573 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
1560 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), 1574 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
1561 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), 1575 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
1562 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), 1576 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
1563 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), 1577 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
1564 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X), 1578 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
1565 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X), 1579 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
1566 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X), 1580 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
1567 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X), 1581 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
1568 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X), 1582 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
1569 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X), 1583 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
1570 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X), 1584 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
1571 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X), 1585 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
1572 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X), 1586 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
1573 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X), 1587 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
1574 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X), 1588 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
1575 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 1589 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
1576 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), 1590 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
1577 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 1591 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
1578 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), 1592 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
1579 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), 1593 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
1580 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), 1594 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
1581 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), 1595 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
1582 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), 1596 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
1583 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), 1597 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
1584 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), 1598 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
1585 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), 1599 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
1586 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), 1600 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
1587 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), 1601 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
1588 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), 1602 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
1589 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), 1603 CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
1590 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), 1604 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
1591 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), 1605 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
1592 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), 1606 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
1593 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), 1607 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
1594 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), 1608 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
1595 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), 1609 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
1596 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), 1610 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
1597 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), 1611 CLK(NULL, "usim_ck", &usim_ck),
1598 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 1612 CLK(NULL, "usim_fclk", &usim_fclk),
1599 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 1613 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
1600 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 1614 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
1601 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 1615 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
1602 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 1616 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
1603 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 1617 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
1604 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 1618 CLK(NULL, "auxclk0_ck", &auxclk0_ck),
1605 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 1619 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
1606 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), 1620 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
1607 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), 1621 CLK(NULL, "auxclk1_ck", &auxclk1_ck),
1608 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), 1622 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
1609 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), 1623 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
1610 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), 1624 CLK(NULL, "auxclk2_ck", &auxclk2_ck),
1611 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), 1625 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
1612 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), 1626 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
1613 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), 1627 CLK(NULL, "auxclk3_ck", &auxclk3_ck),
1614 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), 1628 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
1615 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), 1629 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
1616 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), 1630 CLK(NULL, "auxclk4_ck", &auxclk4_ck),
1617 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), 1631 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
1618 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), 1632 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
1619 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), 1633 CLK(NULL, "auxclk5_ck", &auxclk5_ck),
1620 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), 1634 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
1621 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), 1635 CLK("omap-gpmc", "fck", &dummy_ck),
1622 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), 1636 CLK("omap_i2c.1", "ick", &dummy_ck),
1623 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), 1637 CLK("omap_i2c.2", "ick", &dummy_ck),
1624 CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), 1638 CLK("omap_i2c.3", "ick", &dummy_ck),
1625 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), 1639 CLK("omap_i2c.4", "ick", &dummy_ck),
1626 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 1640 CLK(NULL, "mailboxes_ick", &dummy_ck),
1627 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 1641 CLK("omap_hsmmc.0", "ick", &dummy_ck),
1628 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), 1642 CLK("omap_hsmmc.1", "ick", &dummy_ck),
1629 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), 1643 CLK("omap_hsmmc.2", "ick", &dummy_ck),
1630 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), 1644 CLK("omap_hsmmc.3", "ick", &dummy_ck),
1631 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), 1645 CLK("omap_hsmmc.4", "ick", &dummy_ck),
1632 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), 1646 CLK("omap-mcbsp.1", "ick", &dummy_ck),
1633 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), 1647 CLK("omap-mcbsp.2", "ick", &dummy_ck),
1634 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), 1648 CLK("omap-mcbsp.3", "ick", &dummy_ck),
1635 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 1649 CLK("omap-mcbsp.4", "ick", &dummy_ck),
1636 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 1650 CLK("omap2_mcspi.1", "ick", &dummy_ck),
1637 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 1651 CLK("omap2_mcspi.2", "ick", &dummy_ck),
1638 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 1652 CLK("omap2_mcspi.3", "ick", &dummy_ck),
1639 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 1653 CLK("omap2_mcspi.4", "ick", &dummy_ck),
1640 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 1654 CLK(NULL, "uart1_ick", &dummy_ck),
1641 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 1655 CLK(NULL, "uart2_ick", &dummy_ck),
1642 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 1656 CLK(NULL, "uart3_ick", &dummy_ck),
1643 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 1657 CLK(NULL, "uart4_ick", &dummy_ck),
1644 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 1658 CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
1645 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 1659 CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
1646 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 1660 CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
1647 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), 1661 CLK("omap_wdt", "ick", &dummy_ck),
1648 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), 1662 CLK(NULL, "timer_32k_ck", &sys_32k_ck),
1649 CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
1650 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
1651 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
1652 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ 1663 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1653 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1664 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
1654 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1665 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
1655 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1666 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
1656 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1667 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
1657 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1668 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
1658 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1669 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
1659 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1670 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
1660 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1671 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
1661 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1672 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
1662 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1673 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
1663 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1674 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
1664 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1675 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
1665 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1676 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
1666 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1677 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
1667 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1678 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
1668 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1679 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
1669 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1680 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
1670 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1681 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
1671 CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1682 CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
1672 CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1683 CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
1673 CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1684 CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
1674 CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1685 CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
1675 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), 1686 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
1676}; 1687};
1677 1688
1678int __init omap4xxx_clk_init(void) 1689int __init omap4xxx_clk_init(void)
1679{ 1690{
1680 u32 cpu_clkflg;
1681 struct omap_clk *c;
1682 int rc; 1691 int rc;
1683 1692
1684 if (cpu_is_omap443x()) { 1693 if (cpu_is_omap443x()) {
1685 cpu_mask = RATE_IN_4430; 1694 cpu_mask = RATE_IN_4430;
1686 cpu_clkflg = CK_443X; 1695 omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
1687 } else if (cpu_is_omap446x() || cpu_is_omap447x()) { 1696 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1688 cpu_mask = RATE_IN_4460 | RATE_IN_4430; 1697 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1689 cpu_clkflg = CK_446X | CK_443X; 1698 omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
1690
1691 if (cpu_is_omap447x()) 1699 if (cpu_is_omap447x())
1692 pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); 1700 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1693 } else { 1701 } else {
1694 return 0; 1702 return 0;
1695 } 1703 }
1696 1704
1697 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); 1705 omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
1698 c++) {
1699 if (c->cpu & cpu_clkflg) {
1700 clkdev_add(&c->lk);
1701 if (!__clk_init(NULL, c->lk.clk))
1702 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1703 }
1704 }
1705 1706
1706 omap2_clk_disable_autoidle_all(); 1707 omap2_clk_disable_autoidle_all();
1707 1708
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e4ec3a69ee2e..8474c7d228ee 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,7 +23,7 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26 26#include <linux/clk-private.h>
27#include <asm/cpu.h> 27#include <asm/cpu.h>
28 28
29 29
@@ -569,6 +569,21 @@ const struct clk_hw_omap_ops clkhwops_wait = {
569}; 569};
570 570
571/** 571/**
572 * omap_clocks_register - register an array of omap_clk
573 * @ocs: pointer to an array of omap_clk to register
574 */
575void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
576{
577 struct omap_clk *c;
578
579 for (c = oclks; c < oclks + cnt; c++) {
580 clkdev_add(&c->lk);
581 if (!__clk_init(NULL, c->lk.clk))
582 omap2_init_clk_hw_omap_clocks(c->lk.clk);
583 }
584}
585
586/**
572 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 587 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
573 * @mpurate_ck_name: clk name of the clock to change rate 588 * @mpurate_ck_name: clk name of the clock to change rate
574 * 589 *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 60ddd8612b4d..7aa32cd292f9 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -27,9 +27,8 @@ struct omap_clk {
27 struct clk_lookup lk; 27 struct clk_lookup lk;
28}; 28};
29 29
30#define CLK(dev, con, ck, cp) \ 30#define CLK(dev, con, ck) \
31 { \ 31 { \
32 .cpu = cp, \
33 .lk = { \ 32 .lk = { \
34 .dev_id = dev, \ 33 .dev_id = dev, \
35 .con_id = con, \ 34 .con_id = con, \
@@ -37,22 +36,6 @@ struct omap_clk {
37 }, \ 36 }, \
38 } 37 }
39 38
40/* Platform flags for the clkdev-OMAP integration code */
41#define CK_242X (1 << 0)
42#define CK_243X (1 << 1) /* 243x, 253x */
43#define CK_3430ES1 (1 << 2) /* 34xxES1 only */
44#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
45#define CK_AM35XX (1 << 4) /* Sitara AM35xx */
46#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
47#define CK_443X (1 << 6)
48#define CK_TI816X (1 << 7)
49#define CK_446X (1 << 8)
50#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
51
52
53#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
54#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
55
56struct clockdomain; 39struct clockdomain;
57#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 40#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
58 41
@@ -480,4 +463,5 @@ extern int am33xx_clk_init(void);
480extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 463extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
481extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 464extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
482 465
466extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
483#endif 467#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 1ec7f0597710..4269fc145698 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -504,140 +504,31 @@ static void omap_init_rng(void)
504 WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); 504 WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
505} 505}
506 506
507#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) 507static void __init omap_init_sham(void)
508
509#ifdef CONFIG_ARCH_OMAP2
510static struct resource omap2_sham_resources[] = {
511 {
512 .start = OMAP24XX_SEC_SHA1MD5_BASE,
513 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
514 .flags = IORESOURCE_MEM,
515 },
516 {
517 .start = 51 + OMAP_INTC_START,
518 .flags = IORESOURCE_IRQ,
519 }
520};
521static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
522#else
523#define omap2_sham_resources NULL
524#define omap2_sham_resources_sz 0
525#endif
526
527#ifdef CONFIG_ARCH_OMAP3
528static struct resource omap3_sham_resources[] = {
529 {
530 .start = OMAP34XX_SEC_SHA1MD5_BASE,
531 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
532 .flags = IORESOURCE_MEM,
533 },
534 {
535 .start = 49 + OMAP_INTC_START,
536 .flags = IORESOURCE_IRQ,
537 },
538 {
539 .start = OMAP34XX_DMA_SHA1MD5_RX,
540 .flags = IORESOURCE_DMA,
541 }
542};
543static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
544#else
545#define omap3_sham_resources NULL
546#define omap3_sham_resources_sz 0
547#endif
548
549static struct platform_device sham_device = {
550 .name = "omap-sham",
551 .id = -1,
552};
553
554static void omap_init_sham(void)
555{ 508{
556 if (cpu_is_omap24xx()) { 509 struct omap_hwmod *oh;
557 sham_device.resource = omap2_sham_resources; 510 struct platform_device *pdev;
558 sham_device.num_resources = omap2_sham_resources_sz;
559 } else if (cpu_is_omap34xx()) {
560 sham_device.resource = omap3_sham_resources;
561 sham_device.num_resources = omap3_sham_resources_sz;
562 } else {
563 pr_err("%s: platform not supported\n", __func__);
564 return;
565 }
566 platform_device_register(&sham_device);
567}
568#else
569static inline void omap_init_sham(void) { }
570#endif
571
572#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
573
574#ifdef CONFIG_ARCH_OMAP2
575static struct resource omap2_aes_resources[] = {
576 {
577 .start = OMAP24XX_SEC_AES_BASE,
578 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
579 .flags = IORESOURCE_MEM,
580 },
581 {
582 .start = OMAP24XX_DMA_AES_TX,
583 .flags = IORESOURCE_DMA,
584 },
585 {
586 .start = OMAP24XX_DMA_AES_RX,
587 .flags = IORESOURCE_DMA,
588 }
589};
590static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
591#else
592#define omap2_aes_resources NULL
593#define omap2_aes_resources_sz 0
594#endif
595 511
596#ifdef CONFIG_ARCH_OMAP3 512 oh = omap_hwmod_lookup("sham");
597static struct resource omap3_aes_resources[] = { 513 if (!oh)
598 { 514 return;
599 .start = OMAP34XX_SEC_AES_BASE,
600 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
601 .flags = IORESOURCE_MEM,
602 },
603 {
604 .start = OMAP34XX_DMA_AES2_TX,
605 .flags = IORESOURCE_DMA,
606 },
607 {
608 .start = OMAP34XX_DMA_AES2_RX,
609 .flags = IORESOURCE_DMA,
610 }
611};
612static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
613#else
614#define omap3_aes_resources NULL
615#define omap3_aes_resources_sz 0
616#endif
617 515
618static struct platform_device aes_device = { 516 pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
619 .name = "omap-aes", 517 WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
620 .id = -1, 518}
621};
622 519
623static void omap_init_aes(void) 520static void __init omap_init_aes(void)
624{ 521{
625 if (cpu_is_omap24xx()) { 522 struct omap_hwmod *oh;
626 aes_device.resource = omap2_aes_resources; 523 struct platform_device *pdev;
627 aes_device.num_resources = omap2_aes_resources_sz; 524
628 } else if (cpu_is_omap34xx()) { 525 oh = omap_hwmod_lookup("aes");
629 aes_device.resource = omap3_aes_resources; 526 if (!oh)
630 aes_device.num_resources = omap3_aes_resources_sz;
631 } else {
632 pr_err("%s: platform not supported\n", __func__);
633 return; 527 return;
634 }
635 platform_device_register(&aes_device);
636}
637 528
638#else 529 pdev = omap_device_build("omap-aes", -1, oh, NULL, 0);
639static inline void omap_init_aes(void) { } 530 WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
640#endif 531}
641 532
642/*-------------------------------------------------------------------------*/ 533/*-------------------------------------------------------------------------*/
643 534
@@ -764,11 +655,11 @@ static int __init omap2_init_devices(void)
764 omap_init_dmic(); 655 omap_init_dmic();
765 omap_init_mcpdm(); 656 omap_init_mcpdm();
766 omap_init_mcspi(); 657 omap_init_mcspi();
658 omap_init_sham();
659 omap_init_aes();
767 } 660 }
768 omap_init_sti(); 661 omap_init_sti();
769 omap_init_rng(); 662 omap_init_rng();
770 omap_init_sham();
771 omap_init_aes();
772 omap_init_vout(); 663 omap_init_vout();
773 omap_init_ocp2scp(); 664 omap_init_ocp2scp();
774 665
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6a764af6c6d3..5137cc84b504 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -610,6 +610,8 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
610 &omap2420_l4_core__mcbsp2, 610 &omap2420_l4_core__mcbsp2,
611 &omap2420_l4_core__msdi1, 611 &omap2420_l4_core__msdi1,
612 &omap2xxx_l4_core__rng, 612 &omap2xxx_l4_core__rng,
613 &omap2xxx_l4_core__sham,
614 &omap2xxx_l4_core__aes,
613 &omap2420_l4_core__hdq1w, 615 &omap2420_l4_core__hdq1w,
614 &omap2420_l4_wkup__counter_32k, 616 &omap2420_l4_wkup__counter_32k,
615 &omap2420_l3__gpmc, 617 &omap2420_l3__gpmc,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index d2d3840557c3..4ce999ee3ee9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -963,6 +963,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
963 &omap2430_l4_core__mcbsp5, 963 &omap2430_l4_core__mcbsp5,
964 &omap2430_l4_core__hdq1w, 964 &omap2430_l4_core__hdq1w,
965 &omap2xxx_l4_core__rng, 965 &omap2xxx_l4_core__rng,
966 &omap2xxx_l4_core__sham,
967 &omap2xxx_l4_core__aes,
966 &omap2430_l4_wkup__counter_32k, 968 &omap2430_l4_wkup__counter_32k,
967 &omap2430_l3__gpmc, 969 &omap2430_l3__gpmc,
968 NULL, 970 NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 47901a5e76de..5fd40d4a989e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -138,6 +138,24 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
138 { } 138 { }
139}; 139};
140 140
141static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
142 {
143 .pa_start = 0x480a4000,
144 .pa_end = 0x480a4000 + 0x64 - 1,
145 .flags = ADDR_TYPE_RT
146 },
147 { }
148};
149
150static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
151 {
152 .pa_start = 0x480a6000,
153 .pa_end = 0x480a6000 + 0x50 - 1,
154 .flags = ADDR_TYPE_RT
155 },
156 { }
157};
158
141/* 159/*
142 * Common interconnect data 160 * Common interconnect data
143 */ 161 */
@@ -389,3 +407,21 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
389 .addr = omap2_rng_addr_space, 407 .addr = omap2_rng_addr_space,
390 .user = OCP_USER_MPU | OCP_USER_SDMA, 408 .user = OCP_USER_MPU | OCP_USER_SDMA,
391}; 409};
410
411/* l4 core -> sham interface */
412struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
413 .master = &omap2xxx_l4_core_hwmod,
414 .slave = &omap2xxx_sham_hwmod,
415 .clk = "sha_ick",
416 .addr = omap2xxx_sham_addrs,
417 .user = OCP_USER_MPU | OCP_USER_SDMA,
418};
419
420/* l4 core -> aes interface */
421struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
422 .master = &omap2xxx_l4_core_hwmod,
423 .slave = &omap2xxx_aes_hwmod,
424 .clk = "aes_ick",
425 .addr = omap2xxx_aes_addrs,
426 .user = OCP_USER_MPU | OCP_USER_SDMA,
427};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index e596117004d4..c8c64b3e1acc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -864,3 +864,84 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
864 .flags = HWMOD_INIT_NO_RESET, 864 .flags = HWMOD_INIT_NO_RESET,
865 .class = &omap2_rng_hwmod_class, 865 .class = &omap2_rng_hwmod_class,
866}; 866};
867
868/* SHAM */
869
870static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
871 .rev_offs = 0x5c,
872 .sysc_offs = 0x60,
873 .syss_offs = 0x64,
874 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
875 SYSS_HAS_RESET_STATUS),
876 .sysc_fields = &omap_hwmod_sysc_type1,
877};
878
879static struct omap_hwmod_class omap2xxx_sham_class = {
880 .name = "sham",
881 .sysc = &omap2_sham_sysc,
882};
883
884static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
885 { .irq = 51 + OMAP_INTC_START, },
886 { .irq = -1 }
887};
888
889static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
890 { .name = "rx", .dma_req = 13 },
891 { .dma_req = -1 }
892};
893
894struct omap_hwmod omap2xxx_sham_hwmod = {
895 .name = "sham",
896 .mpu_irqs = omap2_sham_mpu_irqs,
897 .sdma_reqs = omap2_sham_sdma_chs,
898 .main_clk = "l4_ck",
899 .prcm = {
900 .omap2 = {
901 .module_offs = CORE_MOD,
902 .prcm_reg_id = 4,
903 .module_bit = OMAP24XX_EN_SHA_SHIFT,
904 .idlest_reg_id = 4,
905 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
906 },
907 },
908 .class = &omap2xxx_sham_class,
909};
910
911/* AES */
912
913static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
914 .rev_offs = 0x44,
915 .sysc_offs = 0x48,
916 .syss_offs = 0x4c,
917 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
918 SYSS_HAS_RESET_STATUS),
919 .sysc_fields = &omap_hwmod_sysc_type1,
920};
921
922static struct omap_hwmod_class omap2xxx_aes_class = {
923 .name = "aes",
924 .sysc = &omap2_aes_sysc,
925};
926
927static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
928 { .name = "tx", .dma_req = 9 },
929 { .name = "rx", .dma_req = 10 },
930 { .dma_req = -1 }
931};
932
933struct omap_hwmod omap2xxx_aes_hwmod = {
934 .name = "aes",
935 .sdma_reqs = omap2_aes_sdma_chs,
936 .main_clk = "l4_ck",
937 .prcm = {
938 .omap2 = {
939 .module_offs = CORE_MOD,
940 .prcm_reg_id = 4,
941 .module_bit = OMAP24XX_EN_AES_SHIFT,
942 .idlest_reg_id = 4,
943 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
944 },
945 },
946 .class = &omap2xxx_aes_class,
947};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 26eee4a556ad..556a1222fde6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -417,8 +417,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
417 * - clkdiv32k 417 * - clkdiv32k
418 * - debugss 418 * - debugss
419 * - ocp watch point 419 * - ocp watch point
420 * - aes0
421 * - sha0
422 */ 420 */
423#if 0 421#if 0
424/* 422/*
@@ -499,25 +497,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = {
499 }, 497 },
500 }, 498 },
501}; 499};
500#endif
502 501
503/* 502/*
504 * 'aes' class 503 * 'aes0' class
505 */ 504 */
506static struct omap_hwmod_class am33xx_aes_hwmod_class = { 505static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
507 .name = "aes", 506 .rev_offs = 0x80,
507 .sysc_offs = 0x84,
508 .syss_offs = 0x88,
509 .sysc_flags = SYSS_HAS_RESET_STATUS,
510};
511
512static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
513 .name = "aes0",
514 .sysc = &am33xx_aes0_sysc,
508}; 515};
509 516
510static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { 517static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
511 { .irq = 102 + OMAP_INTC_START, }, 518 { .irq = 103 + OMAP_INTC_START, },
512 { .irq = -1 }, 519 { .irq = -1 },
513}; 520};
514 521
522static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
523 { .name = "tx", .dma_req = 6, },
524 { .name = "rx", .dma_req = 5, },
525 { .dma_req = -1 }
526};
527
515static struct omap_hwmod am33xx_aes0_hwmod = { 528static struct omap_hwmod am33xx_aes0_hwmod = {
516 .name = "aes0", 529 .name = "aes",
517 .class = &am33xx_aes_hwmod_class, 530 .class = &am33xx_aes0_hwmod_class,
518 .clkdm_name = "l3_clkdm", 531 .clkdm_name = "l3_clkdm",
519 .mpu_irqs = am33xx_aes0_irqs, 532 .mpu_irqs = am33xx_aes0_irqs,
520 .main_clk = "l3_gclk", 533 .sdma_reqs = am33xx_aes0_edma_reqs,
534 .main_clk = "aes0_fck",
521 .prcm = { 535 .prcm = {
522 .omap4 = { 536 .omap4 = {
523 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, 537 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
@@ -526,21 +540,35 @@ static struct omap_hwmod am33xx_aes0_hwmod = {
526 }, 540 },
527}; 541};
528 542
529/* sha0 */ 543/* sha0 HIB2 (the 'P' (public) device) */
544static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
545 .rev_offs = 0x100,
546 .sysc_offs = 0x110,
547 .syss_offs = 0x114,
548 .sysc_flags = SYSS_HAS_RESET_STATUS,
549};
550
530static struct omap_hwmod_class am33xx_sha0_hwmod_class = { 551static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
531 .name = "sha0", 552 .name = "sha0",
553 .sysc = &am33xx_sha0_sysc,
532}; 554};
533 555
534static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { 556static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
535 { .irq = 108 + OMAP_INTC_START, }, 557 { .irq = 109 + OMAP_INTC_START, },
536 { .irq = -1 }, 558 { .irq = -1 },
537}; 559};
538 560
561static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
562 { .name = "rx", .dma_req = 36, },
563 { .dma_req = -1 }
564};
565
539static struct omap_hwmod am33xx_sha0_hwmod = { 566static struct omap_hwmod am33xx_sha0_hwmod = {
540 .name = "sha0", 567 .name = "sham",
541 .class = &am33xx_sha0_hwmod_class, 568 .class = &am33xx_sha0_hwmod_class,
542 .clkdm_name = "l3_clkdm", 569 .clkdm_name = "l3_clkdm",
543 .mpu_irqs = am33xx_sha0_irqs, 570 .mpu_irqs = am33xx_sha0_irqs,
571 .sdma_reqs = am33xx_sha0_edma_reqs,
544 .main_clk = "l3_gclk", 572 .main_clk = "l3_gclk",
545 .prcm = { 573 .prcm = {
546 .omap4 = { 574 .omap4 = {
@@ -550,8 +578,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
550 }, 578 },
551}; 579};
552 580
553#endif
554
555/* ocmcram */ 581/* ocmcram */
556static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { 582static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
557 .name = "ocmcram", 583 .name = "ocmcram",
@@ -3434,6 +3460,42 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3434 .user = OCP_USER_MPU | OCP_USER_SDMA, 3460 .user = OCP_USER_MPU | OCP_USER_SDMA,
3435}; 3461};
3436 3462
3463/* l3 main -> sha0 HIB2 */
3464static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
3465 {
3466 .pa_start = 0x53100000,
3467 .pa_end = 0x53100000 + SZ_512 - 1,
3468 .flags = ADDR_TYPE_RT
3469 },
3470 { }
3471};
3472
3473static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
3474 .master = &am33xx_l3_main_hwmod,
3475 .slave = &am33xx_sha0_hwmod,
3476 .clk = "sha0_fck",
3477 .addr = am33xx_sha0_addrs,
3478 .user = OCP_USER_MPU | OCP_USER_SDMA,
3479};
3480
3481/* l3 main -> AES0 HIB2 */
3482static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
3483 {
3484 .pa_start = 0x53500000,
3485 .pa_end = 0x53500000 + SZ_1M - 1,
3486 .flags = ADDR_TYPE_RT
3487 },
3488 { }
3489};
3490
3491static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
3492 .master = &am33xx_l3_main_hwmod,
3493 .slave = &am33xx_aes0_hwmod,
3494 .clk = "aes0_fck",
3495 .addr = am33xx_aes0_addrs,
3496 .user = OCP_USER_MPU | OCP_USER_SDMA,
3497};
3498
3437static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 3499static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3438 &am33xx_l4_fw__emif_fw, 3500 &am33xx_l4_fw__emif_fw,
3439 &am33xx_l3_main__emif, 3501 &am33xx_l3_main__emif,
@@ -3514,6 +3576,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3514 &am33xx_l3_s__usbss, 3576 &am33xx_l3_s__usbss,
3515 &am33xx_l4_hs__cpgmac0, 3577 &am33xx_l4_hs__cpgmac0,
3516 &am33xx_cpgmac0__mdio, 3578 &am33xx_cpgmac0__mdio,
3579 &am33xx_l3_main__sha0,
3580 &am33xx_l3_main__aes0,
3517 NULL, 3581 NULL,
3518}; 3582};
3519 3583
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5112d04e7b79..4083606ea1da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3550,6 +3550,132 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3550 .user = OCP_USER_MPU | OCP_USER_SDMA, 3550 .user = OCP_USER_MPU | OCP_USER_SDMA,
3551}; 3551};
3552 3552
3553/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3554static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3555 .sidle_shift = 4,
3556 .srst_shift = 1,
3557 .autoidle_shift = 0,
3558};
3559
3560static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3561 .rev_offs = 0x5c,
3562 .sysc_offs = 0x60,
3563 .syss_offs = 0x64,
3564 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3565 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3566 .sysc_fields = &omap3_sham_sysc_fields,
3567};
3568
3569static struct omap_hwmod_class omap3xxx_sham_class = {
3570 .name = "sham",
3571 .sysc = &omap3_sham_sysc,
3572};
3573
3574static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3575 { .irq = 49 + OMAP_INTC_START, },
3576 { .irq = -1 }
3577};
3578
3579static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3580 { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
3581 { .dma_req = -1 }
3582};
3583
3584static struct omap_hwmod omap3xxx_sham_hwmod = {
3585 .name = "sham",
3586 .mpu_irqs = omap3_sham_mpu_irqs,
3587 .sdma_reqs = omap3_sham_sdma_reqs,
3588 .main_clk = "sha12_ick",
3589 .prcm = {
3590 .omap2 = {
3591 .module_offs = CORE_MOD,
3592 .prcm_reg_id = 1,
3593 .module_bit = OMAP3430_EN_SHA12_SHIFT,
3594 .idlest_reg_id = 1,
3595 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3596 },
3597 },
3598 .class = &omap3xxx_sham_class,
3599};
3600
3601static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3602 {
3603 .pa_start = 0x480c3000,
3604 .pa_end = 0x480c3000 + 0x64 - 1,
3605 .flags = ADDR_TYPE_RT
3606 },
3607 { }
3608};
3609
3610static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3611 .master = &omap3xxx_l4_core_hwmod,
3612 .slave = &omap3xxx_sham_hwmod,
3613 .clk = "sha12_ick",
3614 .addr = omap3xxx_sham_addrs,
3615 .user = OCP_USER_MPU | OCP_USER_SDMA,
3616};
3617
3618/* l4_core -> AES */
3619static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3620 .sidle_shift = 6,
3621 .srst_shift = 1,
3622 .autoidle_shift = 0,
3623};
3624
3625static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3626 .rev_offs = 0x44,
3627 .sysc_offs = 0x48,
3628 .syss_offs = 0x4c,
3629 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3630 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3631 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3632 .sysc_fields = &omap3xxx_aes_sysc_fields,
3633};
3634
3635static struct omap_hwmod_class omap3xxx_aes_class = {
3636 .name = "aes",
3637 .sysc = &omap3_aes_sysc,
3638};
3639
3640static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3641 { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
3642 { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
3643 { .dma_req = -1 }
3644};
3645
3646static struct omap_hwmod omap3xxx_aes_hwmod = {
3647 .name = "aes",
3648 .sdma_reqs = omap3_aes_sdma_reqs,
3649 .main_clk = "aes2_ick",
3650 .prcm = {
3651 .omap2 = {
3652 .module_offs = CORE_MOD,
3653 .prcm_reg_id = 1,
3654 .module_bit = OMAP3430_EN_AES2_SHIFT,
3655 .idlest_reg_id = 1,
3656 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3657 },
3658 },
3659 .class = &omap3xxx_aes_class,
3660};
3661
3662static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3663 {
3664 .pa_start = 0x480c5000,
3665 .pa_end = 0x480c5000 + 0x50 - 1,
3666 .flags = ADDR_TYPE_RT
3667 },
3668 { }
3669};
3670
3671static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3672 .master = &omap3xxx_l4_core_hwmod,
3673 .slave = &omap3xxx_aes_hwmod,
3674 .clk = "aes2_ick",
3675 .addr = omap3xxx_aes_addrs,
3676 .user = OCP_USER_MPU | OCP_USER_SDMA,
3677};
3678
3553static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 3679static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3554 &omap3xxx_l3_main__l4_core, 3680 &omap3xxx_l3_main__l4_core,
3555 &omap3xxx_l3_main__l4_per, 3681 &omap3xxx_l3_main__l4_per,
@@ -3601,8 +3727,32 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3601}; 3727};
3602 3728
3603/* GP-only hwmod links */ 3729/* GP-only hwmod links */
3604static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { 3730static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3605 &omap3xxx_l4_sec__timer12, 3731 &omap3xxx_l4_sec__timer12,
3732 &omap3xxx_l4_core__sham,
3733 &omap3xxx_l4_core__aes,
3734 NULL
3735};
3736
3737static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3738 &omap3xxx_l4_sec__timer12,
3739 &omap3xxx_l4_core__sham,
3740 &omap3xxx_l4_core__aes,
3741 NULL
3742};
3743
3744static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3745 &omap3xxx_l4_sec__timer12,
3746 /*
3747 * Apparently the SHA/MD5 and AES accelerator IP blocks are
3748 * only present on some AM35xx chips, and no one knows which
3749 * ones. See
3750 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3751 * if you need these IP blocks on an AM35xx, try uncommenting
3752 * the following lines.
3753 */
3754 /* &omap3xxx_l4_core__sham, */
3755 /* &omap3xxx_l4_core__aes, */
3606 NULL 3756 NULL
3607}; 3757};
3608 3758
@@ -3709,7 +3859,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3709int __init omap3xxx_hwmod_init(void) 3859int __init omap3xxx_hwmod_init(void)
3710{ 3860{
3711 int r; 3861 int r;
3712 struct omap_hwmod_ocp_if **h = NULL; 3862 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
3713 unsigned int rev; 3863 unsigned int rev;
3714 3864
3715 omap_hwmod_init(); 3865 omap_hwmod_init();
@@ -3719,13 +3869,6 @@ int __init omap3xxx_hwmod_init(void)
3719 if (r < 0) 3869 if (r < 0)
3720 return r; 3870 return r;
3721 3871
3722 /* Register GP-only hwmod links. */
3723 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3724 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3725 if (r < 0)
3726 return r;
3727 }
3728
3729 rev = omap_rev(); 3872 rev = omap_rev();
3730 3873
3731 /* 3874 /*
@@ -3737,11 +3880,14 @@ int __init omap3xxx_hwmod_init(void)
3737 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3880 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3738 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3881 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3739 h = omap34xx_hwmod_ocp_ifs; 3882 h = omap34xx_hwmod_ocp_ifs;
3883 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3740 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 3884 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3741 h = am35xx_hwmod_ocp_ifs; 3885 h = am35xx_hwmod_ocp_ifs;
3886 h_gp = am35xx_gp_hwmod_ocp_ifs;
3742 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3887 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3743 rev == OMAP3630_REV_ES1_2) { 3888 rev == OMAP3630_REV_ES1_2) {
3744 h = omap36xx_hwmod_ocp_ifs; 3889 h = omap36xx_hwmod_ocp_ifs;
3890 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3745 } else { 3891 } else {
3746 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3892 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3747 return -EINVAL; 3893 return -EINVAL;
@@ -3751,6 +3897,14 @@ int __init omap3xxx_hwmod_init(void)
3751 if (r < 0) 3897 if (r < 0)
3752 return r; 3898 return r;
3753 3899
3900 /* Register GP-only hwmod links. */
3901 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3902 r = omap_hwmod_register_links(h_gp);
3903 if (r < 0)
3904 return r;
3905 }
3906
3907
3754 /* 3908 /*
3755 * Register hwmod links specific to certain ES levels of a 3909 * Register hwmod links specific to certain ES levels of a
3756 * particular family of silicon (e.g., 34xx ES1.0) 3910 * particular family of silicon (e.g., 34xx ES1.0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index cfcce299177c..6e04ff7065e1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -78,6 +78,8 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
78extern struct omap_hwmod omap2xxx_counter_32k_hwmod; 78extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
79extern struct omap_hwmod omap2xxx_gpmc_hwmod; 79extern struct omap_hwmod omap2xxx_gpmc_hwmod;
80extern struct omap_hwmod omap2xxx_rng_hwmod; 80extern struct omap_hwmod omap2xxx_rng_hwmod;
81extern struct omap_hwmod omap2xxx_sham_hwmod;
82extern struct omap_hwmod omap2xxx_aes_hwmod;
81 83
82/* Common interface data across OMAP2xxx */ 84/* Common interface data across OMAP2xxx */
83extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; 85extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -105,6 +107,8 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
105extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; 107extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
106extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; 108extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
107extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng; 109extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
110extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
111extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
108 112
109/* Common IP block data */ 113/* Common IP block data */
110extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; 114extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 07:32:00 -0500