Merge tag 'omap-for-v3.10/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

From Tony Lindgren <tony@atomide.com>:

Changes needed for enabling SOC_BUS for the SoC revision
information. Also enable few HW errata workarounds for omap4.

* tag 'omap-for-v3.10/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (236 commits)
  ARM: OMAP4: Enable fix for Cortex-A9 erratas
  ARM: OMAP2+: Export SoC information to userspace
  ARM: OMAP2+: SoC name and revision unification
  ARM: OMAP2+: Move common part of late init into common function

Includes an update to Linux 3.9-rc6

Conflicts:
	arch/arm/mach-omap2/cclock44xx_data.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

10 files changed, 177 insertions, 37 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8111cd9ff3e5..b56530cb5fa8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,6 +15,7 @@ config ARCH_OMAP2PLUS
         select OMAP_DM_TIMER
         select PINCTRL
         select PROC_DEVICETREE if PROC_FS
+        select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
         help
@@ -96,6 +97,8 @@ config ARCH_OMAP4
         select PM_RUNTIME if CPU_IDLE
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select COMMON_CLK
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_775420
 
 config SOC_OMAP5
         bool "TI OMAP5"
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index b1e77ef968fa..88e37a474334 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -52,6 +52,13 @@
  */
 #define OMAP4_DPLL_ABE_DEFFREQ                          98304000
 
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ                          960000000
+
 /* Root clocks */
 
 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
@@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
                     OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
                     hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
 
+DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
+
 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
                 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1549,6 +1560,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "per_mcbsp4_gfclk",             &per_mcbsp4_gfclk),
         CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk),
         CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m),
         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck),
         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1),
         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0),
@@ -1706,5 +1718,13 @@ int __init omap4xxx_clk_init(void)
         if (rc)
                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+        /*
+         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+         * domain can transition to retention state when not in use.
+         */
+        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+        if (rc)
+                pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
         return 0;
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 40f4a03d728f..1ddd0cb5fab9 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -110,6 +110,14 @@ void am35xx_init_late(void);
 void ti81xx_init_late(void);
 int omap2_common_pm_late_init(void);
 
+#ifdef CONFIG_SOC_BUS
+void omap_soc_device_init(void);
+#else
+static inline void omap_soc_device_init(void)
+{
+}
+#endif
+
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
 void omap2xxx_restart(char mode, const char *cmd);
 #else
@@ -293,5 +301,8 @@ extern void omap_reserve(void);
 struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 
+/* SoC specific clock initializer */
+extern int (*omap_clk_init)(void);
+
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 8a68f1ec66b9..098e94e31336 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,6 +18,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+
+#ifdef CONFIG_SOC_BUS
+#include <linux/sys_soc.h>
+#endif
 
 #include <asm/cputype.h>
 
@@ -31,8 +36,11 @@
 #define OMAP4_SILICON_TYPE_STANDARD             0x01
 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
 
+#define OMAP_SOC_MAX_NAME_LENGTH                16
+
 static unsigned int omap_revision;
-static const char *cpu_rev;
+static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
+static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
 u32 omap_features;
 
 unsigned int omap_rev(void)
@@ -169,9 +177,12 @@ void __init omap2xxx_check_revision(void)
                 j = i;
         }
 
-        pr_info("OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
+
+        pr_info("%s", soc_name);
         if ((omap_rev() >> 8) & 0x0f)
-                pr_info("ES%x", (omap_rev() >> 12) & 0xf);
+                pr_info("%s", soc_rev);
         pr_info("\n");
 }
 
@@ -211,8 +222,10 @@ static void __init omap3_cpuinfo(void)
                 cpu_name = "OMAP3503";
         }
 
+        sprintf(soc_name, "%s", cpu_name);
+
         /* Print verbose information */
-        pr_info("%s ES%s (", cpu_name, cpu_rev);
+        pr_info("%s %s (", soc_name, soc_rev);
 
         OMAP3_SHOW_FEATURE(l2cache);
         OMAP3_SHOW_FEATURE(iva);
@@ -291,6 +304,7 @@ void __init ti81xx_check_features(void)
 
 void __init omap3xxx_check_revision(void)
 {
+        const char *cpu_rev;
         u32 cpuid, idcode;
         u16 hawkeye;
         u8 rev;
@@ -438,6 +452,7 @@ void __init omap3xxx_check_revision(void)
                 cpu_rev = "1.2";
                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
         }
+        sprintf(soc_rev, "ES%s", cpu_rev);
 }
 
 void __init omap4xxx_check_revision(void)
@@ -512,8 +527,10 @@ void __init omap4xxx_check_revision(void)
                 omap_revision = OMAP4430_REV_ES2_3;
         }
 
-        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
-                ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
+                                                (omap_rev() >> 8) & 0xf);
+        pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 void __init omap5xxx_check_revision(void)
@@ -547,8 +564,10 @@ void __init omap5xxx_check_revision(void)
                 omap_revision = OMAP5430_REV_ES1_0;
         }
 
-        pr_info("OMAP%04x ES%d.0\n",
-                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
+
+        pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 /*
@@ -569,3 +588,63 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
         else
                 tap_prod_id = 0x0208;
 }
+
+#ifdef CONFIG_SOC_BUS
+
+static const char const *omap_types[] = {
+        [OMAP2_DEVICE_TYPE_TEST]        = "TST",
+        [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
+        [OMAP2_DEVICE_TYPE_SEC]         = "HS",
+        [OMAP2_DEVICE_TYPE_GP]          = "GP",
+        [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
+};
+
+static const char * __init omap_get_family(void)
+{
+        if (cpu_is_omap24xx())
+                return kasprintf(GFP_KERNEL, "OMAP2");
+        else if (cpu_is_omap34xx())
+                return kasprintf(GFP_KERNEL, "OMAP3");
+        else if (cpu_is_omap44xx())
+                return kasprintf(GFP_KERNEL, "OMAP4");
+        else if (soc_is_omap54xx())
+                return kasprintf(GFP_KERNEL, "OMAP5");
+        else
+                return kasprintf(GFP_KERNEL, "Unknown");
+}
+
+static ssize_t omap_get_type(struct device *dev,
+                                        struct device_attribute *attr,
+                                        char *buf)
+{
+        return sprintf(buf, "%s\n", omap_types[omap_type()]);
+}
+
+static struct device_attribute omap_soc_attr =
+        __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
+
+void __init omap_soc_device_init(void)
+{
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+
+        soc_dev_attr->machine  = soc_name;
+        soc_dev_attr->family   = omap_get_family();
+        soc_dev_attr->revision = soc_rev;
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR_OR_NULL(soc_dev)) {
+                kfree(soc_dev_attr);
+                return;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+        if (!IS_ERR_OR_NULL(parent))
+                device_create_file(parent, &omap_soc_attr);
+}
+#endif /* CONFIG_SOC_BUS */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2c3fdd65387b..3241f23afe09 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,6 +55,12 @@
 #include "prm44xx.h"
 
 /*
+ * omap_clk_init: points to a function that does the SoC-specific
+ * clock initializations
+ */
+int (*omap_clk_init)(void);
+
+/*
  * The machine specific code may provide the extra mapping besides the
  * default mapping provided here.
  */
@@ -379,6 +385,13 @@ static void __init omap_hwmod_init_postsetup(void)
         omap_pm_if_early_init();
 }
 
+static void __init omap_common_late_init(void)
+{
+        omap_mux_late_init();
+        omap2_common_pm_late_init();
+        omap_soc_device_init();
+}
+
 #ifdef CONFIG_SOC_OMAP2420
 void __init omap2420_init_early(void)
 {
@@ -397,13 +410,12 @@ void __init omap2420_init_early(void)
         omap242x_clockdomains_init();
         omap2420_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap2420_clk_init();
+        omap_clk_init = omap2420_clk_init;
 }
 
 void __init omap2420_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap2_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -427,13 +439,12 @@ void __init omap2430_init_early(void)
         omap243x_clockdomains_init();
         omap2430_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap2430_clk_init();
+        omap_clk_init = omap2430_clk_init;
 }
 
 void __init omap2430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap2_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -462,7 +473,7 @@ void __init omap3_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap3xxx_clk_init();
+        omap_clk_init = omap3xxx_clk_init;
 }
 
 void __init omap3430_init_early(void)
@@ -500,53 +511,47 @@ void __init ti81xx_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap3xxx_clk_init();
+        omap_clk_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap3430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap35xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap3630_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init am35xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init ti81xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -568,7 +573,7 @@ void __init am33xx_init_early(void)
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        am33xx_clk_init();
+        omap_clk_init = am33xx_clk_init;
 }
 #endif
 
@@ -593,13 +598,12 @@ void __init omap4430_init_early(void)
         omap44xx_clockdomains_init();
         omap44xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap4xxx_clk_init();
+        omap_clk_init = omap4xxx_clk_init;
 }
 
 void __init omap4430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap4_pm_init();
         omap2_clk_enable_autoidle_all();
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c2c798c08c2b..a202a4785104 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                if (oh->flags & HWMOD_FORCE_MSTANDBY) {
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
                         idlemode = HWMOD_IDLEMODE_NO;
                 } else {
                         if (sf & SYSC_HAS_ENAWAKEUP)
@@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
+                    (oh->flags & HWMOD_FORCE_MSTANDBY)) {
                         idlemode = HWMOD_IDLEMODE_FORCE;
                 } else {
                         if (sf & SYSC_HAS_ENAWAKEUP)
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d43d9b608eda..d5dc935f6060 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
  *
  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
  *     of idle, rather than relying on module smart-idle
- * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
- *     of standby, rather than relying on module smart-standby
+ * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
+ *     out of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
  *     XXX Should be HWMOD_SETUP_NO_RESET
@@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
  *     correctly, or this is being abused to deal with some PM latency
  *     issues -- but we're currently suffering from a shortage of
  *     folks who are able to track these issues down properly.
+ * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
+ *     is kept in force-standby mode. Failing to do so causes PM problems
+ *     with musb on OMAP3630 at least. Note that musb has a dedicated register
+ *     to control MSTANDBY signal when MIDLEMODE is set to force-standby.
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_16BIT_REG                         (1 << 8)
 #define HWMOD_EXT_OPT_MAIN_CLK                  (1 << 9)
 #define HWMOD_BLOCK_WFI                         (1 << 10)
+#define HWMOD_FORCE_MSTANDBY                    (1 << 11)
 
 /*
  * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 85c917cb193d..4083606ea1da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
          * broken when autoidle is enabled
          * workaround is to disable the autoidle bit at module level.
+         *
+         * Enabling the device in any other MIDLEMODE setting but force-idle
+         * causes core_pwrdm not enter idle states at least on OMAP3630.
+         * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
+         * signal when MIDLEMODE is set to force-idle.
          */
         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
-                                | HWMOD_SWSUP_MSTANDBY,
+                                | HWMOD_FORCE_MSTANDBY,
 };
 
 /* usb_otg_hs */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0e47d2e1687c..9e0576569e07 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
         { }
 };
 
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+        { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
+};
+
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
@@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                 },
         },
         .dev_attr       = ocp2scp_dev_attr,
+        .opt_clks       = ocp2scp_usb_phy_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2bdd4cf17a8f..f62b509ed08d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -547,6 +547,8 @@ static inline void __init realtime_counter_init(void)
                                clksrc_nr, clksrc_src)                   \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
+        if (omap_clk_init)                                              \
+                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
@@ -556,6 +558,8 @@ void __init omap##name##_gptimer_timer_init(void)			\
                                 clksrc_nr, clksrc_src)                  \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
+        if (omap_clk_init)                                              \
+                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \