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-rw-r--r--arch/arm/mach-omap2/prcm.c411
1 files changed, 407 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index ced555a4cd1a..029d376198d4 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -7,6 +7,9 @@
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
10 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
11 * 14 *
12 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
@@ -19,10 +22,13 @@
19#include <linux/io.h> 22#include <linux/io.h>
20#include <linux/delay.h> 23#include <linux/delay.h>
21 24
22#include <mach/common.h> 25#include <plat/common.h>
23#include <mach/prcm.h> 26#include <plat/prcm.h>
27#include <plat/irqs.h>
28#include <plat/control.h>
24 29
25#include "clock.h" 30#include "clock.h"
31#include "cm.h"
26#include "prm.h" 32#include "prm.h"
27#include "prm-regbits-24xx.h" 33#include "prm-regbits-24xx.h"
28 34
@@ -31,6 +37,89 @@ static void __iomem *cm_base;
31 37
32#define MAX_MODULE_ENABLE_WAIT 100000 38#define MAX_MODULE_ENABLE_WAIT 100000
33 39
40struct omap3_prcm_regs {
41 u32 control_padconf_sys_nirq;
42 u32 iva2_cm_clksel1;
43 u32 iva2_cm_clksel2;
44 u32 cm_sysconfig;
45 u32 sgx_cm_clksel;
46 u32 wkup_cm_clksel;
47 u32 dss_cm_clksel;
48 u32 cam_cm_clksel;
49 u32 per_cm_clksel;
50 u32 emu_cm_clksel;
51 u32 emu_cm_clkstctrl;
52 u32 pll_cm_autoidle2;
53 u32 pll_cm_clksel4;
54 u32 pll_cm_clksel5;
55 u32 pll_cm_clken;
56 u32 pll_cm_clken2;
57 u32 cm_polctrl;
58 u32 iva2_cm_fclken;
59 u32 iva2_cm_clken_pll;
60 u32 core_cm_fclken1;
61 u32 core_cm_fclken3;
62 u32 sgx_cm_fclken;
63 u32 wkup_cm_fclken;
64 u32 dss_cm_fclken;
65 u32 cam_cm_fclken;
66 u32 per_cm_fclken;
67 u32 usbhost_cm_fclken;
68 u32 core_cm_iclken1;
69 u32 core_cm_iclken2;
70 u32 core_cm_iclken3;
71 u32 sgx_cm_iclken;
72 u32 wkup_cm_iclken;
73 u32 dss_cm_iclken;
74 u32 cam_cm_iclken;
75 u32 per_cm_iclken;
76 u32 usbhost_cm_iclken;
77 u32 iva2_cm_autiidle2;
78 u32 mpu_cm_autoidle2;
79 u32 pll_cm_autoidle;
80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119};
120
121struct omap3_prcm_regs prcm_context;
122
34u32 omap_prcm_get_reset_sources(void) 123u32 omap_prcm_get_reset_sources(void)
35{ 124{
36 /* XXX This presumably needs modification for 34XX */ 125 /* XXX This presumably needs modification for 34XX */
@@ -46,9 +135,18 @@ void omap_prcm_arch_reset(char mode)
46 135
47 if (cpu_is_omap24xx()) 136 if (cpu_is_omap24xx())
48 prcm_offs = WKUP_MOD; 137 prcm_offs = WKUP_MOD;
49 else if (cpu_is_omap34xx()) 138 else if (cpu_is_omap34xx()) {
139 u32 l;
140
50 prcm_offs = OMAP3430_GR_MOD; 141 prcm_offs = OMAP3430_GR_MOD;
51 else 142 l = ('B' << 24) | ('M' << 16) | mode;
143 /* Reserve the first word in scratchpad for communicating
144 * with the boot ROM. A pointer to a data structure
145 * describing the boot process can be stored there,
146 * cf. OMAP34xx TRM, Initialization / Software Booting
147 * Configuration. */
148 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
149 } else
52 WARN_ON(1); 150 WARN_ON(1);
53 151
54 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); 152 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
@@ -168,3 +266,308 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
168 prm_base = omap2_globals->prm; 266 prm_base = omap2_globals->prm;
169 cm_base = omap2_globals->cm; 267 cm_base = omap2_globals->cm;
170} 268}
269
270#ifdef CONFIG_ARCH_OMAP3
271void omap3_prcm_save_context(void)
272{
273 prcm_context.control_padconf_sys_nirq =
274 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
275 prcm_context.iva2_cm_clksel1 =
276 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
277 prcm_context.iva2_cm_clksel2 =
278 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
279 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
280 prcm_context.sgx_cm_clksel =
281 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
282 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
283 prcm_context.dss_cm_clksel =
284 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
285 prcm_context.cam_cm_clksel =
286 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
287 prcm_context.per_cm_clksel =
288 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
289 prcm_context.emu_cm_clksel =
290 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
291 prcm_context.emu_cm_clkstctrl =
292 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
293 prcm_context.pll_cm_autoidle2 =
294 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
295 prcm_context.pll_cm_clksel4 =
296 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
297 prcm_context.pll_cm_clksel5 =
298 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
299 prcm_context.pll_cm_clken =
300 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
301 prcm_context.pll_cm_clken2 =
302 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
303 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
304 prcm_context.iva2_cm_fclken =
305 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
306 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
307 OMAP3430_CM_CLKEN_PLL);
308 prcm_context.core_cm_fclken1 =
309 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
310 prcm_context.core_cm_fclken3 =
311 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
312 prcm_context.sgx_cm_fclken =
313 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
314 prcm_context.wkup_cm_fclken =
315 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
316 prcm_context.dss_cm_fclken =
317 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
318 prcm_context.cam_cm_fclken =
319 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
320 prcm_context.per_cm_fclken =
321 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
322 prcm_context.usbhost_cm_fclken =
323 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
324 prcm_context.core_cm_iclken1 =
325 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
326 prcm_context.core_cm_iclken2 =
327 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
328 prcm_context.core_cm_iclken3 =
329 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
330 prcm_context.sgx_cm_iclken =
331 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
332 prcm_context.wkup_cm_iclken =
333 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
334 prcm_context.dss_cm_iclken =
335 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
336 prcm_context.cam_cm_iclken =
337 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
338 prcm_context.per_cm_iclken =
339 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
340 prcm_context.usbhost_cm_iclken =
341 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
342 prcm_context.iva2_cm_autiidle2 =
343 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
344 prcm_context.mpu_cm_autoidle2 =
345 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
346 prcm_context.pll_cm_autoidle =
347 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
348 prcm_context.iva2_cm_clkstctrl =
349 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
350 prcm_context.mpu_cm_clkstctrl =
351 cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
352 prcm_context.core_cm_clkstctrl =
353 cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
354 prcm_context.sgx_cm_clkstctrl =
355 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
356 prcm_context.dss_cm_clkstctrl =
357 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
358 prcm_context.cam_cm_clkstctrl =
359 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
360 prcm_context.per_cm_clkstctrl =
361 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
362 prcm_context.neon_cm_clkstctrl =
363 cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
364 prcm_context.usbhost_cm_clkstctrl =
365 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
366 prcm_context.core_cm_autoidle1 =
367 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
368 prcm_context.core_cm_autoidle2 =
369 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
370 prcm_context.core_cm_autoidle3 =
371 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
372 prcm_context.wkup_cm_autoidle =
373 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
374 prcm_context.dss_cm_autoidle =
375 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
376 prcm_context.cam_cm_autoidle =
377 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
378 prcm_context.per_cm_autoidle =
379 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
380 prcm_context.usbhost_cm_autoidle =
381 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
382 prcm_context.sgx_cm_sleepdep =
383 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
384 prcm_context.dss_cm_sleepdep =
385 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
386 prcm_context.cam_cm_sleepdep =
387 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
388 prcm_context.per_cm_sleepdep =
389 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
390 prcm_context.usbhost_cm_sleepdep =
391 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
392 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
393 OMAP3_CM_CLKOUT_CTRL_OFFSET);
394 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
395 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
396 prcm_context.sgx_pm_wkdep =
397 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
398 prcm_context.dss_pm_wkdep =
399 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
400 prcm_context.cam_pm_wkdep =
401 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
402 prcm_context.per_pm_wkdep =
403 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
404 prcm_context.neon_pm_wkdep =
405 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
406 prcm_context.usbhost_pm_wkdep =
407 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
408 prcm_context.core_pm_mpugrpsel1 =
409 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
410 prcm_context.iva2_pm_ivagrpsel1 =
411 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
412 prcm_context.core_pm_mpugrpsel3 =
413 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
414 prcm_context.core_pm_ivagrpsel3 =
415 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
416 prcm_context.wkup_pm_mpugrpsel =
417 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
418 prcm_context.wkup_pm_ivagrpsel =
419 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
420 prcm_context.per_pm_mpugrpsel =
421 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
422 prcm_context.per_pm_ivagrpsel =
423 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
424 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
425 return;
426}
427
428void omap3_prcm_restore_context(void)
429{
430 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
431 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
432 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
433 CM_CLKSEL1);
434 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
435 CM_CLKSEL2);
436 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
437 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
438 CM_CLKSEL);
439 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
440 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
441 CM_CLKSEL);
442 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
443 CM_CLKSEL);
444 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
445 CM_CLKSEL);
446 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
447 CM_CLKSEL1);
448 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
449 CM_CLKSTCTRL);
450 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
451 CM_AUTOIDLE2);
452 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
453 OMAP3430ES2_CM_CLKSEL4);
454 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
455 OMAP3430ES2_CM_CLKSEL5);
456 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
457 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
458 OMAP3430ES2_CM_CLKEN2);
459 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
460 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
461 CM_FCLKEN);
462 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
463 OMAP3430_CM_CLKEN_PLL);
464 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
465 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
466 OMAP3430ES2_CM_FCLKEN3);
467 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
468 CM_FCLKEN);
469 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
470 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
471 CM_FCLKEN);
472 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
473 CM_FCLKEN);
474 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
475 CM_FCLKEN);
476 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
477 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
478 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
479 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
480 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
481 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
482 CM_ICLKEN);
483 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
484 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
485 CM_ICLKEN);
486 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
487 CM_ICLKEN);
488 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
489 CM_ICLKEN);
490 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
491 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
492 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
493 CM_AUTOIDLE2);
494 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
495 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
496 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
497 CM_CLKSTCTRL);
498 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
499 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
500 CM_CLKSTCTRL);
501 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
502 CM_CLKSTCTRL);
503 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
504 CM_CLKSTCTRL);
505 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
506 CM_CLKSTCTRL);
507 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
508 CM_CLKSTCTRL);
509 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
510 CM_CLKSTCTRL);
511 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
512 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
513 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
514 CM_AUTOIDLE1);
515 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
516 CM_AUTOIDLE2);
517 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
518 CM_AUTOIDLE3);
519 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
520 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
521 CM_AUTOIDLE);
522 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
523 CM_AUTOIDLE);
524 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
525 CM_AUTOIDLE);
526 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
527 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
528 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
529 OMAP3430_CM_SLEEPDEP);
530 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
531 OMAP3430_CM_SLEEPDEP);
532 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
533 OMAP3430_CM_SLEEPDEP);
534 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
535 OMAP3430_CM_SLEEPDEP);
536 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
537 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
538 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
539 OMAP3_CM_CLKOUT_CTRL_OFFSET);
540 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
541 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
542 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
543 PM_WKDEP);
544 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
545 PM_WKDEP);
546 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
547 PM_WKDEP);
548 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
549 PM_WKDEP);
550 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
551 PM_WKDEP);
552 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
553 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
554 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
555 OMAP3430_PM_MPUGRPSEL1);
556 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
557 OMAP3430_PM_IVAGRPSEL1);
558 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
559 OMAP3430ES2_PM_MPUGRPSEL3);
560 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
561 OMAP3430ES2_PM_IVAGRPSEL3);
562 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
563 OMAP3430_PM_MPUGRPSEL);
564 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
565 OMAP3430_PM_IVAGRPSEL);
566 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
567 OMAP3430_PM_MPUGRPSEL);
568 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
569 OMAP3430_PM_IVAGRPSEL);
570 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
571 return;
572}
573#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 01:33:57 -0400