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-rw-r--r--arch/arm/mach-omap2/pm34xx.c259
1 files changed, 137 insertions, 122 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ea0000bc5358..2e967716cc3f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -58,6 +58,7 @@
58u32 enable_off_mode; 58u32 enable_off_mode;
59u32 sleep_while_idle; 59u32 sleep_while_idle;
60u32 wakeup_timer_seconds; 60u32 wakeup_timer_seconds;
61u32 wakeup_timer_milliseconds;
61 62
62struct power_state { 63struct power_state {
63 struct powerdomain *pwrdm; 64 struct powerdomain *pwrdm;
@@ -93,19 +94,20 @@ static void omap3_enable_io_chain(void)
93 int timeout = 0; 94 int timeout = 0;
94 95
95 if (omap_rev() >= OMAP3430_REV_ES3_1) { 96 if (omap_rev() >= OMAP3430_REV_ES3_1) {
96 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 97 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
98 PM_WKEN);
97 /* Do a readback to assure write has been done */ 99 /* Do a readback to assure write has been done */
98 prm_read_mod_reg(WKUP_MOD, PM_WKEN); 100 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
99 101
100 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & 102 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
101 OMAP3430_ST_IO_CHAIN)) { 103 OMAP3430_ST_IO_CHAIN_MASK)) {
102 timeout++; 104 timeout++;
103 if (timeout > 1000) { 105 if (timeout > 1000) {
104 printk(KERN_ERR "Wake up daisy chain " 106 printk(KERN_ERR "Wake up daisy chain "
105 "activation failed.\n"); 107 "activation failed.\n");
106 return; 108 return;
107 } 109 }
108 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, 110 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
109 WKUP_MOD, PM_WKST); 111 WKUP_MOD, PM_WKST);
110 } 112 }
111 } 113 }
@@ -114,7 +116,8 @@ static void omap3_enable_io_chain(void)
114static void omap3_disable_io_chain(void) 116static void omap3_disable_io_chain(void)
115{ 117{
116 if (omap_rev() >= OMAP3430_REV_ES3_1) 118 if (omap_rev() >= OMAP3430_REV_ES3_1)
117 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 119 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
120 PM_WKEN);
118} 121}
119 122
120static void omap3_core_save_context(void) 123static void omap3_core_save_context(void)
@@ -267,14 +270,18 @@ static int _prcm_int_handle_wakeup(void)
267 */ 270 */
268static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 271static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
269{ 272{
270 u32 irqstatus_mpu; 273 u32 irqenable_mpu, irqstatus_mpu;
271 int c = 0; 274 int c = 0;
272 275
273 do { 276 irqenable_mpu = prm_read_mod_reg(OCP_MOD,
274 irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 277 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
275 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 278 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
279 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
280 irqstatus_mpu &= irqenable_mpu;
276 281
277 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 282 do {
283 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
284 OMAP3430_IO_ST_MASK)) {
278 c = _prcm_int_handle_wakeup(); 285 c = _prcm_int_handle_wakeup();
279 286
280 /* 287 /*
@@ -292,7 +299,11 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
292 prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 299 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
293 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 300 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
294 301
295 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 302 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
303 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
304 irqstatus_mpu &= irqenable_mpu;
305
306 } while (irqstatus_mpu);
296 307
297 return IRQ_HANDLED; 308 return IRQ_HANDLED;
298} 309}
@@ -371,12 +382,19 @@ void omap_sram_idle(void)
371 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 382 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
372 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 383 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
373 384
374 /* PER */ 385 /* Enable IO-PAD and IO-CHAIN wakeups */
375 per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 386 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
376 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 387 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
388 if (per_next_state < PWRDM_POWER_ON ||
389 core_next_state < PWRDM_POWER_ON) {
390 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
391 omap3_enable_io_chain();
392 }
393
394 /* PER */
377 if (per_next_state < PWRDM_POWER_ON) { 395 if (per_next_state < PWRDM_POWER_ON) {
378 omap_uart_prepare_idle(2); 396 omap_uart_prepare_idle(2);
379 omap2_gpio_prepare_for_retention(); 397 omap2_gpio_prepare_for_idle(per_next_state);
380 if (per_next_state == PWRDM_POWER_OFF) { 398 if (per_next_state == PWRDM_POWER_OFF) {
381 if (core_next_state == PWRDM_POWER_ON) { 399 if (core_next_state == PWRDM_POWER_ON) {
382 per_next_state = PWRDM_POWER_RET; 400 per_next_state = PWRDM_POWER_RET;
@@ -398,10 +416,8 @@ void omap_sram_idle(void)
398 omap3_core_save_context(); 416 omap3_core_save_context();
399 omap3_prcm_save_context(); 417 omap3_prcm_save_context();
400 } 418 }
401 /* Enable IO-PAD and IO-CHAIN wakeups */
402 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
403 omap3_enable_io_chain();
404 } 419 }
420
405 omap3_intc_prepare_idle(); 421 omap3_intc_prepare_idle();
406 422
407 /* 423 /*
@@ -445,7 +461,7 @@ void omap_sram_idle(void)
445 omap_uart_resume_idle(0); 461 omap_uart_resume_idle(0);
446 omap_uart_resume_idle(1); 462 omap_uart_resume_idle(1);
447 if (core_next_state == PWRDM_POWER_OFF) 463 if (core_next_state == PWRDM_POWER_OFF)
448 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, 464 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
449 OMAP3430_GR_MOD, 465 OMAP3430_GR_MOD,
450 OMAP3_PRM_VOLTCTRL_OFFSET); 466 OMAP3_PRM_VOLTCTRL_OFFSET);
451 } 467 }
@@ -454,9 +470,9 @@ void omap_sram_idle(void)
454 /* PER */ 470 /* PER */
455 if (per_next_state < PWRDM_POWER_ON) { 471 if (per_next_state < PWRDM_POWER_ON) {
456 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 472 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
473 omap2_gpio_resume_after_idle();
457 if (per_prev_state == PWRDM_POWER_OFF) 474 if (per_prev_state == PWRDM_POWER_OFF)
458 omap3_per_restore_context(); 475 omap3_per_restore_context();
459 omap2_gpio_resume_after_retention();
460 omap_uart_resume_idle(2); 476 omap_uart_resume_idle(2);
461 if (per_state_modified) 477 if (per_state_modified)
462 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); 478 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
@@ -464,7 +480,7 @@ void omap_sram_idle(void)
464 480
465 /* Disable IO-PAD and IO-CHAIN wakeup */ 481 /* Disable IO-PAD and IO-CHAIN wakeup */
466 if (core_next_state < PWRDM_POWER_ON) { 482 if (core_next_state < PWRDM_POWER_ON) {
467 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 483 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
468 omap3_disable_io_chain(); 484 omap3_disable_io_chain();
469 } 485 }
470 486
@@ -548,20 +564,21 @@ out:
548#ifdef CONFIG_SUSPEND 564#ifdef CONFIG_SUSPEND
549static suspend_state_t suspend_state; 565static suspend_state_t suspend_state;
550 566
551static void omap2_pm_wakeup_on_timer(u32 seconds) 567static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
552{ 568{
553 u32 tick_rate, cycles; 569 u32 tick_rate, cycles;
554 570
555 if (!seconds) 571 if (!seconds && !milliseconds)
556 return; 572 return;
557 573
558 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); 574 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
559 cycles = tick_rate * seconds; 575 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
560 omap_dm_timer_stop(gptimer_wakeup); 576 omap_dm_timer_stop(gptimer_wakeup);
561 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); 577 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
562 578
563 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", 579 pr_info("PM: Resume timer in %u.%03u secs"
564 seconds, cycles, tick_rate); 580 " (%d ticks at %d ticks/sec.)\n",
581 seconds, milliseconds, cycles, tick_rate);
565} 582}
566 583
567static int omap3_pm_prepare(void) 584static int omap3_pm_prepare(void)
@@ -575,8 +592,9 @@ static int omap3_pm_suspend(void)
575 struct power_state *pwrst; 592 struct power_state *pwrst;
576 int state, ret = 0; 593 int state, ret = 0;
577 594
578 if (wakeup_timer_seconds) 595 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
579 omap2_pm_wakeup_on_timer(wakeup_timer_seconds); 596 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
597 wakeup_timer_milliseconds);
580 598
581 /* Read current next_pwrsts */ 599 /* Read current next_pwrsts */
582 list_for_each_entry(pwrst, &pwrst_list, node) 600 list_for_each_entry(pwrst, &pwrst_list, node)
@@ -683,9 +701,9 @@ static void __init omap3_iva_idle(void)
683 return; 701 return;
684 702
685 /* Reset IVA2 */ 703 /* Reset IVA2 */
686 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 704 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
687 OMAP3430_RST2_IVA2 | 705 OMAP3430_RST2_IVA2_MASK |
688 OMAP3430_RST3_IVA2, 706 OMAP3430_RST3_IVA2_MASK,
689 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 707 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
690 708
691 /* Enable IVA2 clock */ 709 /* Enable IVA2 clock */
@@ -703,9 +721,9 @@ static void __init omap3_iva_idle(void)
703 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 721 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
704 722
705 /* Reset IVA2 */ 723 /* Reset IVA2 */
706 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 724 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
707 OMAP3430_RST2_IVA2 | 725 OMAP3430_RST2_IVA2_MASK |
708 OMAP3430_RST3_IVA2, 726 OMAP3430_RST3_IVA2_MASK,
709 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 727 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
710} 728}
711 729
@@ -727,8 +745,8 @@ static void __init omap3_d2d_idle(void)
727 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 745 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
728 746
729 /* reset modem */ 747 /* reset modem */
730 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 748 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
731 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 749 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
732 CORE_MOD, OMAP2_RM_RSTCTRL); 750 CORE_MOD, OMAP2_RM_RSTCTRL);
733 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 751 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
734} 752}
@@ -754,102 +772,102 @@ static void __init prcm_setup_regs(void)
754 * Note that in the long run this should be done by clockfw 772 * Note that in the long run this should be done by clockfw
755 */ 773 */
756 cm_write_mod_reg( 774 cm_write_mod_reg(
757 OMAP3430_AUTO_MODEM | 775 OMAP3430_AUTO_MODEM_MASK |
758 OMAP3430ES2_AUTO_MMC3 | 776 OMAP3430ES2_AUTO_MMC3_MASK |
759 OMAP3430ES2_AUTO_ICR | 777 OMAP3430ES2_AUTO_ICR_MASK |
760 OMAP3430_AUTO_AES2 | 778 OMAP3430_AUTO_AES2_MASK |
761 OMAP3430_AUTO_SHA12 | 779 OMAP3430_AUTO_SHA12_MASK |
762 OMAP3430_AUTO_DES2 | 780 OMAP3430_AUTO_DES2_MASK |
763 OMAP3430_AUTO_MMC2 | 781 OMAP3430_AUTO_MMC2_MASK |
764 OMAP3430_AUTO_MMC1 | 782 OMAP3430_AUTO_MMC1_MASK |
765 OMAP3430_AUTO_MSPRO | 783 OMAP3430_AUTO_MSPRO_MASK |
766 OMAP3430_AUTO_HDQ | 784 OMAP3430_AUTO_HDQ_MASK |
767 OMAP3430_AUTO_MCSPI4 | 785 OMAP3430_AUTO_MCSPI4_MASK |
768 OMAP3430_AUTO_MCSPI3 | 786 OMAP3430_AUTO_MCSPI3_MASK |
769 OMAP3430_AUTO_MCSPI2 | 787 OMAP3430_AUTO_MCSPI2_MASK |
770 OMAP3430_AUTO_MCSPI1 | 788 OMAP3430_AUTO_MCSPI1_MASK |
771 OMAP3430_AUTO_I2C3 | 789 OMAP3430_AUTO_I2C3_MASK |
772 OMAP3430_AUTO_I2C2 | 790 OMAP3430_AUTO_I2C2_MASK |
773 OMAP3430_AUTO_I2C1 | 791 OMAP3430_AUTO_I2C1_MASK |
774 OMAP3430_AUTO_UART2 | 792 OMAP3430_AUTO_UART2_MASK |
775 OMAP3430_AUTO_UART1 | 793 OMAP3430_AUTO_UART1_MASK |
776 OMAP3430_AUTO_GPT11 | 794 OMAP3430_AUTO_GPT11_MASK |
777 OMAP3430_AUTO_GPT10 | 795 OMAP3430_AUTO_GPT10_MASK |
778 OMAP3430_AUTO_MCBSP5 | 796 OMAP3430_AUTO_MCBSP5_MASK |
779 OMAP3430_AUTO_MCBSP1 | 797 OMAP3430_AUTO_MCBSP1_MASK |
780 OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 798 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
781 OMAP3430_AUTO_MAILBOXES | 799 OMAP3430_AUTO_MAILBOXES_MASK |
782 OMAP3430_AUTO_OMAPCTRL | 800 OMAP3430_AUTO_OMAPCTRL_MASK |
783 OMAP3430ES1_AUTO_FSHOSTUSB | 801 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
784 OMAP3430_AUTO_HSOTGUSB | 802 OMAP3430_AUTO_HSOTGUSB_MASK |
785 OMAP3430_AUTO_SAD2D | 803 OMAP3430_AUTO_SAD2D_MASK |
786 OMAP3430_AUTO_SSI, 804 OMAP3430_AUTO_SSI_MASK,
787 CORE_MOD, CM_AUTOIDLE1); 805 CORE_MOD, CM_AUTOIDLE1);
788 806
789 cm_write_mod_reg( 807 cm_write_mod_reg(
790 OMAP3430_AUTO_PKA | 808 OMAP3430_AUTO_PKA_MASK |
791 OMAP3430_AUTO_AES1 | 809 OMAP3430_AUTO_AES1_MASK |
792 OMAP3430_AUTO_RNG | 810 OMAP3430_AUTO_RNG_MASK |
793 OMAP3430_AUTO_SHA11 | 811 OMAP3430_AUTO_SHA11_MASK |
794 OMAP3430_AUTO_DES1, 812 OMAP3430_AUTO_DES1_MASK,
795 CORE_MOD, CM_AUTOIDLE2); 813 CORE_MOD, CM_AUTOIDLE2);
796 814
797 if (omap_rev() > OMAP3430_REV_ES1_0) { 815 if (omap_rev() > OMAP3430_REV_ES1_0) {
798 cm_write_mod_reg( 816 cm_write_mod_reg(
799 OMAP3430_AUTO_MAD2D | 817 OMAP3430_AUTO_MAD2D_MASK |
800 OMAP3430ES2_AUTO_USBTLL, 818 OMAP3430ES2_AUTO_USBTLL_MASK,
801 CORE_MOD, CM_AUTOIDLE3); 819 CORE_MOD, CM_AUTOIDLE3);
802 } 820 }
803 821
804 cm_write_mod_reg( 822 cm_write_mod_reg(
805 OMAP3430_AUTO_WDT2 | 823 OMAP3430_AUTO_WDT2_MASK |
806 OMAP3430_AUTO_WDT1 | 824 OMAP3430_AUTO_WDT1_MASK |
807 OMAP3430_AUTO_GPIO1 | 825 OMAP3430_AUTO_GPIO1_MASK |
808 OMAP3430_AUTO_32KSYNC | 826 OMAP3430_AUTO_32KSYNC_MASK |
809 OMAP3430_AUTO_GPT12 | 827 OMAP3430_AUTO_GPT12_MASK |
810 OMAP3430_AUTO_GPT1 , 828 OMAP3430_AUTO_GPT1_MASK,
811 WKUP_MOD, CM_AUTOIDLE); 829 WKUP_MOD, CM_AUTOIDLE);
812 830
813 cm_write_mod_reg( 831 cm_write_mod_reg(
814 OMAP3430_AUTO_DSS, 832 OMAP3430_AUTO_DSS_MASK,
815 OMAP3430_DSS_MOD, 833 OMAP3430_DSS_MOD,
816 CM_AUTOIDLE); 834 CM_AUTOIDLE);
817 835
818 cm_write_mod_reg( 836 cm_write_mod_reg(
819 OMAP3430_AUTO_CAM, 837 OMAP3430_AUTO_CAM_MASK,
820 OMAP3430_CAM_MOD, 838 OMAP3430_CAM_MOD,
821 CM_AUTOIDLE); 839 CM_AUTOIDLE);
822 840
823 cm_write_mod_reg( 841 cm_write_mod_reg(
824 OMAP3430_AUTO_GPIO6 | 842 OMAP3430_AUTO_GPIO6_MASK |
825 OMAP3430_AUTO_GPIO5 | 843 OMAP3430_AUTO_GPIO5_MASK |
826 OMAP3430_AUTO_GPIO4 | 844 OMAP3430_AUTO_GPIO4_MASK |
827 OMAP3430_AUTO_GPIO3 | 845 OMAP3430_AUTO_GPIO3_MASK |
828 OMAP3430_AUTO_GPIO2 | 846 OMAP3430_AUTO_GPIO2_MASK |
829 OMAP3430_AUTO_WDT3 | 847 OMAP3430_AUTO_WDT3_MASK |
830 OMAP3430_AUTO_UART3 | 848 OMAP3430_AUTO_UART3_MASK |
831 OMAP3430_AUTO_GPT9 | 849 OMAP3430_AUTO_GPT9_MASK |
832 OMAP3430_AUTO_GPT8 | 850 OMAP3430_AUTO_GPT8_MASK |
833 OMAP3430_AUTO_GPT7 | 851 OMAP3430_AUTO_GPT7_MASK |
834 OMAP3430_AUTO_GPT6 | 852 OMAP3430_AUTO_GPT6_MASK |
835 OMAP3430_AUTO_GPT5 | 853 OMAP3430_AUTO_GPT5_MASK |
836 OMAP3430_AUTO_GPT4 | 854 OMAP3430_AUTO_GPT4_MASK |
837 OMAP3430_AUTO_GPT3 | 855 OMAP3430_AUTO_GPT3_MASK |
838 OMAP3430_AUTO_GPT2 | 856 OMAP3430_AUTO_GPT2_MASK |
839 OMAP3430_AUTO_MCBSP4 | 857 OMAP3430_AUTO_MCBSP4_MASK |
840 OMAP3430_AUTO_MCBSP3 | 858 OMAP3430_AUTO_MCBSP3_MASK |
841 OMAP3430_AUTO_MCBSP2, 859 OMAP3430_AUTO_MCBSP2_MASK,
842 OMAP3430_PER_MOD, 860 OMAP3430_PER_MOD,
843 CM_AUTOIDLE); 861 CM_AUTOIDLE);
844 862
845 if (omap_rev() > OMAP3430_REV_ES1_0) { 863 if (omap_rev() > OMAP3430_REV_ES1_0) {
846 cm_write_mod_reg( 864 cm_write_mod_reg(
847 OMAP3430ES2_AUTO_USBHOST, 865 OMAP3430ES2_AUTO_USBHOST_MASK,
848 OMAP3430ES2_USBHOST_MOD, 866 OMAP3430ES2_USBHOST_MOD,
849 CM_AUTOIDLE); 867 CM_AUTOIDLE);
850 } 868 }
851 869
852 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); 870 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
853 871
854 /* 872 /*
855 * Set all plls to autoidle. This is needed until autoidle is 873 * Set all plls to autoidle. This is needed until autoidle is
@@ -879,35 +897,40 @@ static void __init prcm_setup_regs(void)
879 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 897 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
880 898
881 /* setup wakup source */ 899 /* setup wakup source */
882 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 900 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
883 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 901 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
884 WKUP_MOD, PM_WKEN); 902 WKUP_MOD, PM_WKEN);
885 /* No need to write EN_IO, that is always enabled */ 903 /* No need to write EN_IO, that is always enabled */
886 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 904 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
887 OMAP3430_EN_GPT12, 905 OMAP3430_GRPSEL_GPT1_MASK |
906 OMAP3430_GRPSEL_GPT12_MASK,
888 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 907 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
889 /* For some reason IO doesn't generate wakeup event even if 908 /* For some reason IO doesn't generate wakeup event even if
890 * it is selected to mpu wakeup goup */ 909 * it is selected to mpu wakeup goup */
891 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 910 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
892 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 911 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
893 912
894 /* Enable PM_WKEN to support DSS LPR */ 913 /* Enable PM_WKEN to support DSS LPR */
895 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, 914 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
896 OMAP3430_DSS_MOD, PM_WKEN); 915 OMAP3430_DSS_MOD, PM_WKEN);
897 916
898 /* Enable wakeups in PER */ 917 /* Enable wakeups in PER */
899 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 918 prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
900 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 919 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
901 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | 920 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
902 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 921 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
903 OMAP3430_EN_MCBSP4, 922 OMAP3430_EN_MCBSP4_MASK,
904 OMAP3430_PER_MOD, PM_WKEN); 923 OMAP3430_PER_MOD, PM_WKEN);
905 /* and allow them to wake up MPU */ 924 /* and allow them to wake up MPU */
906 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 925 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
907 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 926 OMAP3430_GRPSEL_GPIO3_MASK |
908 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | 927 OMAP3430_GRPSEL_GPIO4_MASK |
909 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 928 OMAP3430_GRPSEL_GPIO5_MASK |
910 OMAP3430_EN_MCBSP4, 929 OMAP3430_GRPSEL_GPIO6_MASK |
930 OMAP3430_GRPSEL_UART3_MASK |
931 OMAP3430_GRPSEL_MCBSP2_MASK |
932 OMAP3430_GRPSEL_MCBSP3_MASK |
933 OMAP3430_GRPSEL_MCBSP4_MASK,
911 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 934 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
912 935
913 /* Don't attach IVA interrupts */ 936 /* Don't attach IVA interrupts */
@@ -1080,14 +1103,6 @@ static int __init omap3_pm_init(void)
1080 omap3_idle_init(); 1103 omap3_idle_init();
1081 1104
1082 clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 1105 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1083 /*
1084 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1085 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1086 * waking up PER with every CORE wakeup - see
1087 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1088 */
1089 clkdm_add_wkdep(per_clkdm, core_clkdm);
1090
1091 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 1106 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1092 omap3_secure_ram_storage = 1107 omap3_secure_ram_storage =
1093 kmalloc(0x803F, GFP_KERNEL); 1108 kmalloc(0x803F, GFP_KERNEL);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 13:52:09 -0400