diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_54xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index e297d6231c3a..892317294fdc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c | |||
@@ -1122,6 +1122,71 @@ static struct omap_hwmod omap54xx_mmc5_hwmod = { | |||
1122 | }; | 1122 | }; |
1123 | 1123 | ||
1124 | /* | 1124 | /* |
1125 | * 'mmu' class | ||
1126 | * The memory management unit performs virtual to physical address translation | ||
1127 | * for its requestors. | ||
1128 | */ | ||
1129 | |||
1130 | static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = { | ||
1131 | .rev_offs = 0x0000, | ||
1132 | .sysc_offs = 0x0010, | ||
1133 | .syss_offs = 0x0014, | ||
1134 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
1135 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
1136 | SYSS_HAS_RESET_STATUS), | ||
1137 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1138 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1139 | }; | ||
1140 | |||
1141 | static struct omap_hwmod_class omap54xx_mmu_hwmod_class = { | ||
1142 | .name = "mmu", | ||
1143 | .sysc = &omap54xx_mmu_sysc, | ||
1144 | }; | ||
1145 | |||
1146 | static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = { | ||
1147 | { .name = "mmu_cache", .rst_shift = 1 }, | ||
1148 | }; | ||
1149 | |||
1150 | static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { | ||
1151 | .name = "mmu_dsp", | ||
1152 | .class = &omap54xx_mmu_hwmod_class, | ||
1153 | .clkdm_name = "dsp_clkdm", | ||
1154 | .rst_lines = omap54xx_mmu_dsp_resets, | ||
1155 | .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets), | ||
1156 | .main_clk = "dpll_iva_h11x2_ck", | ||
1157 | .prcm = { | ||
1158 | .omap4 = { | ||
1159 | .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, | ||
1160 | .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, | ||
1161 | .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, | ||
1162 | .modulemode = MODULEMODE_HWCTRL, | ||
1163 | }, | ||
1164 | }, | ||
1165 | }; | ||
1166 | |||
1167 | /* mmu ipu */ | ||
1168 | static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = { | ||
1169 | { .name = "mmu_cache", .rst_shift = 2 }, | ||
1170 | }; | ||
1171 | |||
1172 | static struct omap_hwmod omap54xx_mmu_ipu_hwmod = { | ||
1173 | .name = "mmu_ipu", | ||
1174 | .class = &omap54xx_mmu_hwmod_class, | ||
1175 | .clkdm_name = "ipu_clkdm", | ||
1176 | .rst_lines = omap54xx_mmu_ipu_resets, | ||
1177 | .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets), | ||
1178 | .main_clk = "dpll_core_h22x2_ck", | ||
1179 | .prcm = { | ||
1180 | .omap4 = { | ||
1181 | .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, | ||
1182 | .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, | ||
1183 | .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, | ||
1184 | .modulemode = MODULEMODE_HWCTRL, | ||
1185 | }, | ||
1186 | }, | ||
1187 | }; | ||
1188 | |||
1189 | /* | ||
1125 | * 'mpu' class | 1190 | * 'mpu' class |
1126 | * mpu sub-system | 1191 | * mpu sub-system |
1127 | */ | 1192 | */ |
@@ -1763,6 +1828,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { | |||
1763 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1828 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1764 | }; | 1829 | }; |
1765 | 1830 | ||
1831 | /* l4_cfg -> mmu_dsp */ | ||
1832 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { | ||
1833 | .master = &omap54xx_l4_cfg_hwmod, | ||
1834 | .slave = &omap54xx_mmu_dsp_hwmod, | ||
1835 | .clk = "l4_root_clk_div", | ||
1836 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1837 | }; | ||
1838 | |||
1766 | /* mpu -> l3_main_1 */ | 1839 | /* mpu -> l3_main_1 */ |
1767 | static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { | 1840 | static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { |
1768 | .master = &omap54xx_mpu_hwmod, | 1841 | .master = &omap54xx_mpu_hwmod, |
@@ -1787,6 +1860,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { | |||
1787 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1860 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1788 | }; | 1861 | }; |
1789 | 1862 | ||
1863 | /* l3_main_2 -> mmu_ipu */ | ||
1864 | static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { | ||
1865 | .master = &omap54xx_l3_main_2_hwmod, | ||
1866 | .slave = &omap54xx_mmu_ipu_hwmod, | ||
1867 | .clk = "l3_iclk_div", | ||
1868 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1869 | }; | ||
1870 | |||
1790 | /* l3_main_1 -> l3_main_3 */ | 1871 | /* l3_main_1 -> l3_main_3 */ |
1791 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { | 1872 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { |
1792 | .master = &omap54xx_l3_main_1_hwmod, | 1873 | .master = &omap54xx_l3_main_1_hwmod, |
@@ -2345,6 +2426,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { | |||
2345 | &omap54xx_l4_wkup__counter_32k, | 2426 | &omap54xx_l4_wkup__counter_32k, |
2346 | &omap54xx_l4_cfg__dma_system, | 2427 | &omap54xx_l4_cfg__dma_system, |
2347 | &omap54xx_l4_abe__dmic, | 2428 | &omap54xx_l4_abe__dmic, |
2429 | &omap54xx_l4_cfg__mmu_dsp, | ||
2348 | &omap54xx_mpu__emif1, | 2430 | &omap54xx_mpu__emif1, |
2349 | &omap54xx_mpu__emif2, | 2431 | &omap54xx_mpu__emif2, |
2350 | &omap54xx_l4_wkup__gpio1, | 2432 | &omap54xx_l4_wkup__gpio1, |
@@ -2360,6 +2442,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { | |||
2360 | &omap54xx_l4_per__i2c3, | 2442 | &omap54xx_l4_per__i2c3, |
2361 | &omap54xx_l4_per__i2c4, | 2443 | &omap54xx_l4_per__i2c4, |
2362 | &omap54xx_l4_per__i2c5, | 2444 | &omap54xx_l4_per__i2c5, |
2445 | &omap54xx_l3_main_2__mmu_ipu, | ||
2363 | &omap54xx_l4_wkup__kbd, | 2446 | &omap54xx_l4_wkup__kbd, |
2364 | &omap54xx_l4_cfg__mailbox, | 2447 | &omap54xx_l4_cfg__mailbox, |
2365 | &omap54xx_l4_abe__mcbsp1, | 2448 | &omap54xx_l4_abe__mcbsp1, |