1 files changed, 251 insertions, 2 deletions

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58ba5e3..5c9cb255a052 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,6 +17,7 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -82,6 +83,10 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
+static struct omap_hwmod omap3xxx_uart1_hwmod;
+static struct omap_hwmod omap3xxx_uart2_hwmod;
+static struct omap_hwmod omap3xxx_uart3_hwmod;
+static struct omap_hwmod omap3xxx_uart4_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
@@ -90,6 +95,78 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART1_BASE,
+                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap3xxx_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART2_BASE,
+                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap3xxx_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART3_BASE,
+                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap3xxx_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART4 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_BASE,
+                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = omap3xxx_uart4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
         &omap3xxx_l3_main__l4_core,
@@ -98,6 +175,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
         &omap3xxx_l4_core__l4_wkup,
+        &omap3_l4_core__uart1,
+        &omap3_l4_core__uart2,
 };
 
 /* L4 CORE */
@@ -119,6 +198,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 
 /* Master interfaces on the L4_PER interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
+        &omap3_l4_per__uart3,
+        &omap3_l4_per__uart4,
 };
 
 /* L4 PER */
@@ -197,6 +278,172 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+/* UART common */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+        &omap3_l4_core__uart1,
+};
+
+static struct omap_hwmod omap3xxx_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+        &omap3_l4_core__uart2,
+};
+
+static struct omap_hwmod omap3xxx_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+        &omap3_l4_per__uart3,
+};
+
+static struct omap_hwmod omap3xxx_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART4 */
+
+static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+        { .irq = INT_36XX_UART4_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
+        { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+        &omap3_l4_per__uart4,
+};
+
+static struct omap_hwmod omap3xxx_uart4_hwmod = {
+        .name           = "uart4",
+        .mpu_irqs       = uart4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
+        .sdma_reqs      = uart4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
+        .main_clk       = "uart4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3630_EN_UART4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
@@ -204,6 +451,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l4_wkup_hwmod,
         &omap3xxx_mpu_hwmod,
         &omap3xxx_iva_hwmod,
+        &omap3xxx_uart1_hwmod,
+        &omap3xxx_uart2_hwmod,
+        &omap3xxx_uart3_hwmod,
+        &omap3xxx_uart4_hwmod,
         NULL,
 };
 
@@ -211,5 +462,3 @@ int __init omap3xxx_hwmod_init(void)
 {
         return omap_hwmod_init(omap3xxx_hwmods);
 }
-
-