1 files changed, 546 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index b46a54ce1a41..4aa74d78289c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,8 +18,10 @@
 #include <plat/serial.h>
 #include <plat/i2c.h>
 #include <plat/gpio.h>
+#include <plat/mcbsp.h>
 #include <plat/mcspi.h>
 #include <plat/dmtimer.h>
+#include <plat/mmc.h>
 #include <plat/l3_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
@@ -52,9 +54,16 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
 static struct omap_hwmod omap2430_gpio4_hwmod;
 static struct omap_hwmod omap2430_gpio5_hwmod;
 static struct omap_hwmod omap2430_dma_system_hwmod;
+static struct omap_hwmod omap2430_mcbsp1_hwmod;
+static struct omap_hwmod omap2430_mcbsp2_hwmod;
+static struct omap_hwmod omap2430_mcbsp3_hwmod;
+static struct omap_hwmod omap2430_mcbsp4_hwmod;
+static struct omap_hwmod omap2430_mcbsp5_hwmod;
 static struct omap_hwmod omap2430_mcspi1_hwmod;
 static struct omap_hwmod omap2430_mcspi2_hwmod;
 static struct omap_hwmod omap2430_mcspi3_hwmod;
+static struct omap_hwmod omap2430_mmc1_hwmod;
+static struct omap_hwmod omap2430_mmc2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -251,6 +260,42 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
         &omap2430_l4_core__usbhsotg,
 };
 
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mmc1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b41ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mmc2_hwmod,
+        .addr           = omap2430_mmc2_addr_space,
+        .clk            = "mmchs2_ick",
+        .addr_cnt       = ARRAY_SIZE(omap2430_mmc2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
         &omap2430_l3_main__l4_core,
@@ -259,6 +304,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
         &omap2430_l4_core__l4_wkup,
+        &omap2430_l4_core__mmc1,
+        &omap2430_l4_core__mmc2,
 };
 
 /* L4 CORE */
@@ -1914,6 +1961,75 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 };
 
 /*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+        .name = "mailbox",
+        .sysc = &omap2430_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2430_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+        { .irq = 26 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mailbox_hwmod,
+        .addr           = omap2430_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
+        &omap2430_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2430_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap2430_mailbox_hwmod_class,
+        .mpu_irqs       = omap2430_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
+        .main_clk       = "mailboxes_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
  * 'mcspi' class
  * multichannel serial port interface (mcspi) / master/slave synchronous serial
  * bus
@@ -2125,7 +2241,425 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
+        .rev_offs       = 0x007C,
+        .sysc_offs      = 0x008C,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
+        .name = "mcbsp",
+        .sysc = &omap2430_mcbsp_sysc,
+        .rev  = MCBSP_CONFIG_TYPE2,
+};
 
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
+        { .name = "tx",         .irq = 59 },
+        { .name = "rx",         .irq = 60 },
+        { .name = "ovr",        .irq = 61 },
+        { .name = "common",     .irq = 64 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap2430_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
+        &omap2430_l4_core__mcbsp1,
+};
+
+static struct omap_hwmod omap2430_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
+        .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
+        { .name = "tx",         .irq = 62 },
+        { .name = "rx",         .irq = 63 },
+        { .name = "common",     .irq = 16 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480760ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap2430_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
+        &omap2430_l4_core__mcbsp2,
+};
+
+static struct omap_hwmod omap2430_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
+        .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
+        { .name = "tx",         .irq = 89 },
+        { .name = "rx",         .irq = 90 },
+        { .name = "common",     .irq = 17 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
+        { .name = "rx", .dma_req = 18 },
+        { .name = "tx", .dma_req = 17 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808C000,
+                .pa_end         = 0x4808C0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap2430_mcbsp3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp3 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
+        &omap2430_l4_core__mcbsp3,
+};
+
+static struct omap_hwmod omap2430_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
+        .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp4 */
+static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
+        { .name = "tx",         .irq = 54 },
+        { .name = "rx",         .irq = 55 },
+        { .name = "common",     .irq = 18 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
+        { .name = "rx", .dma_req = 20 },
+        { .name = "tx", .dma_req = 19 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808E000,
+                .pa_end         = 0x4808E0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap2430_mcbsp4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp4 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
+        &omap2430_l4_core__mcbsp4,
+};
+
+static struct omap_hwmod omap2430_mcbsp4_hwmod = {
+        .name           = "mcbsp4",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
+        .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
+        .main_clk       = "mcbsp4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp5 */
+static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
+        { .name = "tx",         .irq = 81 },
+        { .name = "rx",         .irq = 82 },
+        { .name = "common",     .irq = 19 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
+        { .name = "rx", .dma_req = 22 },
+        { .name = "tx", .dma_req = 21 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap2430_mcbsp5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp5 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
+        &omap2430_l4_core__mcbsp5,
+};
+
+static struct omap_hwmod omap2430_mcbsp5_hwmod = {
+        .name           = "mcbsp5",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
+        .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
+        .main_clk       = "mcbsp5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* MMC/SD/SDIO common */
+
+static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mmc_class = {
+        .name = "mmc",
+        .sysc = &omap2430_mmc_sysc,
+};
+
+/* MMC/SD/SDIO1 */
+
+static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
+        { .irq = 83 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
+        { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
+};
+
+static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
+        { .role = "dbck", .clk = "mmchsdb1_fck" },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
+        &omap2430_l4_core__mmc1,
+};
+
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap2430_mmc1_hwmod = {
+        .name           = "mmc1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2430_mmc1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
+        .sdma_reqs      = omap2430_mmc1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
+        .opt_clks       = omap2430_mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
+        .main_clk       = "mmchs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc1_dev_attr,
+        .slaves         = omap2430_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
+        .class          = &omap2430_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* MMC/SD/SDIO2 */
+
+static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
+        { .irq = 86 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
+        { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
+};
+
+static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
+        { .role = "dbck", .clk = "mmchsdb2_fck" },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
+        &omap2430_l4_core__mmc2,
+};
+
+static struct omap_hwmod omap2430_mmc2_hwmod = {
+        .name           = "mmc2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2430_mmc2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
+        .sdma_reqs      = omap2430_mmc2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
+        .opt_clks       = omap2430_mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
+        .main_clk       = "mmchs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
+        .class          = &omap2430_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
 
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l3_main_hwmod,
@@ -2159,6 +2693,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         /* i2c class */
         &omap2430_i2c1_hwmod,
         &omap2430_i2c2_hwmod,
+        &omap2430_mmc1_hwmod,
+        &omap2430_mmc2_hwmod,
 
         /* gpio class */
         &omap2430_gpio1_hwmod,
@@ -2170,6 +2706,16 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         /* dma_system class*/
         &omap2430_dma_system_hwmod,
 
+        /* mcbsp class */
+        &omap2430_mcbsp1_hwmod,
+        &omap2430_mcbsp2_hwmod,
+        &omap2430_mcbsp3_hwmod,
+        &omap2430_mcbsp4_hwmod,
+        &omap2430_mcbsp5_hwmod,
+
+        /* mailbox class */
+        &omap2430_mailbox_hwmod,
+
         /* mcspi class */
         &omap2430_mcspi1_hwmod,
         &omap2430_mcspi2_hwmod,