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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1786
1 files changed, 1785 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 8ecfbcde13ba..490789a6bed0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,6 +18,11 @@
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcbsp.h>
22#include <plat/mcspi.h>
23#include <plat/dmtimer.h>
24#include <plat/mmc.h>
25#include <plat/l3_2xxx.h>
21 26
22#include "omap_hwmod_common_data.h" 27#include "omap_hwmod_common_data.h"
23 28
@@ -38,6 +43,10 @@ static struct omap_hwmod omap2430_mpu_hwmod;
38static struct omap_hwmod omap2430_iva_hwmod; 43static struct omap_hwmod omap2430_iva_hwmod;
39static struct omap_hwmod omap2430_l3_main_hwmod; 44static struct omap_hwmod omap2430_l3_main_hwmod;
40static struct omap_hwmod omap2430_l4_core_hwmod; 45static struct omap_hwmod omap2430_l4_core_hwmod;
46static struct omap_hwmod omap2430_dss_core_hwmod;
47static struct omap_hwmod omap2430_dss_dispc_hwmod;
48static struct omap_hwmod omap2430_dss_rfbi_hwmod;
49static struct omap_hwmod omap2430_dss_venc_hwmod;
41static struct omap_hwmod omap2430_wd_timer2_hwmod; 50static struct omap_hwmod omap2430_wd_timer2_hwmod;
42static struct omap_hwmod omap2430_gpio1_hwmod; 51static struct omap_hwmod omap2430_gpio1_hwmod;
43static struct omap_hwmod omap2430_gpio2_hwmod; 52static struct omap_hwmod omap2430_gpio2_hwmod;
@@ -45,6 +54,16 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
45static struct omap_hwmod omap2430_gpio4_hwmod; 54static struct omap_hwmod omap2430_gpio4_hwmod;
46static struct omap_hwmod omap2430_gpio5_hwmod; 55static struct omap_hwmod omap2430_gpio5_hwmod;
47static struct omap_hwmod omap2430_dma_system_hwmod; 56static struct omap_hwmod omap2430_dma_system_hwmod;
57static struct omap_hwmod omap2430_mcbsp1_hwmod;
58static struct omap_hwmod omap2430_mcbsp2_hwmod;
59static struct omap_hwmod omap2430_mcbsp3_hwmod;
60static struct omap_hwmod omap2430_mcbsp4_hwmod;
61static struct omap_hwmod omap2430_mcbsp5_hwmod;
62static struct omap_hwmod omap2430_mcspi1_hwmod;
63static struct omap_hwmod omap2430_mcspi2_hwmod;
64static struct omap_hwmod omap2430_mcspi3_hwmod;
65static struct omap_hwmod omap2430_mmc1_hwmod;
66static struct omap_hwmod omap2430_mmc2_hwmod;
48 67
49/* L3 -> L4_CORE interface */ 68/* L3 -> L4_CORE interface */
50static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 69static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -65,6 +84,19 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
65 &omap2430_mpu__l3_main, 84 &omap2430_mpu__l3_main,
66}; 85};
67 86
87/* DSS -> l3 */
88static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
89 .master = &omap2430_dss_core_hwmod,
90 .slave = &omap2430_l3_main_hwmod,
91 .fw = {
92 .omap2 = {
93 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
94 .flags = OMAP_FIREWALL_L3,
95 }
96 },
97 .user = OCP_USER_MPU | OCP_USER_SDMA,
98};
99
68/* Master interfaces on the L3 interconnect */ 100/* Master interfaces on the L3 interconnect */
69static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { 101static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
70 &omap2430_l3_main__l4_core, 102 &omap2430_l3_main__l4_core,
@@ -89,6 +121,16 @@ static struct omap_hwmod omap2430_uart3_hwmod;
89static struct omap_hwmod omap2430_i2c1_hwmod; 121static struct omap_hwmod omap2430_i2c1_hwmod;
90static struct omap_hwmod omap2430_i2c2_hwmod; 122static struct omap_hwmod omap2430_i2c2_hwmod;
91 123
124static struct omap_hwmod omap2430_usbhsotg_hwmod;
125
126/* l3_core -> usbhsotg interface */
127static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
128 .master = &omap2430_usbhsotg_hwmod,
129 .slave = &omap2430_l3_main_hwmod,
130 .clk = "core_l3_ck",
131 .user = OCP_USER_MPU,
132};
133
92/* I2C IP block address space length (in bytes) */ 134/* I2C IP block address space length (in bytes) */
93#define OMAP2_I2C_AS_LEN 128 135#define OMAP2_I2C_AS_LEN 128
94 136
@@ -189,6 +231,71 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
189 .user = OCP_USER_MPU | OCP_USER_SDMA, 231 .user = OCP_USER_MPU | OCP_USER_SDMA,
190}; 232};
191 233
234/*
235* usbhsotg interface data
236*/
237static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
238 {
239 .pa_start = OMAP243X_HS_BASE,
240 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
241 .flags = ADDR_TYPE_RT
242 },
243};
244
245/* l4_core ->usbhsotg interface */
246static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
247 .master = &omap2430_l4_core_hwmod,
248 .slave = &omap2430_usbhsotg_hwmod,
249 .clk = "usb_l4_ick",
250 .addr = omap2430_usbhsotg_addrs,
251 .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
252 .user = OCP_USER_MPU,
253};
254
255static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
256 &omap2430_usbhsotg__l3,
257};
258
259static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
260 &omap2430_l4_core__usbhsotg,
261};
262
263/* L4 CORE -> MMC1 interface */
264static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
265 {
266 .pa_start = 0x4809c000,
267 .pa_end = 0x4809c1ff,
268 .flags = ADDR_TYPE_RT,
269 },
270};
271
272static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
273 .master = &omap2430_l4_core_hwmod,
274 .slave = &omap2430_mmc1_hwmod,
275 .clk = "mmchs1_ick",
276 .addr = omap2430_mmc1_addr_space,
277 .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
279};
280
281/* L4 CORE -> MMC2 interface */
282static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
283 {
284 .pa_start = 0x480b4000,
285 .pa_end = 0x480b41ff,
286 .flags = ADDR_TYPE_RT,
287 },
288};
289
290static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
291 .master = &omap2430_l4_core_hwmod,
292 .slave = &omap2430_mmc2_hwmod,
293 .addr = omap2430_mmc2_addr_space,
294 .clk = "mmchs2_ick",
295 .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space),
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297};
298
192/* Slave interfaces on the L4_CORE interconnect */ 299/* Slave interfaces on the L4_CORE interconnect */
193static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { 300static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
194 &omap2430_l3_main__l4_core, 301 &omap2430_l3_main__l4_core,
@@ -197,6 +304,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
197/* Master interfaces on the L4_CORE interconnect */ 304/* Master interfaces on the L4_CORE interconnect */
198static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { 305static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
199 &omap2430_l4_core__l4_wkup, 306 &omap2430_l4_core__l4_wkup,
307 &omap2430_l4_core__mmc1,
308 &omap2430_l4_core__mmc2,
200}; 309};
201 310
202/* L4 CORE */ 311/* L4 CORE */
@@ -223,6 +332,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
223static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { 332static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
224}; 333};
225 334
335/* l4 core -> mcspi1 interface */
336static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
337 {
338 .pa_start = 0x48098000,
339 .pa_end = 0x480980ff,
340 .flags = ADDR_TYPE_RT,
341 },
342};
343
344static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
345 .master = &omap2430_l4_core_hwmod,
346 .slave = &omap2430_mcspi1_hwmod,
347 .clk = "mcspi1_ick",
348 .addr = omap2430_mcspi1_addr_space,
349 .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
350 .user = OCP_USER_MPU | OCP_USER_SDMA,
351};
352
353/* l4 core -> mcspi2 interface */
354static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
355 {
356 .pa_start = 0x4809a000,
357 .pa_end = 0x4809a0ff,
358 .flags = ADDR_TYPE_RT,
359 },
360};
361
362static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
363 .master = &omap2430_l4_core_hwmod,
364 .slave = &omap2430_mcspi2_hwmod,
365 .clk = "mcspi2_ick",
366 .addr = omap2430_mcspi2_addr_space,
367 .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
368 .user = OCP_USER_MPU | OCP_USER_SDMA,
369};
370
371/* l4 core -> mcspi3 interface */
372static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
373 {
374 .pa_start = 0x480b8000,
375 .pa_end = 0x480b80ff,
376 .flags = ADDR_TYPE_RT,
377 },
378};
379
380static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
381 .master = &omap2430_l4_core_hwmod,
382 .slave = &omap2430_mcspi3_hwmod,
383 .clk = "mcspi3_ick",
384 .addr = omap2430_mcspi3_addr_space,
385 .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
386 .user = OCP_USER_MPU | OCP_USER_SDMA,
387};
388
226/* L4 WKUP */ 389/* L4 WKUP */
227static struct omap_hwmod omap2430_l4_wkup_hwmod = { 390static struct omap_hwmod omap2430_l4_wkup_hwmod = {
228 .name = "l4_wkup", 391 .name = "l4_wkup",
@@ -278,6 +441,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
279}; 442};
280 443
444/* Timer Common */
445static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
446 .rev_offs = 0x0000,
447 .sysc_offs = 0x0010,
448 .syss_offs = 0x0014,
449 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
450 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
451 SYSC_HAS_AUTOIDLE),
452 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454};
455
456static struct omap_hwmod_class omap2430_timer_hwmod_class = {
457 .name = "timer",
458 .sysc = &omap2430_timer_sysc,
459 .rev = OMAP_TIMER_IP_VERSION_1,
460};
461
462/* timer1 */
463static struct omap_hwmod omap2430_timer1_hwmod;
464static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
465 { .irq = 37, },
466};
467
468static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
469 {
470 .pa_start = 0x49018000,
471 .pa_end = 0x49018000 + SZ_1K - 1,
472 .flags = ADDR_TYPE_RT
473 },
474};
475
476/* l4_wkup -> timer1 */
477static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
478 .master = &omap2430_l4_wkup_hwmod,
479 .slave = &omap2430_timer1_hwmod,
480 .clk = "gpt1_ick",
481 .addr = omap2430_timer1_addrs,
482 .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
483 .user = OCP_USER_MPU | OCP_USER_SDMA,
484};
485
486/* timer1 slave port */
487static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
488 &omap2430_l4_wkup__timer1,
489};
490
491/* timer1 hwmod */
492static struct omap_hwmod omap2430_timer1_hwmod = {
493 .name = "timer1",
494 .mpu_irqs = omap2430_timer1_mpu_irqs,
495 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
496 .main_clk = "gpt1_fck",
497 .prcm = {
498 .omap2 = {
499 .prcm_reg_id = 1,
500 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
501 .module_offs = WKUP_MOD,
502 .idlest_reg_id = 1,
503 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
504 },
505 },
506 .slaves = omap2430_timer1_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
508 .class = &omap2430_timer_hwmod_class,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
510};
511
512/* timer2 */
513static struct omap_hwmod omap2430_timer2_hwmod;
514static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
515 { .irq = 38, },
516};
517
518static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
519 {
520 .pa_start = 0x4802a000,
521 .pa_end = 0x4802a000 + SZ_1K - 1,
522 .flags = ADDR_TYPE_RT
523 },
524};
525
526/* l4_core -> timer2 */
527static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
528 .master = &omap2430_l4_core_hwmod,
529 .slave = &omap2430_timer2_hwmod,
530 .clk = "gpt2_ick",
531 .addr = omap2430_timer2_addrs,
532 .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
533 .user = OCP_USER_MPU | OCP_USER_SDMA,
534};
535
536/* timer2 slave port */
537static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
538 &omap2430_l4_core__timer2,
539};
540
541/* timer2 hwmod */
542static struct omap_hwmod omap2430_timer2_hwmod = {
543 .name = "timer2",
544 .mpu_irqs = omap2430_timer2_mpu_irqs,
545 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
546 .main_clk = "gpt2_fck",
547 .prcm = {
548 .omap2 = {
549 .prcm_reg_id = 1,
550 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
551 .module_offs = CORE_MOD,
552 .idlest_reg_id = 1,
553 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
554 },
555 },
556 .slaves = omap2430_timer2_slaves,
557 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
558 .class = &omap2430_timer_hwmod_class,
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
560};
561
562/* timer3 */
563static struct omap_hwmod omap2430_timer3_hwmod;
564static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
565 { .irq = 39, },
566};
567
568static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
569 {
570 .pa_start = 0x48078000,
571 .pa_end = 0x48078000 + SZ_1K - 1,
572 .flags = ADDR_TYPE_RT
573 },
574};
575
576/* l4_core -> timer3 */
577static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
578 .master = &omap2430_l4_core_hwmod,
579 .slave = &omap2430_timer3_hwmod,
580 .clk = "gpt3_ick",
581 .addr = omap2430_timer3_addrs,
582 .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
583 .user = OCP_USER_MPU | OCP_USER_SDMA,
584};
585
586/* timer3 slave port */
587static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
588 &omap2430_l4_core__timer3,
589};
590
591/* timer3 hwmod */
592static struct omap_hwmod omap2430_timer3_hwmod = {
593 .name = "timer3",
594 .mpu_irqs = omap2430_timer3_mpu_irqs,
595 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
596 .main_clk = "gpt3_fck",
597 .prcm = {
598 .omap2 = {
599 .prcm_reg_id = 1,
600 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
601 .module_offs = CORE_MOD,
602 .idlest_reg_id = 1,
603 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
604 },
605 },
606 .slaves = omap2430_timer3_slaves,
607 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
608 .class = &omap2430_timer_hwmod_class,
609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
610};
611
612/* timer4 */
613static struct omap_hwmod omap2430_timer4_hwmod;
614static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
615 { .irq = 40, },
616};
617
618static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
619 {
620 .pa_start = 0x4807a000,
621 .pa_end = 0x4807a000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625
626/* l4_core -> timer4 */
627static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
628 .master = &omap2430_l4_core_hwmod,
629 .slave = &omap2430_timer4_hwmod,
630 .clk = "gpt4_ick",
631 .addr = omap2430_timer4_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634};
635
636/* timer4 slave port */
637static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
638 &omap2430_l4_core__timer4,
639};
640
641/* timer4 hwmod */
642static struct omap_hwmod omap2430_timer4_hwmod = {
643 .name = "timer4",
644 .mpu_irqs = omap2430_timer4_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
646 .main_clk = "gpt4_fck",
647 .prcm = {
648 .omap2 = {
649 .prcm_reg_id = 1,
650 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
651 .module_offs = CORE_MOD,
652 .idlest_reg_id = 1,
653 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
654 },
655 },
656 .slaves = omap2430_timer4_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
658 .class = &omap2430_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
660};
661
662/* timer5 */
663static struct omap_hwmod omap2430_timer5_hwmod;
664static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
665 { .irq = 41, },
666};
667
668static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
669 {
670 .pa_start = 0x4807c000,
671 .pa_end = 0x4807c000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675
676/* l4_core -> timer5 */
677static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
678 .master = &omap2430_l4_core_hwmod,
679 .slave = &omap2430_timer5_hwmod,
680 .clk = "gpt5_ick",
681 .addr = omap2430_timer5_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
684};
685
686/* timer5 slave port */
687static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
688 &omap2430_l4_core__timer5,
689};
690
691/* timer5 hwmod */
692static struct omap_hwmod omap2430_timer5_hwmod = {
693 .name = "timer5",
694 .mpu_irqs = omap2430_timer5_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
696 .main_clk = "gpt5_fck",
697 .prcm = {
698 .omap2 = {
699 .prcm_reg_id = 1,
700 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
701 .module_offs = CORE_MOD,
702 .idlest_reg_id = 1,
703 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
704 },
705 },
706 .slaves = omap2430_timer5_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
708 .class = &omap2430_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
710};
711
712/* timer6 */
713static struct omap_hwmod omap2430_timer6_hwmod;
714static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
715 { .irq = 42, },
716};
717
718static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
719 {
720 .pa_start = 0x4807e000,
721 .pa_end = 0x4807e000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725
726/* l4_core -> timer6 */
727static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
728 .master = &omap2430_l4_core_hwmod,
729 .slave = &omap2430_timer6_hwmod,
730 .clk = "gpt6_ick",
731 .addr = omap2430_timer6_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA,
734};
735
736/* timer6 slave port */
737static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
738 &omap2430_l4_core__timer6,
739};
740
741/* timer6 hwmod */
742static struct omap_hwmod omap2430_timer6_hwmod = {
743 .name = "timer6",
744 .mpu_irqs = omap2430_timer6_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
746 .main_clk = "gpt6_fck",
747 .prcm = {
748 .omap2 = {
749 .prcm_reg_id = 1,
750 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
751 .module_offs = CORE_MOD,
752 .idlest_reg_id = 1,
753 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
754 },
755 },
756 .slaves = omap2430_timer6_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
758 .class = &omap2430_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
760};
761
762/* timer7 */
763static struct omap_hwmod omap2430_timer7_hwmod;
764static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
765 { .irq = 43, },
766};
767
768static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
769 {
770 .pa_start = 0x48080000,
771 .pa_end = 0x48080000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775
776/* l4_core -> timer7 */
777static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
778 .master = &omap2430_l4_core_hwmod,
779 .slave = &omap2430_timer7_hwmod,
780 .clk = "gpt7_ick",
781 .addr = omap2430_timer7_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
784};
785
786/* timer7 slave port */
787static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
788 &omap2430_l4_core__timer7,
789};
790
791/* timer7 hwmod */
792static struct omap_hwmod omap2430_timer7_hwmod = {
793 .name = "timer7",
794 .mpu_irqs = omap2430_timer7_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
796 .main_clk = "gpt7_fck",
797 .prcm = {
798 .omap2 = {
799 .prcm_reg_id = 1,
800 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
801 .module_offs = CORE_MOD,
802 .idlest_reg_id = 1,
803 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
804 },
805 },
806 .slaves = omap2430_timer7_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
808 .class = &omap2430_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
810};
811
812/* timer8 */
813static struct omap_hwmod omap2430_timer8_hwmod;
814static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
815 { .irq = 44, },
816};
817
818static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
819 {
820 .pa_start = 0x48082000,
821 .pa_end = 0x48082000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825
826/* l4_core -> timer8 */
827static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
828 .master = &omap2430_l4_core_hwmod,
829 .slave = &omap2430_timer8_hwmod,
830 .clk = "gpt8_ick",
831 .addr = omap2430_timer8_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA,
834};
835
836/* timer8 slave port */
837static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
838 &omap2430_l4_core__timer8,
839};
840
841/* timer8 hwmod */
842static struct omap_hwmod omap2430_timer8_hwmod = {
843 .name = "timer8",
844 .mpu_irqs = omap2430_timer8_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
846 .main_clk = "gpt8_fck",
847 .prcm = {
848 .omap2 = {
849 .prcm_reg_id = 1,
850 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
851 .module_offs = CORE_MOD,
852 .idlest_reg_id = 1,
853 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
854 },
855 },
856 .slaves = omap2430_timer8_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
858 .class = &omap2430_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
860};
861
862/* timer9 */
863static struct omap_hwmod omap2430_timer9_hwmod;
864static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
865 { .irq = 45, },
866};
867
868static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
869 {
870 .pa_start = 0x48084000,
871 .pa_end = 0x48084000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875
876/* l4_core -> timer9 */
877static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
878 .master = &omap2430_l4_core_hwmod,
879 .slave = &omap2430_timer9_hwmod,
880 .clk = "gpt9_ick",
881 .addr = omap2430_timer9_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA,
884};
885
886/* timer9 slave port */
887static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
888 &omap2430_l4_core__timer9,
889};
890
891/* timer9 hwmod */
892static struct omap_hwmod omap2430_timer9_hwmod = {
893 .name = "timer9",
894 .mpu_irqs = omap2430_timer9_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
896 .main_clk = "gpt9_fck",
897 .prcm = {
898 .omap2 = {
899 .prcm_reg_id = 1,
900 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
901 .module_offs = CORE_MOD,
902 .idlest_reg_id = 1,
903 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
904 },
905 },
906 .slaves = omap2430_timer9_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
908 .class = &omap2430_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
910};
911
912/* timer10 */
913static struct omap_hwmod omap2430_timer10_hwmod;
914static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
915 { .irq = 46, },
916};
917
918static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
919 {
920 .pa_start = 0x48086000,
921 .pa_end = 0x48086000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925
926/* l4_core -> timer10 */
927static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
928 .master = &omap2430_l4_core_hwmod,
929 .slave = &omap2430_timer10_hwmod,
930 .clk = "gpt10_ick",
931 .addr = omap2430_timer10_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA,
934};
935
936/* timer10 slave port */
937static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
938 &omap2430_l4_core__timer10,
939};
940
941/* timer10 hwmod */
942static struct omap_hwmod omap2430_timer10_hwmod = {
943 .name = "timer10",
944 .mpu_irqs = omap2430_timer10_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
946 .main_clk = "gpt10_fck",
947 .prcm = {
948 .omap2 = {
949 .prcm_reg_id = 1,
950 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
951 .module_offs = CORE_MOD,
952 .idlest_reg_id = 1,
953 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
954 },
955 },
956 .slaves = omap2430_timer10_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
958 .class = &omap2430_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
960};
961
962/* timer11 */
963static struct omap_hwmod omap2430_timer11_hwmod;
964static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
965 { .irq = 47, },
966};
967
968static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
969 {
970 .pa_start = 0x48088000,
971 .pa_end = 0x48088000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT
973 },
974};
975
976/* l4_core -> timer11 */
977static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
978 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_timer11_hwmod,
980 .clk = "gpt11_ick",
981 .addr = omap2430_timer11_addrs,
982 .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA,
984};
985
986/* timer11 slave port */
987static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
988 &omap2430_l4_core__timer11,
989};
990
991/* timer11 hwmod */
992static struct omap_hwmod omap2430_timer11_hwmod = {
993 .name = "timer11",
994 .mpu_irqs = omap2430_timer11_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
996 .main_clk = "gpt11_fck",
997 .prcm = {
998 .omap2 = {
999 .prcm_reg_id = 1,
1000 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
1001 .module_offs = CORE_MOD,
1002 .idlest_reg_id = 1,
1003 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
1004 },
1005 },
1006 .slaves = omap2430_timer11_slaves,
1007 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
1008 .class = &omap2430_timer_hwmod_class,
1009 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1010};
1011
1012/* timer12 */
1013static struct omap_hwmod omap2430_timer12_hwmod;
1014static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1015 { .irq = 48, },
1016};
1017
1018static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1019 {
1020 .pa_start = 0x4808a000,
1021 .pa_end = 0x4808a000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT
1023 },
1024};
1025
1026/* l4_core -> timer12 */
1027static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1028 .master = &omap2430_l4_core_hwmod,
1029 .slave = &omap2430_timer12_hwmod,
1030 .clk = "gpt12_ick",
1031 .addr = omap2430_timer12_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034};
1035
1036/* timer12 slave port */
1037static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1038 &omap2430_l4_core__timer12,
1039};
1040
1041/* timer12 hwmod */
1042static struct omap_hwmod omap2430_timer12_hwmod = {
1043 .name = "timer12",
1044 .mpu_irqs = omap2430_timer12_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1046 .main_clk = "gpt12_fck",
1047 .prcm = {
1048 .omap2 = {
1049 .prcm_reg_id = 1,
1050 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1051 .module_offs = CORE_MOD,
1052 .idlest_reg_id = 1,
1053 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1054 },
1055 },
1056 .slaves = omap2430_timer12_slaves,
1057 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
1058 .class = &omap2430_timer_hwmod_class,
1059 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1060};
1061
281/* l4_wkup -> wd_timer2 */ 1062/* l4_wkup -> wd_timer2 */
282static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { 1063static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
283 { 1064 {
@@ -469,6 +1250,267 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
469 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
470}; 1251};
471 1252
1253/*
1254 * 'dss' class
1255 * display sub-system
1256 */
1257
1258static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1259 .rev_offs = 0x0000,
1260 .sysc_offs = 0x0010,
1261 .syss_offs = 0x0014,
1262 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1263 .sysc_fields = &omap_hwmod_sysc_type1,
1264};
1265
1266static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1267 .name = "dss",
1268 .sysc = &omap2430_dss_sysc,
1269};
1270
1271/* dss */
1272static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
1273 { .irq = 25 },
1274};
1275static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1276 { .name = "dispc", .dma_req = 5 },
1277};
1278
1279/* dss */
1280/* dss master ports */
1281static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1282 &omap2430_dss__l3,
1283};
1284
1285static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1286 {
1287 .pa_start = 0x48050000,
1288 .pa_end = 0x480503FF,
1289 .flags = ADDR_TYPE_RT
1290 },
1291};
1292
1293/* l4_core -> dss */
1294static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1295 .master = &omap2430_l4_core_hwmod,
1296 .slave = &omap2430_dss_core_hwmod,
1297 .clk = "dss_ick",
1298 .addr = omap2430_dss_addrs,
1299 .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
1300 .user = OCP_USER_MPU | OCP_USER_SDMA,
1301};
1302
1303/* dss slave ports */
1304static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
1305 &omap2430_l4_core__dss,
1306};
1307
1308static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1309 { .role = "tv_clk", .clk = "dss_54m_fck" },
1310 { .role = "sys_clk", .clk = "dss2_fck" },
1311};
1312
1313static struct omap_hwmod omap2430_dss_core_hwmod = {
1314 .name = "dss_core",
1315 .class = &omap2430_dss_hwmod_class,
1316 .main_clk = "dss1_fck", /* instead of dss_fck */
1317 .mpu_irqs = omap2430_dss_irqs,
1318 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs),
1319 .sdma_reqs = omap2430_dss_sdma_chs,
1320 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
1321 .prcm = {
1322 .omap2 = {
1323 .prcm_reg_id = 1,
1324 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1325 .module_offs = CORE_MOD,
1326 .idlest_reg_id = 1,
1327 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1328 },
1329 },
1330 .opt_clks = dss_opt_clks,
1331 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1332 .slaves = omap2430_dss_slaves,
1333 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
1334 .masters = omap2430_dss_masters,
1335 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
1336 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1337 .flags = HWMOD_NO_IDLEST,
1338};
1339
1340/*
1341 * 'dispc' class
1342 * display controller
1343 */
1344
1345static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1346 .rev_offs = 0x0000,
1347 .sysc_offs = 0x0010,
1348 .syss_offs = 0x0014,
1349 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1350 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1351 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1352 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1353 .sysc_fields = &omap_hwmod_sysc_type1,
1354};
1355
1356static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1357 .name = "dispc",
1358 .sysc = &omap2430_dispc_sysc,
1359};
1360
1361static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1362 {
1363 .pa_start = 0x48050400,
1364 .pa_end = 0x480507FF,
1365 .flags = ADDR_TYPE_RT
1366 },
1367};
1368
1369/* l4_core -> dss_dispc */
1370static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1371 .master = &omap2430_l4_core_hwmod,
1372 .slave = &omap2430_dss_dispc_hwmod,
1373 .clk = "dss_ick",
1374 .addr = omap2430_dss_dispc_addrs,
1375 .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
1376 .user = OCP_USER_MPU | OCP_USER_SDMA,
1377};
1378
1379/* dss_dispc slave ports */
1380static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1381 &omap2430_l4_core__dss_dispc,
1382};
1383
1384static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1385 .name = "dss_dispc",
1386 .class = &omap2430_dispc_hwmod_class,
1387 .main_clk = "dss1_fck",
1388 .prcm = {
1389 .omap2 = {
1390 .prcm_reg_id = 1,
1391 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1392 .module_offs = CORE_MOD,
1393 .idlest_reg_id = 1,
1394 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1395 },
1396 },
1397 .slaves = omap2430_dss_dispc_slaves,
1398 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1399 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1400 .flags = HWMOD_NO_IDLEST,
1401};
1402
1403/*
1404 * 'rfbi' class
1405 * remote frame buffer interface
1406 */
1407
1408static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1409 .rev_offs = 0x0000,
1410 .sysc_offs = 0x0010,
1411 .syss_offs = 0x0014,
1412 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1413 SYSC_HAS_AUTOIDLE),
1414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1415 .sysc_fields = &omap_hwmod_sysc_type1,
1416};
1417
1418static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1419 .name = "rfbi",
1420 .sysc = &omap2430_rfbi_sysc,
1421};
1422
1423static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1424 {
1425 .pa_start = 0x48050800,
1426 .pa_end = 0x48050BFF,
1427 .flags = ADDR_TYPE_RT
1428 },
1429};
1430
1431/* l4_core -> dss_rfbi */
1432static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1433 .master = &omap2430_l4_core_hwmod,
1434 .slave = &omap2430_dss_rfbi_hwmod,
1435 .clk = "dss_ick",
1436 .addr = omap2430_dss_rfbi_addrs,
1437 .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
1438 .user = OCP_USER_MPU | OCP_USER_SDMA,
1439};
1440
1441/* dss_rfbi slave ports */
1442static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1443 &omap2430_l4_core__dss_rfbi,
1444};
1445
1446static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1447 .name = "dss_rfbi",
1448 .class = &omap2430_rfbi_hwmod_class,
1449 .main_clk = "dss1_fck",
1450 .prcm = {
1451 .omap2 = {
1452 .prcm_reg_id = 1,
1453 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1454 .module_offs = CORE_MOD,
1455 },
1456 },
1457 .slaves = omap2430_dss_rfbi_slaves,
1458 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1459 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1460 .flags = HWMOD_NO_IDLEST,
1461};
1462
1463/*
1464 * 'venc' class
1465 * video encoder
1466 */
1467
1468static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1469 .name = "venc",
1470};
1471
1472/* dss_venc */
1473static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1474 {
1475 .pa_start = 0x48050C00,
1476 .pa_end = 0x48050FFF,
1477 .flags = ADDR_TYPE_RT
1478 },
1479};
1480
1481/* l4_core -> dss_venc */
1482static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1483 .master = &omap2430_l4_core_hwmod,
1484 .slave = &omap2430_dss_venc_hwmod,
1485 .clk = "dss_54m_fck",
1486 .addr = omap2430_dss_venc_addrs,
1487 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
1488 .flags = OCPIF_SWSUP_IDLE,
1489 .user = OCP_USER_MPU | OCP_USER_SDMA,
1490};
1491
1492/* dss_venc slave ports */
1493static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1494 &omap2430_l4_core__dss_venc,
1495};
1496
1497static struct omap_hwmod omap2430_dss_venc_hwmod = {
1498 .name = "dss_venc",
1499 .class = &omap2430_venc_hwmod_class,
1500 .main_clk = "dss1_fck",
1501 .prcm = {
1502 .omap2 = {
1503 .prcm_reg_id = 1,
1504 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1505 .module_offs = CORE_MOD,
1506 },
1507 },
1508 .slaves = omap2430_dss_venc_slaves,
1509 .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
1510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1511 .flags = HWMOD_NO_IDLEST,
1512};
1513
472/* I2C common */ 1514/* I2C common */
473static struct omap_hwmod_class_sysconfig i2c_sysc = { 1515static struct omap_hwmod_class_sysconfig i2c_sysc = {
474 .rev_offs = 0x00, 1516 .rev_offs = 0x00,
@@ -919,18 +1961,741 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
919 .flags = HWMOD_NO_IDLEST, 1961 .flags = HWMOD_NO_IDLEST,
920}; 1962};
921 1963
1964/*
1965 * 'mailbox' class
1966 * mailbox module allowing communication between the on-chip processors
1967 * using a queued mailbox-interrupt mechanism.
1968 */
1969
1970static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1971 .rev_offs = 0x000,
1972 .sysc_offs = 0x010,
1973 .syss_offs = 0x014,
1974 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1975 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1976 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1977 .sysc_fields = &omap_hwmod_sysc_type1,
1978};
1979
1980static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1981 .name = "mailbox",
1982 .sysc = &omap2430_mailbox_sysc,
1983};
1984
1985/* mailbox */
1986static struct omap_hwmod omap2430_mailbox_hwmod;
1987static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1988 { .irq = 26 },
1989};
1990
1991static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1992 {
1993 .pa_start = 0x48094000,
1994 .pa_end = 0x480941ff,
1995 .flags = ADDR_TYPE_RT,
1996 },
1997};
1998
1999/* l4_core -> mailbox */
2000static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2001 .master = &omap2430_l4_core_hwmod,
2002 .slave = &omap2430_mailbox_hwmod,
2003 .addr = omap2430_mailbox_addrs,
2004 .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
2005 .user = OCP_USER_MPU | OCP_USER_SDMA,
2006};
2007
2008/* mailbox slave ports */
2009static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2010 &omap2430_l4_core__mailbox,
2011};
2012
2013static struct omap_hwmod omap2430_mailbox_hwmod = {
2014 .name = "mailbox",
2015 .class = &omap2430_mailbox_hwmod_class,
2016 .mpu_irqs = omap2430_mailbox_irqs,
2017 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
2018 .main_clk = "mailboxes_ick",
2019 .prcm = {
2020 .omap2 = {
2021 .prcm_reg_id = 1,
2022 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2023 .module_offs = CORE_MOD,
2024 .idlest_reg_id = 1,
2025 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
2026 },
2027 },
2028 .slaves = omap2430_mailbox_slaves,
2029 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
2030 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2031};
2032
2033/*
2034 * 'mcspi' class
2035 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2036 * bus
2037 */
2038
2039static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
2040 .rev_offs = 0x0000,
2041 .sysc_offs = 0x0010,
2042 .syss_offs = 0x0014,
2043 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2044 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2045 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2046 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2047 .sysc_fields = &omap_hwmod_sysc_type1,
2048};
2049
2050static struct omap_hwmod_class omap2430_mcspi_class = {
2051 .name = "mcspi",
2052 .sysc = &omap2430_mcspi_sysc,
2053 .rev = OMAP2_MCSPI_REV,
2054};
2055
2056/* mcspi1 */
2057static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
2058 { .irq = 65 },
2059};
2060
2061static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
2062 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
2063 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
2064 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
2065 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
2066 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
2067 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
2068 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
2069 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
2070};
2071
2072static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
2073 &omap2430_l4_core__mcspi1,
2074};
2075
2076static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2077 .num_chipselect = 4,
2078};
2079
2080static struct omap_hwmod omap2430_mcspi1_hwmod = {
2081 .name = "mcspi1_hwmod",
2082 .mpu_irqs = omap2430_mcspi1_mpu_irqs,
2083 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
2084 .sdma_reqs = omap2430_mcspi1_sdma_reqs,
2085 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
2086 .main_clk = "mcspi1_fck",
2087 .prcm = {
2088 .omap2 = {
2089 .module_offs = CORE_MOD,
2090 .prcm_reg_id = 1,
2091 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2092 .idlest_reg_id = 1,
2093 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
2094 },
2095 },
2096 .slaves = omap2430_mcspi1_slaves,
2097 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
2098 .class = &omap2430_mcspi_class,
2099 .dev_attr = &omap_mcspi1_dev_attr,
2100 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2101};
2102
2103/* mcspi2 */
2104static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
2105 { .irq = 66 },
2106};
2107
2108static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
2109 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
2110 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
2111 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
2112 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
2113};
2114
2115static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
2116 &omap2430_l4_core__mcspi2,
2117};
2118
2119static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2120 .num_chipselect = 2,
2121};
2122
2123static struct omap_hwmod omap2430_mcspi2_hwmod = {
2124 .name = "mcspi2_hwmod",
2125 .mpu_irqs = omap2430_mcspi2_mpu_irqs,
2126 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
2127 .sdma_reqs = omap2430_mcspi2_sdma_reqs,
2128 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2129 .main_clk = "mcspi2_fck",
2130 .prcm = {
2131 .omap2 = {
2132 .module_offs = CORE_MOD,
2133 .prcm_reg_id = 1,
2134 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2135 .idlest_reg_id = 1,
2136 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2137 },
2138 },
2139 .slaves = omap2430_mcspi2_slaves,
2140 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
2141 .class = &omap2430_mcspi_class,
2142 .dev_attr = &omap_mcspi2_dev_attr,
2143 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2144};
2145
2146/* mcspi3 */
2147static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2148 { .irq = 91 },
2149};
2150
2151static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2152 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
2153 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2154 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2155 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
2156};
2157
2158static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
2159 &omap2430_l4_core__mcspi3,
2160};
2161
2162static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2163 .num_chipselect = 2,
2164};
2165
2166static struct omap_hwmod omap2430_mcspi3_hwmod = {
2167 .name = "mcspi3_hwmod",
2168 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
2169 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2170 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
2171 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2172 .main_clk = "mcspi3_fck",
2173 .prcm = {
2174 .omap2 = {
2175 .module_offs = CORE_MOD,
2176 .prcm_reg_id = 2,
2177 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
2178 .idlest_reg_id = 2,
2179 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
2180 },
2181 },
2182 .slaves = omap2430_mcspi3_slaves,
2183 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
2184 .class = &omap2430_mcspi_class,
2185 .dev_attr = &omap_mcspi3_dev_attr,
2186 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2187};
2188
2189/*
2190 * usbhsotg
2191 */
2192static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
2193 .rev_offs = 0x0400,
2194 .sysc_offs = 0x0404,
2195 .syss_offs = 0x0408,
2196 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2197 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2198 SYSC_HAS_AUTOIDLE),
2199 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2200 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2201 .sysc_fields = &omap_hwmod_sysc_type1,
2202};
2203
2204static struct omap_hwmod_class usbotg_class = {
2205 .name = "usbotg",
2206 .sysc = &omap2430_usbhsotg_sysc,
2207};
2208
2209/* usb_otg_hs */
2210static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2211
2212 { .name = "mc", .irq = 92 },
2213 { .name = "dma", .irq = 93 },
2214};
2215
2216static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2217 .name = "usb_otg_hs",
2218 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
2219 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2220 .main_clk = "usbhs_ick",
2221 .prcm = {
2222 .omap2 = {
2223 .prcm_reg_id = 1,
2224 .module_bit = OMAP2430_EN_USBHS_MASK,
2225 .module_offs = CORE_MOD,
2226 .idlest_reg_id = 1,
2227 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
2228 },
2229 },
2230 .masters = omap2430_usbhsotg_masters,
2231 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
2232 .slaves = omap2430_usbhsotg_slaves,
2233 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
2234 .class = &usbotg_class,
2235 /*
2236 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
2237 * broken when autoidle is enabled
2238 * workaround is to disable the autoidle bit at module level.
2239 */
2240 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2241 | HWMOD_SWSUP_MSTANDBY,
2242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2243};
2244
2245/*
2246 * 'mcbsp' class
2247 * multi channel buffered serial port controller
2248 */
2249
2250static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
2251 .rev_offs = 0x007C,
2252 .sysc_offs = 0x008C,
2253 .sysc_flags = (SYSC_HAS_SOFTRESET),
2254 .sysc_fields = &omap_hwmod_sysc_type1,
2255};
2256
2257static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
2258 .name = "mcbsp",
2259 .sysc = &omap2430_mcbsp_sysc,
2260 .rev = MCBSP_CONFIG_TYPE2,
2261};
2262
2263/* mcbsp1 */
2264static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2265 { .name = "tx", .irq = 59 },
2266 { .name = "rx", .irq = 60 },
2267 { .name = "ovr", .irq = 61 },
2268 { .name = "common", .irq = 64 },
2269};
2270
2271static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2272 { .name = "rx", .dma_req = 32 },
2273 { .name = "tx", .dma_req = 31 },
2274};
2275
2276static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2277 {
2278 .name = "mpu",
2279 .pa_start = 0x48074000,
2280 .pa_end = 0x480740ff,
2281 .flags = ADDR_TYPE_RT
2282 },
2283};
2284
2285/* l4_core -> mcbsp1 */
2286static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2287 .master = &omap2430_l4_core_hwmod,
2288 .slave = &omap2430_mcbsp1_hwmod,
2289 .clk = "mcbsp1_ick",
2290 .addr = omap2430_mcbsp1_addrs,
2291 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
2292 .user = OCP_USER_MPU | OCP_USER_SDMA,
2293};
2294
2295/* mcbsp1 slave ports */
2296static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
2297 &omap2430_l4_core__mcbsp1,
2298};
2299
2300static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2301 .name = "mcbsp1",
2302 .class = &omap2430_mcbsp_hwmod_class,
2303 .mpu_irqs = omap2430_mcbsp1_irqs,
2304 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
2305 .sdma_reqs = omap2430_mcbsp1_sdma_chs,
2306 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2307 .main_clk = "mcbsp1_fck",
2308 .prcm = {
2309 .omap2 = {
2310 .prcm_reg_id = 1,
2311 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2312 .module_offs = CORE_MOD,
2313 .idlest_reg_id = 1,
2314 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2315 },
2316 },
2317 .slaves = omap2430_mcbsp1_slaves,
2318 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
2319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2320};
2321
2322/* mcbsp2 */
2323static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2324 { .name = "tx", .irq = 62 },
2325 { .name = "rx", .irq = 63 },
2326 { .name = "common", .irq = 16 },
2327};
2328
2329static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2330 { .name = "rx", .dma_req = 34 },
2331 { .name = "tx", .dma_req = 33 },
2332};
2333
2334static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2335 {
2336 .name = "mpu",
2337 .pa_start = 0x48076000,
2338 .pa_end = 0x480760ff,
2339 .flags = ADDR_TYPE_RT
2340 },
2341};
2342
2343/* l4_core -> mcbsp2 */
2344static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2345 .master = &omap2430_l4_core_hwmod,
2346 .slave = &omap2430_mcbsp2_hwmod,
2347 .clk = "mcbsp2_ick",
2348 .addr = omap2430_mcbsp2_addrs,
2349 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2351};
2352
2353/* mcbsp2 slave ports */
2354static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
2355 &omap2430_l4_core__mcbsp2,
2356};
2357
2358static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2359 .name = "mcbsp2",
2360 .class = &omap2430_mcbsp_hwmod_class,
2361 .mpu_irqs = omap2430_mcbsp2_irqs,
2362 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
2363 .sdma_reqs = omap2430_mcbsp2_sdma_chs,
2364 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2365 .main_clk = "mcbsp2_fck",
2366 .prcm = {
2367 .omap2 = {
2368 .prcm_reg_id = 1,
2369 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2370 .module_offs = CORE_MOD,
2371 .idlest_reg_id = 1,
2372 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2373 },
2374 },
2375 .slaves = omap2430_mcbsp2_slaves,
2376 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
2377 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2378};
2379
2380/* mcbsp3 */
2381static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2382 { .name = "tx", .irq = 89 },
2383 { .name = "rx", .irq = 90 },
2384 { .name = "common", .irq = 17 },
2385};
2386
2387static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2388 { .name = "rx", .dma_req = 18 },
2389 { .name = "tx", .dma_req = 17 },
2390};
2391
2392static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2393 {
2394 .name = "mpu",
2395 .pa_start = 0x4808C000,
2396 .pa_end = 0x4808C0ff,
2397 .flags = ADDR_TYPE_RT
2398 },
2399};
2400
2401/* l4_core -> mcbsp3 */
2402static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2403 .master = &omap2430_l4_core_hwmod,
2404 .slave = &omap2430_mcbsp3_hwmod,
2405 .clk = "mcbsp3_ick",
2406 .addr = omap2430_mcbsp3_addrs,
2407 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409};
2410
2411/* mcbsp3 slave ports */
2412static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
2413 &omap2430_l4_core__mcbsp3,
2414};
2415
2416static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2417 .name = "mcbsp3",
2418 .class = &omap2430_mcbsp_hwmod_class,
2419 .mpu_irqs = omap2430_mcbsp3_irqs,
2420 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
2421 .sdma_reqs = omap2430_mcbsp3_sdma_chs,
2422 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2423 .main_clk = "mcbsp3_fck",
2424 .prcm = {
2425 .omap2 = {
2426 .prcm_reg_id = 1,
2427 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
2428 .module_offs = CORE_MOD,
2429 .idlest_reg_id = 2,
2430 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
2431 },
2432 },
2433 .slaves = omap2430_mcbsp3_slaves,
2434 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
2435 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2436};
2437
2438/* mcbsp4 */
2439static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2440 { .name = "tx", .irq = 54 },
2441 { .name = "rx", .irq = 55 },
2442 { .name = "common", .irq = 18 },
2443};
2444
2445static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2446 { .name = "rx", .dma_req = 20 },
2447 { .name = "tx", .dma_req = 19 },
2448};
2449
2450static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2451 {
2452 .name = "mpu",
2453 .pa_start = 0x4808E000,
2454 .pa_end = 0x4808E0ff,
2455 .flags = ADDR_TYPE_RT
2456 },
2457};
2458
2459/* l4_core -> mcbsp4 */
2460static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2461 .master = &omap2430_l4_core_hwmod,
2462 .slave = &omap2430_mcbsp4_hwmod,
2463 .clk = "mcbsp4_ick",
2464 .addr = omap2430_mcbsp4_addrs,
2465 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
2466 .user = OCP_USER_MPU | OCP_USER_SDMA,
2467};
2468
2469/* mcbsp4 slave ports */
2470static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
2471 &omap2430_l4_core__mcbsp4,
2472};
2473
2474static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2475 .name = "mcbsp4",
2476 .class = &omap2430_mcbsp_hwmod_class,
2477 .mpu_irqs = omap2430_mcbsp4_irqs,
2478 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2479 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
2480 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2481 .main_clk = "mcbsp4_fck",
2482 .prcm = {
2483 .omap2 = {
2484 .prcm_reg_id = 1,
2485 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
2486 .module_offs = CORE_MOD,
2487 .idlest_reg_id = 2,
2488 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
2489 },
2490 },
2491 .slaves = omap2430_mcbsp4_slaves,
2492 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
2493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2494};
2495
2496/* mcbsp5 */
2497static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2498 { .name = "tx", .irq = 81 },
2499 { .name = "rx", .irq = 82 },
2500 { .name = "common", .irq = 19 },
2501};
2502
2503static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2504 { .name = "rx", .dma_req = 22 },
2505 { .name = "tx", .dma_req = 21 },
2506};
2507
2508static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2509 {
2510 .name = "mpu",
2511 .pa_start = 0x48096000,
2512 .pa_end = 0x480960ff,
2513 .flags = ADDR_TYPE_RT
2514 },
2515};
2516
2517/* l4_core -> mcbsp5 */
2518static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2519 .master = &omap2430_l4_core_hwmod,
2520 .slave = &omap2430_mcbsp5_hwmod,
2521 .clk = "mcbsp5_ick",
2522 .addr = omap2430_mcbsp5_addrs,
2523 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525};
2526
2527/* mcbsp5 slave ports */
2528static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
2529 &omap2430_l4_core__mcbsp5,
2530};
2531
2532static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2533 .name = "mcbsp5",
2534 .class = &omap2430_mcbsp_hwmod_class,
2535 .mpu_irqs = omap2430_mcbsp5_irqs,
2536 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2537 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
2538 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2539 .main_clk = "mcbsp5_fck",
2540 .prcm = {
2541 .omap2 = {
2542 .prcm_reg_id = 1,
2543 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
2544 .module_offs = CORE_MOD,
2545 .idlest_reg_id = 2,
2546 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
2547 },
2548 },
2549 .slaves = omap2430_mcbsp5_slaves,
2550 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
2551 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2552};
2553
2554/* MMC/SD/SDIO common */
2555
2556static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2557 .rev_offs = 0x1fc,
2558 .sysc_offs = 0x10,
2559 .syss_offs = 0x14,
2560 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2561 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2562 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2564 .sysc_fields = &omap_hwmod_sysc_type1,
2565};
2566
2567static struct omap_hwmod_class omap2430_mmc_class = {
2568 .name = "mmc",
2569 .sysc = &omap2430_mmc_sysc,
2570};
2571
2572/* MMC/SD/SDIO1 */
2573
2574static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2575 { .irq = 83 },
2576};
2577
2578static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2579 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2580 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2581};
2582
2583static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2584 { .role = "dbck", .clk = "mmchsdb1_fck" },
2585};
2586
2587static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2588 &omap2430_l4_core__mmc1,
2589};
2590
2591static struct omap_mmc_dev_attr mmc1_dev_attr = {
2592 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2593};
2594
2595static struct omap_hwmod omap2430_mmc1_hwmod = {
2596 .name = "mmc1",
2597 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2598 .mpu_irqs = omap2430_mmc1_mpu_irqs,
2599 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2600 .sdma_reqs = omap2430_mmc1_sdma_reqs,
2601 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2602 .opt_clks = omap2430_mmc1_opt_clks,
2603 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2604 .main_clk = "mmchs1_fck",
2605 .prcm = {
2606 .omap2 = {
2607 .module_offs = CORE_MOD,
2608 .prcm_reg_id = 2,
2609 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
2610 .idlest_reg_id = 2,
2611 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2612 },
2613 },
2614 .dev_attr = &mmc1_dev_attr,
2615 .slaves = omap2430_mmc1_slaves,
2616 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
2617 .class = &omap2430_mmc_class,
2618 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2619};
2620
2621/* MMC/SD/SDIO2 */
2622
2623static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2624 { .irq = 86 },
2625};
2626
2627static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2628 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2629 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2630};
2631
2632static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2633 { .role = "dbck", .clk = "mmchsdb2_fck" },
2634};
2635
2636static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2637 &omap2430_l4_core__mmc2,
2638};
2639
2640static struct omap_hwmod omap2430_mmc2_hwmod = {
2641 .name = "mmc2",
2642 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2643 .mpu_irqs = omap2430_mmc2_mpu_irqs,
2644 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2645 .sdma_reqs = omap2430_mmc2_sdma_reqs,
2646 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2647 .opt_clks = omap2430_mmc2_opt_clks,
2648 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2649 .main_clk = "mmchs2_fck",
2650 .prcm = {
2651 .omap2 = {
2652 .module_offs = CORE_MOD,
2653 .prcm_reg_id = 2,
2654 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
2655 .idlest_reg_id = 2,
2656 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2657 },
2658 },
2659 .slaves = omap2430_mmc2_slaves,
2660 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2661 .class = &omap2430_mmc_class,
2662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2663};
2664
922static __initdata struct omap_hwmod *omap2430_hwmods[] = { 2665static __initdata struct omap_hwmod *omap2430_hwmods[] = {
923 &omap2430_l3_main_hwmod, 2666 &omap2430_l3_main_hwmod,
924 &omap2430_l4_core_hwmod, 2667 &omap2430_l4_core_hwmod,
925 &omap2430_l4_wkup_hwmod, 2668 &omap2430_l4_wkup_hwmod,
926 &omap2430_mpu_hwmod, 2669 &omap2430_mpu_hwmod,
927 &omap2430_iva_hwmod, 2670 &omap2430_iva_hwmod,
2671
2672 &omap2430_timer1_hwmod,
2673 &omap2430_timer2_hwmod,
2674 &omap2430_timer3_hwmod,
2675 &omap2430_timer4_hwmod,
2676 &omap2430_timer5_hwmod,
2677 &omap2430_timer6_hwmod,
2678 &omap2430_timer7_hwmod,
2679 &omap2430_timer8_hwmod,
2680 &omap2430_timer9_hwmod,
2681 &omap2430_timer10_hwmod,
2682 &omap2430_timer11_hwmod,
2683 &omap2430_timer12_hwmod,
2684
928 &omap2430_wd_timer2_hwmod, 2685 &omap2430_wd_timer2_hwmod,
929 &omap2430_uart1_hwmod, 2686 &omap2430_uart1_hwmod,
930 &omap2430_uart2_hwmod, 2687 &omap2430_uart2_hwmod,
931 &omap2430_uart3_hwmod, 2688 &omap2430_uart3_hwmod,
2689 /* dss class */
2690 &omap2430_dss_core_hwmod,
2691 &omap2430_dss_dispc_hwmod,
2692 &omap2430_dss_rfbi_hwmod,
2693 &omap2430_dss_venc_hwmod,
2694 /* i2c class */
932 &omap2430_i2c1_hwmod, 2695 &omap2430_i2c1_hwmod,
933 &omap2430_i2c2_hwmod, 2696 &omap2430_i2c2_hwmod,
2697 &omap2430_mmc1_hwmod,
2698 &omap2430_mmc2_hwmod,
934 2699
935 /* gpio class */ 2700 /* gpio class */
936 &omap2430_gpio1_hwmod, 2701 &omap2430_gpio1_hwmod,
@@ -941,10 +2706,29 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
941 2706
942 /* dma_system class*/ 2707 /* dma_system class*/
943 &omap2430_dma_system_hwmod, 2708 &omap2430_dma_system_hwmod,
2709
2710 /* mcbsp class */
2711 &omap2430_mcbsp1_hwmod,
2712 &omap2430_mcbsp2_hwmod,
2713 &omap2430_mcbsp3_hwmod,
2714 &omap2430_mcbsp4_hwmod,
2715 &omap2430_mcbsp5_hwmod,
2716
2717 /* mailbox class */
2718 &omap2430_mailbox_hwmod,
2719
2720 /* mcspi class */
2721 &omap2430_mcspi1_hwmod,
2722 &omap2430_mcspi2_hwmod,
2723 &omap2430_mcspi3_hwmod,
2724
2725 /* usbotg class*/
2726 &omap2430_usbhsotg_hwmod,
2727
944 NULL, 2728 NULL,
945}; 2729};
946 2730
947int __init omap2430_hwmod_init(void) 2731int __init omap2430_hwmod_init(void)
948{ 2732{
949 return omap_hwmod_init(omap2430_hwmods); 2733 return omap_hwmod_register(omap2430_hwmods);
950} 2734}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 21:12:53 -0500