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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c841
1 files changed, 109 insertions, 732 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index c4d0ae87d62a..a015c69068f6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
114static struct omap_hwmod omap2420_mcbsp2_hwmod; 114static struct omap_hwmod omap2420_mcbsp2_hwmod;
115 115
116/* l4 core -> mcspi1 interface */ 116/* l4 core -> mcspi1 interface */
117static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
118 {
119 .pa_start = 0x48098000,
120 .pa_end = 0x480980ff,
121 .flags = ADDR_TYPE_RT,
122 },
123};
124
125static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { 117static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
126 .master = &omap2420_l4_core_hwmod, 118 .master = &omap2420_l4_core_hwmod,
127 .slave = &omap2420_mcspi1_hwmod, 119 .slave = &omap2420_mcspi1_hwmod,
128 .clk = "mcspi1_ick", 120 .clk = "mcspi1_ick",
129 .addr = omap2420_mcspi1_addr_space, 121 .addr = omap2_mcspi1_addr_space,
130 .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
131 .user = OCP_USER_MPU | OCP_USER_SDMA, 122 .user = OCP_USER_MPU | OCP_USER_SDMA,
132}; 123};
133 124
134/* l4 core -> mcspi2 interface */ 125/* l4 core -> mcspi2 interface */
135static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
136 {
137 .pa_start = 0x4809a000,
138 .pa_end = 0x4809a0ff,
139 .flags = ADDR_TYPE_RT,
140 },
141};
142
143static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { 126static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
144 .master = &omap2420_l4_core_hwmod, 127 .master = &omap2420_l4_core_hwmod,
145 .slave = &omap2420_mcspi2_hwmod, 128 .slave = &omap2420_mcspi2_hwmod,
146 .clk = "mcspi2_ick", 129 .clk = "mcspi2_ick",
147 .addr = omap2420_mcspi2_addr_space, 130 .addr = omap2_mcspi2_addr_space,
148 .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
149 .user = OCP_USER_MPU | OCP_USER_SDMA, 131 .user = OCP_USER_MPU | OCP_USER_SDMA,
150}; 132};
151 133
@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
157}; 139};
158 140
159/* L4 CORE -> UART1 interface */ 141/* L4 CORE -> UART1 interface */
160static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
161 {
162 .pa_start = OMAP2_UART1_BASE,
163 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
164 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
165 },
166};
167
168static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 142static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
169 .master = &omap2420_l4_core_hwmod, 143 .master = &omap2420_l4_core_hwmod,
170 .slave = &omap2420_uart1_hwmod, 144 .slave = &omap2420_uart1_hwmod,
171 .clk = "uart1_ick", 145 .clk = "uart1_ick",
172 .addr = omap2420_uart1_addr_space, 146 .addr = omap2xxx_uart1_addr_space,
173 .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
174 .user = OCP_USER_MPU | OCP_USER_SDMA, 147 .user = OCP_USER_MPU | OCP_USER_SDMA,
175}; 148};
176 149
177/* L4 CORE -> UART2 interface */ 150/* L4 CORE -> UART2 interface */
178static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
179 {
180 .pa_start = OMAP2_UART2_BASE,
181 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
182 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
183 },
184};
185
186static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 151static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
187 .master = &omap2420_l4_core_hwmod, 152 .master = &omap2420_l4_core_hwmod,
188 .slave = &omap2420_uart2_hwmod, 153 .slave = &omap2420_uart2_hwmod,
189 .clk = "uart2_ick", 154 .clk = "uart2_ick",
190 .addr = omap2420_uart2_addr_space, 155 .addr = omap2xxx_uart2_addr_space,
191 .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
192 .user = OCP_USER_MPU | OCP_USER_SDMA, 156 .user = OCP_USER_MPU | OCP_USER_SDMA,
193}; 157};
194 158
195/* L4 PER -> UART3 interface */ 159/* L4 PER -> UART3 interface */
196static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
197 {
198 .pa_start = OMAP2_UART3_BASE,
199 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
200 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
201 },
202};
203
204static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 160static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
205 .master = &omap2420_l4_core_hwmod, 161 .master = &omap2420_l4_core_hwmod,
206 .slave = &omap2420_uart3_hwmod, 162 .slave = &omap2420_uart3_hwmod,
207 .clk = "uart3_ick", 163 .clk = "uart3_ick",
208 .addr = omap2420_uart3_addr_space, 164 .addr = omap2xxx_uart3_addr_space,
209 .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
210 .user = OCP_USER_MPU | OCP_USER_SDMA, 165 .user = OCP_USER_MPU | OCP_USER_SDMA,
211}; 166};
212 167
213/* I2C IP block address space length (in bytes) */
214#define OMAP2_I2C_AS_LEN 128
215
216/* L4 CORE -> I2C1 interface */ 168/* L4 CORE -> I2C1 interface */
217static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
218 {
219 .pa_start = 0x48070000,
220 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
221 .flags = ADDR_TYPE_RT,
222 },
223};
224
225static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { 169static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
226 .master = &omap2420_l4_core_hwmod, 170 .master = &omap2420_l4_core_hwmod,
227 .slave = &omap2420_i2c1_hwmod, 171 .slave = &omap2420_i2c1_hwmod,
228 .clk = "i2c1_ick", 172 .clk = "i2c1_ick",
229 .addr = omap2420_i2c1_addr_space, 173 .addr = omap2_i2c1_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA, 174 .user = OCP_USER_MPU | OCP_USER_SDMA,
232}; 175};
233 176
234/* L4 CORE -> I2C2 interface */ 177/* L4 CORE -> I2C2 interface */
235static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
236 {
237 .pa_start = 0x48072000,
238 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
239 .flags = ADDR_TYPE_RT,
240 },
241};
242
243static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { 178static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
244 .master = &omap2420_l4_core_hwmod, 179 .master = &omap2420_l4_core_hwmod,
245 .slave = &omap2420_i2c2_hwmod, 180 .slave = &omap2420_i2c2_hwmod,
246 .clk = "i2c2_ick", 181 .clk = "i2c2_ick",
247 .addr = omap2420_i2c2_addr_space, 182 .addr = omap2_i2c2_addr_space,
248 .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
249 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 .user = OCP_USER_MPU | OCP_USER_SDMA,
250}; 184};
251 185
@@ -340,29 +274,8 @@ static struct omap_hwmod omap2420_iva_hwmod = {
340 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
341}; 275};
342 276
343/* Timer Common */
344static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
345 .rev_offs = 0x0000,
346 .sysc_offs = 0x0010,
347 .syss_offs = 0x0014,
348 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
349 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
350 SYSC_HAS_AUTOIDLE),
351 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
352 .sysc_fields = &omap_hwmod_sysc_type1,
353};
354
355static struct omap_hwmod_class omap2420_timer_hwmod_class = {
356 .name = "timer",
357 .sysc = &omap2420_timer_sysc,
358 .rev = OMAP_TIMER_IP_VERSION_1,
359};
360
361/* timer1 */ 277/* timer1 */
362static struct omap_hwmod omap2420_timer1_hwmod; 278static struct omap_hwmod omap2420_timer1_hwmod;
363static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
364 { .irq = 37, },
365};
366 279
367static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { 280static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
368 { 281 {
@@ -370,6 +283,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
370 .pa_end = 0x48028000 + SZ_1K - 1, 283 .pa_end = 0x48028000 + SZ_1K - 1,
371 .flags = ADDR_TYPE_RT 284 .flags = ADDR_TYPE_RT
372 }, 285 },
286 { }
373}; 287};
374 288
375/* l4_wkup -> timer1 */ 289/* l4_wkup -> timer1 */
@@ -378,7 +292,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
378 .slave = &omap2420_timer1_hwmod, 292 .slave = &omap2420_timer1_hwmod,
379 .clk = "gpt1_ick", 293 .clk = "gpt1_ick",
380 .addr = omap2420_timer1_addrs, 294 .addr = omap2420_timer1_addrs,
381 .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
382 .user = OCP_USER_MPU | OCP_USER_SDMA, 295 .user = OCP_USER_MPU | OCP_USER_SDMA,
383}; 296};
384 297
@@ -390,8 +303,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
390/* timer1 hwmod */ 303/* timer1 hwmod */
391static struct omap_hwmod omap2420_timer1_hwmod = { 304static struct omap_hwmod omap2420_timer1_hwmod = {
392 .name = "timer1", 305 .name = "timer1",
393 .mpu_irqs = omap2420_timer1_mpu_irqs, 306 .mpu_irqs = omap2_timer1_mpu_irqs,
394 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
395 .main_clk = "gpt1_fck", 307 .main_clk = "gpt1_fck",
396 .prcm = { 308 .prcm = {
397 .omap2 = { 309 .omap2 = {
@@ -404,31 +316,19 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
404 }, 316 },
405 .slaves = omap2420_timer1_slaves, 317 .slaves = omap2420_timer1_slaves,
406 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), 318 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
407 .class = &omap2420_timer_hwmod_class, 319 .class = &omap2xxx_timer_hwmod_class,
408 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
409}; 321};
410 322
411/* timer2 */ 323/* timer2 */
412static struct omap_hwmod omap2420_timer2_hwmod; 324static struct omap_hwmod omap2420_timer2_hwmod;
413static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
414 { .irq = 38, },
415};
416
417static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
418 {
419 .pa_start = 0x4802a000,
420 .pa_end = 0x4802a000 + SZ_1K - 1,
421 .flags = ADDR_TYPE_RT
422 },
423};
424 325
425/* l4_core -> timer2 */ 326/* l4_core -> timer2 */
426static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { 327static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
427 .master = &omap2420_l4_core_hwmod, 328 .master = &omap2420_l4_core_hwmod,
428 .slave = &omap2420_timer2_hwmod, 329 .slave = &omap2420_timer2_hwmod,
429 .clk = "gpt2_ick", 330 .clk = "gpt2_ick",
430 .addr = omap2420_timer2_addrs, 331 .addr = omap2xxx_timer2_addrs,
431 .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
432 .user = OCP_USER_MPU | OCP_USER_SDMA, 332 .user = OCP_USER_MPU | OCP_USER_SDMA,
433}; 333};
434 334
@@ -440,8 +340,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
440/* timer2 hwmod */ 340/* timer2 hwmod */
441static struct omap_hwmod omap2420_timer2_hwmod = { 341static struct omap_hwmod omap2420_timer2_hwmod = {
442 .name = "timer2", 342 .name = "timer2",
443 .mpu_irqs = omap2420_timer2_mpu_irqs, 343 .mpu_irqs = omap2_timer2_mpu_irqs,
444 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
445 .main_clk = "gpt2_fck", 344 .main_clk = "gpt2_fck",
446 .prcm = { 345 .prcm = {
447 .omap2 = { 346 .omap2 = {
@@ -454,31 +353,19 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
454 }, 353 },
455 .slaves = omap2420_timer2_slaves, 354 .slaves = omap2420_timer2_slaves,
456 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), 355 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
457 .class = &omap2420_timer_hwmod_class, 356 .class = &omap2xxx_timer_hwmod_class,
458 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
459}; 358};
460 359
461/* timer3 */ 360/* timer3 */
462static struct omap_hwmod omap2420_timer3_hwmod; 361static struct omap_hwmod omap2420_timer3_hwmod;
463static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
464 { .irq = 39, },
465};
466
467static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
468 {
469 .pa_start = 0x48078000,
470 .pa_end = 0x48078000 + SZ_1K - 1,
471 .flags = ADDR_TYPE_RT
472 },
473};
474 362
475/* l4_core -> timer3 */ 363/* l4_core -> timer3 */
476static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { 364static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
477 .master = &omap2420_l4_core_hwmod, 365 .master = &omap2420_l4_core_hwmod,
478 .slave = &omap2420_timer3_hwmod, 366 .slave = &omap2420_timer3_hwmod,
479 .clk = "gpt3_ick", 367 .clk = "gpt3_ick",
480 .addr = omap2420_timer3_addrs, 368 .addr = omap2xxx_timer3_addrs,
481 .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
482 .user = OCP_USER_MPU | OCP_USER_SDMA, 369 .user = OCP_USER_MPU | OCP_USER_SDMA,
483}; 370};
484 371
@@ -490,8 +377,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
490/* timer3 hwmod */ 377/* timer3 hwmod */
491static struct omap_hwmod omap2420_timer3_hwmod = { 378static struct omap_hwmod omap2420_timer3_hwmod = {
492 .name = "timer3", 379 .name = "timer3",
493 .mpu_irqs = omap2420_timer3_mpu_irqs, 380 .mpu_irqs = omap2_timer3_mpu_irqs,
494 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
495 .main_clk = "gpt3_fck", 381 .main_clk = "gpt3_fck",
496 .prcm = { 382 .prcm = {
497 .omap2 = { 383 .omap2 = {
@@ -504,31 +390,19 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
504 }, 390 },
505 .slaves = omap2420_timer3_slaves, 391 .slaves = omap2420_timer3_slaves,
506 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 392 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
507 .class = &omap2420_timer_hwmod_class, 393 .class = &omap2xxx_timer_hwmod_class,
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
509}; 395};
510 396
511/* timer4 */ 397/* timer4 */
512static struct omap_hwmod omap2420_timer4_hwmod; 398static struct omap_hwmod omap2420_timer4_hwmod;
513static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
514 { .irq = 40, },
515};
516
517static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
518 {
519 .pa_start = 0x4807a000,
520 .pa_end = 0x4807a000 + SZ_1K - 1,
521 .flags = ADDR_TYPE_RT
522 },
523};
524 399
525/* l4_core -> timer4 */ 400/* l4_core -> timer4 */
526static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { 401static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
527 .master = &omap2420_l4_core_hwmod, 402 .master = &omap2420_l4_core_hwmod,
528 .slave = &omap2420_timer4_hwmod, 403 .slave = &omap2420_timer4_hwmod,
529 .clk = "gpt4_ick", 404 .clk = "gpt4_ick",
530 .addr = omap2420_timer4_addrs, 405 .addr = omap2xxx_timer4_addrs,
531 .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
532 .user = OCP_USER_MPU | OCP_USER_SDMA, 406 .user = OCP_USER_MPU | OCP_USER_SDMA,
533}; 407};
534 408
@@ -540,8 +414,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
540/* timer4 hwmod */ 414/* timer4 hwmod */
541static struct omap_hwmod omap2420_timer4_hwmod = { 415static struct omap_hwmod omap2420_timer4_hwmod = {
542 .name = "timer4", 416 .name = "timer4",
543 .mpu_irqs = omap2420_timer4_mpu_irqs, 417 .mpu_irqs = omap2_timer4_mpu_irqs,
544 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
545 .main_clk = "gpt4_fck", 418 .main_clk = "gpt4_fck",
546 .prcm = { 419 .prcm = {
547 .omap2 = { 420 .omap2 = {
@@ -554,31 +427,19 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
554 }, 427 },
555 .slaves = omap2420_timer4_slaves, 428 .slaves = omap2420_timer4_slaves,
556 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), 429 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
557 .class = &omap2420_timer_hwmod_class, 430 .class = &omap2xxx_timer_hwmod_class,
558 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
559}; 432};
560 433
561/* timer5 */ 434/* timer5 */
562static struct omap_hwmod omap2420_timer5_hwmod; 435static struct omap_hwmod omap2420_timer5_hwmod;
563static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
564 { .irq = 41, },
565};
566
567static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
568 {
569 .pa_start = 0x4807c000,
570 .pa_end = 0x4807c000 + SZ_1K - 1,
571 .flags = ADDR_TYPE_RT
572 },
573};
574 436
575/* l4_core -> timer5 */ 437/* l4_core -> timer5 */
576static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { 438static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
577 .master = &omap2420_l4_core_hwmod, 439 .master = &omap2420_l4_core_hwmod,
578 .slave = &omap2420_timer5_hwmod, 440 .slave = &omap2420_timer5_hwmod,
579 .clk = "gpt5_ick", 441 .clk = "gpt5_ick",
580 .addr = omap2420_timer5_addrs, 442 .addr = omap2xxx_timer5_addrs,
581 .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
582 .user = OCP_USER_MPU | OCP_USER_SDMA, 443 .user = OCP_USER_MPU | OCP_USER_SDMA,
583}; 444};
584 445
@@ -590,8 +451,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
590/* timer5 hwmod */ 451/* timer5 hwmod */
591static struct omap_hwmod omap2420_timer5_hwmod = { 452static struct omap_hwmod omap2420_timer5_hwmod = {
592 .name = "timer5", 453 .name = "timer5",
593 .mpu_irqs = omap2420_timer5_mpu_irqs, 454 .mpu_irqs = omap2_timer5_mpu_irqs,
594 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
595 .main_clk = "gpt5_fck", 455 .main_clk = "gpt5_fck",
596 .prcm = { 456 .prcm = {
597 .omap2 = { 457 .omap2 = {
@@ -604,32 +464,20 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
604 }, 464 },
605 .slaves = omap2420_timer5_slaves, 465 .slaves = omap2420_timer5_slaves,
606 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), 466 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
607 .class = &omap2420_timer_hwmod_class, 467 .class = &omap2xxx_timer_hwmod_class,
608 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 468 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
609}; 469};
610 470
611 471
612/* timer6 */ 472/* timer6 */
613static struct omap_hwmod omap2420_timer6_hwmod; 473static struct omap_hwmod omap2420_timer6_hwmod;
614static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
615 { .irq = 42, },
616};
617
618static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
619 {
620 .pa_start = 0x4807e000,
621 .pa_end = 0x4807e000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625 474
626/* l4_core -> timer6 */ 475/* l4_core -> timer6 */
627static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { 476static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
628 .master = &omap2420_l4_core_hwmod, 477 .master = &omap2420_l4_core_hwmod,
629 .slave = &omap2420_timer6_hwmod, 478 .slave = &omap2420_timer6_hwmod,
630 .clk = "gpt6_ick", 479 .clk = "gpt6_ick",
631 .addr = omap2420_timer6_addrs, 480 .addr = omap2xxx_timer6_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 481 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 482};
635 483
@@ -641,8 +489,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
641/* timer6 hwmod */ 489/* timer6 hwmod */
642static struct omap_hwmod omap2420_timer6_hwmod = { 490static struct omap_hwmod omap2420_timer6_hwmod = {
643 .name = "timer6", 491 .name = "timer6",
644 .mpu_irqs = omap2420_timer6_mpu_irqs, 492 .mpu_irqs = omap2_timer6_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
646 .main_clk = "gpt6_fck", 493 .main_clk = "gpt6_fck",
647 .prcm = { 494 .prcm = {
648 .omap2 = { 495 .omap2 = {
@@ -655,31 +502,19 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
655 }, 502 },
656 .slaves = omap2420_timer6_slaves, 503 .slaves = omap2420_timer6_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), 504 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
658 .class = &omap2420_timer_hwmod_class, 505 .class = &omap2xxx_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
660}; 507};
661 508
662/* timer7 */ 509/* timer7 */
663static struct omap_hwmod omap2420_timer7_hwmod; 510static struct omap_hwmod omap2420_timer7_hwmod;
664static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
665 { .irq = 43, },
666};
667
668static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
669 {
670 .pa_start = 0x48080000,
671 .pa_end = 0x48080000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675 511
676/* l4_core -> timer7 */ 512/* l4_core -> timer7 */
677static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { 513static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
678 .master = &omap2420_l4_core_hwmod, 514 .master = &omap2420_l4_core_hwmod,
679 .slave = &omap2420_timer7_hwmod, 515 .slave = &omap2420_timer7_hwmod,
680 .clk = "gpt7_ick", 516 .clk = "gpt7_ick",
681 .addr = omap2420_timer7_addrs, 517 .addr = omap2xxx_timer7_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 518 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 519};
685 520
@@ -691,8 +526,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
691/* timer7 hwmod */ 526/* timer7 hwmod */
692static struct omap_hwmod omap2420_timer7_hwmod = { 527static struct omap_hwmod omap2420_timer7_hwmod = {
693 .name = "timer7", 528 .name = "timer7",
694 .mpu_irqs = omap2420_timer7_mpu_irqs, 529 .mpu_irqs = omap2_timer7_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
696 .main_clk = "gpt7_fck", 530 .main_clk = "gpt7_fck",
697 .prcm = { 531 .prcm = {
698 .omap2 = { 532 .omap2 = {
@@ -705,31 +539,19 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
705 }, 539 },
706 .slaves = omap2420_timer7_slaves, 540 .slaves = omap2420_timer7_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), 541 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
708 .class = &omap2420_timer_hwmod_class, 542 .class = &omap2xxx_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 543 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
710}; 544};
711 545
712/* timer8 */ 546/* timer8 */
713static struct omap_hwmod omap2420_timer8_hwmod; 547static struct omap_hwmod omap2420_timer8_hwmod;
714static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
715 { .irq = 44, },
716};
717
718static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
719 {
720 .pa_start = 0x48082000,
721 .pa_end = 0x48082000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725 548
726/* l4_core -> timer8 */ 549/* l4_core -> timer8 */
727static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { 550static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
728 .master = &omap2420_l4_core_hwmod, 551 .master = &omap2420_l4_core_hwmod,
729 .slave = &omap2420_timer8_hwmod, 552 .slave = &omap2420_timer8_hwmod,
730 .clk = "gpt8_ick", 553 .clk = "gpt8_ick",
731 .addr = omap2420_timer8_addrs, 554 .addr = omap2xxx_timer8_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 555 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 556};
735 557
@@ -741,8 +563,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
741/* timer8 hwmod */ 563/* timer8 hwmod */
742static struct omap_hwmod omap2420_timer8_hwmod = { 564static struct omap_hwmod omap2420_timer8_hwmod = {
743 .name = "timer8", 565 .name = "timer8",
744 .mpu_irqs = omap2420_timer8_mpu_irqs, 566 .mpu_irqs = omap2_timer8_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
746 .main_clk = "gpt8_fck", 567 .main_clk = "gpt8_fck",
747 .prcm = { 568 .prcm = {
748 .omap2 = { 569 .omap2 = {
@@ -755,31 +576,19 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
755 }, 576 },
756 .slaves = omap2420_timer8_slaves, 577 .slaves = omap2420_timer8_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), 578 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
758 .class = &omap2420_timer_hwmod_class, 579 .class = &omap2xxx_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
760}; 581};
761 582
762/* timer9 */ 583/* timer9 */
763static struct omap_hwmod omap2420_timer9_hwmod; 584static struct omap_hwmod omap2420_timer9_hwmod;
764static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
765 { .irq = 45, },
766};
767
768static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
769 {
770 .pa_start = 0x48084000,
771 .pa_end = 0x48084000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775 585
776/* l4_core -> timer9 */ 586/* l4_core -> timer9 */
777static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { 587static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
778 .master = &omap2420_l4_core_hwmod, 588 .master = &omap2420_l4_core_hwmod,
779 .slave = &omap2420_timer9_hwmod, 589 .slave = &omap2420_timer9_hwmod,
780 .clk = "gpt9_ick", 590 .clk = "gpt9_ick",
781 .addr = omap2420_timer9_addrs, 591 .addr = omap2xxx_timer9_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 592 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 593};
785 594
@@ -791,8 +600,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
791/* timer9 hwmod */ 600/* timer9 hwmod */
792static struct omap_hwmod omap2420_timer9_hwmod = { 601static struct omap_hwmod omap2420_timer9_hwmod = {
793 .name = "timer9", 602 .name = "timer9",
794 .mpu_irqs = omap2420_timer9_mpu_irqs, 603 .mpu_irqs = omap2_timer9_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
796 .main_clk = "gpt9_fck", 604 .main_clk = "gpt9_fck",
797 .prcm = { 605 .prcm = {
798 .omap2 = { 606 .omap2 = {
@@ -805,31 +613,19 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
805 }, 613 },
806 .slaves = omap2420_timer9_slaves, 614 .slaves = omap2420_timer9_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), 615 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
808 .class = &omap2420_timer_hwmod_class, 616 .class = &omap2xxx_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
810}; 618};
811 619
812/* timer10 */ 620/* timer10 */
813static struct omap_hwmod omap2420_timer10_hwmod; 621static struct omap_hwmod omap2420_timer10_hwmod;
814static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
815 { .irq = 46, },
816};
817
818static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
819 {
820 .pa_start = 0x48086000,
821 .pa_end = 0x48086000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825 622
826/* l4_core -> timer10 */ 623/* l4_core -> timer10 */
827static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { 624static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
828 .master = &omap2420_l4_core_hwmod, 625 .master = &omap2420_l4_core_hwmod,
829 .slave = &omap2420_timer10_hwmod, 626 .slave = &omap2420_timer10_hwmod,
830 .clk = "gpt10_ick", 627 .clk = "gpt10_ick",
831 .addr = omap2420_timer10_addrs, 628 .addr = omap2_timer10_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 629 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 630};
835 631
@@ -841,8 +637,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
841/* timer10 hwmod */ 637/* timer10 hwmod */
842static struct omap_hwmod omap2420_timer10_hwmod = { 638static struct omap_hwmod omap2420_timer10_hwmod = {
843 .name = "timer10", 639 .name = "timer10",
844 .mpu_irqs = omap2420_timer10_mpu_irqs, 640 .mpu_irqs = omap2_timer10_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
846 .main_clk = "gpt10_fck", 641 .main_clk = "gpt10_fck",
847 .prcm = { 642 .prcm = {
848 .omap2 = { 643 .omap2 = {
@@ -855,31 +650,19 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
855 }, 650 },
856 .slaves = omap2420_timer10_slaves, 651 .slaves = omap2420_timer10_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), 652 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
858 .class = &omap2420_timer_hwmod_class, 653 .class = &omap2xxx_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 654 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
860}; 655};
861 656
862/* timer11 */ 657/* timer11 */
863static struct omap_hwmod omap2420_timer11_hwmod; 658static struct omap_hwmod omap2420_timer11_hwmod;
864static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
865 { .irq = 47, },
866};
867
868static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
869 {
870 .pa_start = 0x48088000,
871 .pa_end = 0x48088000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875 659
876/* l4_core -> timer11 */ 660/* l4_core -> timer11 */
877static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { 661static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
878 .master = &omap2420_l4_core_hwmod, 662 .master = &omap2420_l4_core_hwmod,
879 .slave = &omap2420_timer11_hwmod, 663 .slave = &omap2420_timer11_hwmod,
880 .clk = "gpt11_ick", 664 .clk = "gpt11_ick",
881 .addr = omap2420_timer11_addrs, 665 .addr = omap2_timer11_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 666 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 667};
885 668
@@ -891,8 +674,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
891/* timer11 hwmod */ 674/* timer11 hwmod */
892static struct omap_hwmod omap2420_timer11_hwmod = { 675static struct omap_hwmod omap2420_timer11_hwmod = {
893 .name = "timer11", 676 .name = "timer11",
894 .mpu_irqs = omap2420_timer11_mpu_irqs, 677 .mpu_irqs = omap2_timer11_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
896 .main_clk = "gpt11_fck", 678 .main_clk = "gpt11_fck",
897 .prcm = { 679 .prcm = {
898 .omap2 = { 680 .omap2 = {
@@ -905,31 +687,19 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
905 }, 687 },
906 .slaves = omap2420_timer11_slaves, 688 .slaves = omap2420_timer11_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), 689 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
908 .class = &omap2420_timer_hwmod_class, 690 .class = &omap2xxx_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
910}; 692};
911 693
912/* timer12 */ 694/* timer12 */
913static struct omap_hwmod omap2420_timer12_hwmod; 695static struct omap_hwmod omap2420_timer12_hwmod;
914static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
915 { .irq = 48, },
916};
917
918static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
919 {
920 .pa_start = 0x4808a000,
921 .pa_end = 0x4808a000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925 696
926/* l4_core -> timer12 */ 697/* l4_core -> timer12 */
927static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { 698static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
928 .master = &omap2420_l4_core_hwmod, 699 .master = &omap2420_l4_core_hwmod,
929 .slave = &omap2420_timer12_hwmod, 700 .slave = &omap2420_timer12_hwmod,
930 .clk = "gpt12_ick", 701 .clk = "gpt12_ick",
931 .addr = omap2420_timer12_addrs, 702 .addr = omap2xxx_timer12_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 703 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 704};
935 705
@@ -941,8 +711,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
941/* timer12 hwmod */ 711/* timer12 hwmod */
942static struct omap_hwmod omap2420_timer12_hwmod = { 712static struct omap_hwmod omap2420_timer12_hwmod = {
943 .name = "timer12", 713 .name = "timer12",
944 .mpu_irqs = omap2420_timer12_mpu_irqs, 714 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
946 .main_clk = "gpt12_fck", 715 .main_clk = "gpt12_fck",
947 .prcm = { 716 .prcm = {
948 .omap2 = { 717 .omap2 = {
@@ -955,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
955 }, 724 },
956 .slaves = omap2420_timer12_slaves, 725 .slaves = omap2420_timer12_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), 726 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
958 .class = &omap2420_timer_hwmod_class, 727 .class = &omap2xxx_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
960}; 729};
961 730
@@ -966,6 +735,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
966 .pa_end = 0x4802207f, 735 .pa_end = 0x4802207f,
967 .flags = ADDR_TYPE_RT 736 .flags = ADDR_TYPE_RT
968 }, 737 },
738 { }
969}; 739};
970 740
971static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 741static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
@@ -973,31 +743,9 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
973 .slave = &omap2420_wd_timer2_hwmod, 743 .slave = &omap2420_wd_timer2_hwmod,
974 .clk = "mpu_wdt_ick", 744 .clk = "mpu_wdt_ick",
975 .addr = omap2420_wd_timer2_addrs, 745 .addr = omap2420_wd_timer2_addrs,
976 .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
977 .user = OCP_USER_MPU | OCP_USER_SDMA, 746 .user = OCP_USER_MPU | OCP_USER_SDMA,
978}; 747};
979 748
980/*
981 * 'wd_timer' class
982 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
983 * overflow condition
984 */
985
986static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
987 .rev_offs = 0x0000,
988 .sysc_offs = 0x0010,
989 .syss_offs = 0x0014,
990 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
991 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
992 .sysc_fields = &omap_hwmod_sysc_type1,
993};
994
995static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
996 .name = "wd_timer",
997 .sysc = &omap2420_wd_timer_sysc,
998 .pre_shutdown = &omap2_wd_timer_disable
999};
1000
1001/* wd_timer2 */ 749/* wd_timer2 */
1002static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { 750static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1003 &omap2420_l4_wkup__wd_timer2, 751 &omap2420_l4_wkup__wd_timer2,
@@ -1005,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1005 753
1006static struct omap_hwmod omap2420_wd_timer2_hwmod = { 754static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1007 .name = "wd_timer2", 755 .name = "wd_timer2",
1008 .class = &omap2420_wd_timer_hwmod_class, 756 .class = &omap2xxx_wd_timer_hwmod_class,
1009 .main_clk = "mpu_wdt_fck", 757 .main_clk = "mpu_wdt_fck",
1010 .prcm = { 758 .prcm = {
1011 .omap2 = { 759 .omap2 = {
@@ -1021,45 +769,16 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1022}; 770};
1023 771
1024/* UART */
1025
1026static struct omap_hwmod_class_sysconfig uart_sysc = {
1027 .rev_offs = 0x50,
1028 .sysc_offs = 0x54,
1029 .syss_offs = 0x58,
1030 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1032 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1034 .sysc_fields = &omap_hwmod_sysc_type1,
1035};
1036
1037static struct omap_hwmod_class uart_class = {
1038 .name = "uart",
1039 .sysc = &uart_sysc,
1040};
1041
1042/* UART1 */ 772/* UART1 */
1043 773
1044static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1045 { .irq = INT_24XX_UART1_IRQ, },
1046};
1047
1048static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1049 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1050 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1051};
1052
1053static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { 774static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
1054 &omap2_l4_core__uart1, 775 &omap2_l4_core__uart1,
1055}; 776};
1056 777
1057static struct omap_hwmod omap2420_uart1_hwmod = { 778static struct omap_hwmod omap2420_uart1_hwmod = {
1058 .name = "uart1", 779 .name = "uart1",
1059 .mpu_irqs = uart1_mpu_irqs, 780 .mpu_irqs = omap2_uart1_mpu_irqs,
1060 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 781 .sdma_reqs = omap2_uart1_sdma_reqs,
1061 .sdma_reqs = uart1_sdma_reqs,
1062 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1063 .main_clk = "uart1_fck", 782 .main_clk = "uart1_fck",
1064 .prcm = { 783 .prcm = {
1065 .omap2 = { 784 .omap2 = {
@@ -1072,31 +791,20 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
1072 }, 791 },
1073 .slaves = omap2420_uart1_slaves, 792 .slaves = omap2420_uart1_slaves,
1074 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), 793 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
1075 .class = &uart_class, 794 .class = &omap2_uart_class,
1076 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 795 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1077}; 796};
1078 797
1079/* UART2 */ 798/* UART2 */
1080 799
1081static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1082 { .irq = INT_24XX_UART2_IRQ, },
1083};
1084
1085static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1086 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1087 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1088};
1089
1090static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { 800static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
1091 &omap2_l4_core__uart2, 801 &omap2_l4_core__uart2,
1092}; 802};
1093 803
1094static struct omap_hwmod omap2420_uart2_hwmod = { 804static struct omap_hwmod omap2420_uart2_hwmod = {
1095 .name = "uart2", 805 .name = "uart2",
1096 .mpu_irqs = uart2_mpu_irqs, 806 .mpu_irqs = omap2_uart2_mpu_irqs,
1097 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 807 .sdma_reqs = omap2_uart2_sdma_reqs,
1098 .sdma_reqs = uart2_sdma_reqs,
1099 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1100 .main_clk = "uart2_fck", 808 .main_clk = "uart2_fck",
1101 .prcm = { 809 .prcm = {
1102 .omap2 = { 810 .omap2 = {
@@ -1109,31 +817,20 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
1109 }, 817 },
1110 .slaves = omap2420_uart2_slaves, 818 .slaves = omap2420_uart2_slaves,
1111 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), 819 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
1112 .class = &uart_class, 820 .class = &omap2_uart_class,
1113 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 821 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1114}; 822};
1115 823
1116/* UART3 */ 824/* UART3 */
1117 825
1118static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1119 { .irq = INT_24XX_UART3_IRQ, },
1120};
1121
1122static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1123 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1124 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1125};
1126
1127static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { 826static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
1128 &omap2_l4_core__uart3, 827 &omap2_l4_core__uart3,
1129}; 828};
1130 829
1131static struct omap_hwmod omap2420_uart3_hwmod = { 830static struct omap_hwmod omap2420_uart3_hwmod = {
1132 .name = "uart3", 831 .name = "uart3",
1133 .mpu_irqs = uart3_mpu_irqs, 832 .mpu_irqs = omap2_uart3_mpu_irqs,
1134 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 833 .sdma_reqs = omap2_uart3_sdma_reqs,
1135 .sdma_reqs = uart3_sdma_reqs,
1136 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1137 .main_clk = "uart3_fck", 834 .main_clk = "uart3_fck",
1138 .prcm = { 835 .prcm = {
1139 .omap2 = { 836 .omap2 = {
@@ -1146,53 +843,22 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
1146 }, 843 },
1147 .slaves = omap2420_uart3_slaves, 844 .slaves = omap2420_uart3_slaves,
1148 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), 845 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
1149 .class = &uart_class, 846 .class = &omap2_uart_class,
1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1151}; 848};
1152 849
1153/*
1154 * 'dss' class
1155 * display sub-system
1156 */
1157
1158static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
1159 .rev_offs = 0x0000,
1160 .sysc_offs = 0x0010,
1161 .syss_offs = 0x0014,
1162 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1163 .sysc_fields = &omap_hwmod_sysc_type1,
1164};
1165
1166static struct omap_hwmod_class omap2420_dss_hwmod_class = {
1167 .name = "dss",
1168 .sysc = &omap2420_dss_sysc,
1169};
1170
1171static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
1172 { .name = "dispc", .dma_req = 5 },
1173};
1174
1175/* dss */ 850/* dss */
1176/* dss master ports */ 851/* dss master ports */
1177static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { 852static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
1178 &omap2420_dss__l3, 853 &omap2420_dss__l3,
1179}; 854};
1180 855
1181static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
1182 {
1183 .pa_start = 0x48050000,
1184 .pa_end = 0x480503FF,
1185 .flags = ADDR_TYPE_RT
1186 },
1187};
1188
1189/* l4_core -> dss */ 856/* l4_core -> dss */
1190static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { 857static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
1191 .master = &omap2420_l4_core_hwmod, 858 .master = &omap2420_l4_core_hwmod,
1192 .slave = &omap2420_dss_core_hwmod, 859 .slave = &omap2420_dss_core_hwmod,
1193 .clk = "dss_ick", 860 .clk = "dss_ick",
1194 .addr = omap2420_dss_addrs, 861 .addr = omap2_dss_addrs,
1195 .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
1196 .fw = { 862 .fw = {
1197 .omap2 = { 863 .omap2 = {
1198 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 864 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1214,10 +880,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1214 880
1215static struct omap_hwmod omap2420_dss_core_hwmod = { 881static struct omap_hwmod omap2420_dss_core_hwmod = {
1216 .name = "dss_core", 882 .name = "dss_core",
1217 .class = &omap2420_dss_hwmod_class, 883 .class = &omap2_dss_hwmod_class,
1218 .main_clk = "dss1_fck", /* instead of dss_fck */ 884 .main_clk = "dss1_fck", /* instead of dss_fck */
1219 .sdma_reqs = omap2420_dss_sdma_chs, 885 .sdma_reqs = omap2xxx_dss_sdma_chs,
1220 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
1221 .prcm = { 886 .prcm = {
1222 .omap2 = { 887 .omap2 = {
1223 .prcm_reg_id = 1, 888 .prcm_reg_id = 1,
@@ -1237,46 +902,12 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
1237 .flags = HWMOD_NO_IDLEST, 902 .flags = HWMOD_NO_IDLEST,
1238}; 903};
1239 904
1240/*
1241 * 'dispc' class
1242 * display controller
1243 */
1244
1245static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
1246 .rev_offs = 0x0000,
1247 .sysc_offs = 0x0010,
1248 .syss_offs = 0x0014,
1249 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1250 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1252 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1253 .sysc_fields = &omap_hwmod_sysc_type1,
1254};
1255
1256static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
1257 .name = "dispc",
1258 .sysc = &omap2420_dispc_sysc,
1259};
1260
1261static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
1262 { .irq = 25 },
1263};
1264
1265static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
1266 {
1267 .pa_start = 0x48050400,
1268 .pa_end = 0x480507FF,
1269 .flags = ADDR_TYPE_RT
1270 },
1271};
1272
1273/* l4_core -> dss_dispc */ 905/* l4_core -> dss_dispc */
1274static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { 906static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1275 .master = &omap2420_l4_core_hwmod, 907 .master = &omap2420_l4_core_hwmod,
1276 .slave = &omap2420_dss_dispc_hwmod, 908 .slave = &omap2420_dss_dispc_hwmod,
1277 .clk = "dss_ick", 909 .clk = "dss_ick",
1278 .addr = omap2420_dss_dispc_addrs, 910 .addr = omap2_dss_dispc_addrs,
1279 .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
1280 .fw = { 911 .fw = {
1281 .omap2 = { 912 .omap2 = {
1282 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 913 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1293,9 +924,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1293 924
1294static struct omap_hwmod omap2420_dss_dispc_hwmod = { 925static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1295 .name = "dss_dispc", 926 .name = "dss_dispc",
1296 .class = &omap2420_dispc_hwmod_class, 927 .class = &omap2_dispc_hwmod_class,
1297 .mpu_irqs = omap2420_dispc_irqs, 928 .mpu_irqs = omap2_dispc_irqs,
1298 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
1299 .main_clk = "dss1_fck", 929 .main_clk = "dss1_fck",
1300 .prcm = { 930 .prcm = {
1301 .omap2 = { 931 .omap2 = {
@@ -1312,41 +942,12 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1312 .flags = HWMOD_NO_IDLEST, 942 .flags = HWMOD_NO_IDLEST,
1313}; 943};
1314 944
1315/*
1316 * 'rfbi' class
1317 * remote frame buffer interface
1318 */
1319
1320static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1321 .rev_offs = 0x0000,
1322 .sysc_offs = 0x0010,
1323 .syss_offs = 0x0014,
1324 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1325 SYSC_HAS_AUTOIDLE),
1326 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1327 .sysc_fields = &omap_hwmod_sysc_type1,
1328};
1329
1330static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1331 .name = "rfbi",
1332 .sysc = &omap2420_rfbi_sysc,
1333};
1334
1335static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
1336 {
1337 .pa_start = 0x48050800,
1338 .pa_end = 0x48050BFF,
1339 .flags = ADDR_TYPE_RT
1340 },
1341};
1342
1343/* l4_core -> dss_rfbi */ 945/* l4_core -> dss_rfbi */
1344static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { 946static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1345 .master = &omap2420_l4_core_hwmod, 947 .master = &omap2420_l4_core_hwmod,
1346 .slave = &omap2420_dss_rfbi_hwmod, 948 .slave = &omap2420_dss_rfbi_hwmod,
1347 .clk = "dss_ick", 949 .clk = "dss_ick",
1348 .addr = omap2420_dss_rfbi_addrs, 950 .addr = omap2_dss_rfbi_addrs,
1349 .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
1350 .fw = { 951 .fw = {
1351 .omap2 = { 952 .omap2 = {
1352 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 953 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1363,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1363 964
1364static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 965static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1365 .name = "dss_rfbi", 966 .name = "dss_rfbi",
1366 .class = &omap2420_rfbi_hwmod_class, 967 .class = &omap2_rfbi_hwmod_class,
1367 .main_clk = "dss1_fck", 968 .main_clk = "dss1_fck",
1368 .prcm = { 969 .prcm = {
1369 .omap2 = { 970 .omap2 = {
@@ -1378,31 +979,12 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1378 .flags = HWMOD_NO_IDLEST, 979 .flags = HWMOD_NO_IDLEST,
1379}; 980};
1380 981
1381/*
1382 * 'venc' class
1383 * video encoder
1384 */
1385
1386static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1387 .name = "venc",
1388};
1389
1390/* dss_venc */
1391static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
1392 {
1393 .pa_start = 0x48050C00,
1394 .pa_end = 0x48050FFF,
1395 .flags = ADDR_TYPE_RT
1396 },
1397};
1398
1399/* l4_core -> dss_venc */ 982/* l4_core -> dss_venc */
1400static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 983static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1401 .master = &omap2420_l4_core_hwmod, 984 .master = &omap2420_l4_core_hwmod,
1402 .slave = &omap2420_dss_venc_hwmod, 985 .slave = &omap2420_dss_venc_hwmod,
1403 .clk = "dss_54m_fck", 986 .clk = "dss_54m_fck",
1404 .addr = omap2420_dss_venc_addrs, 987 .addr = omap2_dss_venc_addrs,
1405 .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
1406 .fw = { 988 .fw = {
1407 .omap2 = { 989 .omap2 = {
1408 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 990 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
@@ -1420,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1420 1002
1421static struct omap_hwmod omap2420_dss_venc_hwmod = { 1003static struct omap_hwmod omap2420_dss_venc_hwmod = {
1422 .name = "dss_venc", 1004 .name = "dss_venc",
1423 .class = &omap2420_venc_hwmod_class, 1005 .class = &omap2_venc_hwmod_class,
1424 .main_clk = "dss1_fck", 1006 .main_clk = "dss1_fck",
1425 .prcm = { 1007 .prcm = {
1426 .omap2 = { 1008 .omap2 = {
@@ -1447,20 +1029,18 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
1447static struct omap_hwmod_class i2c_class = { 1029static struct omap_hwmod_class i2c_class = {
1448 .name = "i2c", 1030 .name = "i2c",
1449 .sysc = &i2c_sysc, 1031 .sysc = &i2c_sysc,
1032 .rev = OMAP_I2C_IP_VERSION_1,
1033 .reset = &omap_i2c_reset,
1450}; 1034};
1451 1035
1452static struct omap_i2c_dev_attr i2c_dev_attr; 1036static struct omap_i2c_dev_attr i2c_dev_attr = {
1453 1037 .flags = OMAP_I2C_FLAG_NO_FIFO |
1454/* I2C1 */ 1038 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1455 1039 OMAP_I2C_FLAG_16BIT_DATA_REG |
1456static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { 1040 OMAP_I2C_FLAG_BUS_SHIFT_2,
1457 { .irq = INT_24XX_I2C1_IRQ, },
1458}; 1041};
1459 1042
1460static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { 1043/* I2C1 */
1461 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1462 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1463};
1464 1044
1465static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { 1045static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1466 &omap2420_l4_core__i2c1, 1046 &omap2420_l4_core__i2c1,
@@ -1468,10 +1048,8 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1468 1048
1469static struct omap_hwmod omap2420_i2c1_hwmod = { 1049static struct omap_hwmod omap2420_i2c1_hwmod = {
1470 .name = "i2c1", 1050 .name = "i2c1",
1471 .mpu_irqs = i2c1_mpu_irqs, 1051 .mpu_irqs = omap2_i2c1_mpu_irqs,
1472 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1052 .sdma_reqs = omap2_i2c1_sdma_reqs,
1473 .sdma_reqs = i2c1_sdma_reqs,
1474 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1475 .main_clk = "i2c1_fck", 1053 .main_clk = "i2c1_fck",
1476 .prcm = { 1054 .prcm = {
1477 .omap2 = { 1055 .omap2 = {
@@ -1492,25 +1070,14 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
1492 1070
1493/* I2C2 */ 1071/* I2C2 */
1494 1072
1495static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1496 { .irq = INT_24XX_I2C2_IRQ, },
1497};
1498
1499static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1500 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1501 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1502};
1503
1504static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { 1073static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1505 &omap2420_l4_core__i2c2, 1074 &omap2420_l4_core__i2c2,
1506}; 1075};
1507 1076
1508static struct omap_hwmod omap2420_i2c2_hwmod = { 1077static struct omap_hwmod omap2420_i2c2_hwmod = {
1509 .name = "i2c2", 1078 .name = "i2c2",
1510 .mpu_irqs = i2c2_mpu_irqs, 1079 .mpu_irqs = omap2_i2c2_mpu_irqs,
1511 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1080 .sdma_reqs = omap2_i2c2_sdma_reqs,
1512 .sdma_reqs = i2c2_sdma_reqs,
1513 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1514 .main_clk = "i2c2_fck", 1081 .main_clk = "i2c2_fck",
1515 .prcm = { 1082 .prcm = {
1516 .omap2 = { 1083 .omap2 = {
@@ -1536,6 +1103,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1536 .pa_end = 0x480181ff, 1103 .pa_end = 0x480181ff,
1537 .flags = ADDR_TYPE_RT 1104 .flags = ADDR_TYPE_RT
1538 }, 1105 },
1106 { }
1539}; 1107};
1540 1108
1541static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 1109static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
@@ -1543,7 +1111,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1543 .slave = &omap2420_gpio1_hwmod, 1111 .slave = &omap2420_gpio1_hwmod,
1544 .clk = "gpios_ick", 1112 .clk = "gpios_ick",
1545 .addr = omap2420_gpio1_addr_space, 1113 .addr = omap2420_gpio1_addr_space,
1546 .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
1547 .user = OCP_USER_MPU | OCP_USER_SDMA, 1114 .user = OCP_USER_MPU | OCP_USER_SDMA,
1548}; 1115};
1549 1116
@@ -1554,6 +1121,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1554 .pa_end = 0x4801a1ff, 1121 .pa_end = 0x4801a1ff,
1555 .flags = ADDR_TYPE_RT 1122 .flags = ADDR_TYPE_RT
1556 }, 1123 },
1124 { }
1557}; 1125};
1558 1126
1559static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 1127static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
@@ -1561,7 +1129,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1561 .slave = &omap2420_gpio2_hwmod, 1129 .slave = &omap2420_gpio2_hwmod,
1562 .clk = "gpios_ick", 1130 .clk = "gpios_ick",
1563 .addr = omap2420_gpio2_addr_space, 1131 .addr = omap2420_gpio2_addr_space,
1564 .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
1565 .user = OCP_USER_MPU | OCP_USER_SDMA, 1132 .user = OCP_USER_MPU | OCP_USER_SDMA,
1566}; 1133};
1567 1134
@@ -1572,6 +1139,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1572 .pa_end = 0x4801c1ff, 1139 .pa_end = 0x4801c1ff,
1573 .flags = ADDR_TYPE_RT 1140 .flags = ADDR_TYPE_RT
1574 }, 1141 },
1142 { }
1575}; 1143};
1576 1144
1577static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 1145static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
@@ -1579,7 +1147,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1579 .slave = &omap2420_gpio3_hwmod, 1147 .slave = &omap2420_gpio3_hwmod,
1580 .clk = "gpios_ick", 1148 .clk = "gpios_ick",
1581 .addr = omap2420_gpio3_addr_space, 1149 .addr = omap2420_gpio3_addr_space,
1582 .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
1583 .user = OCP_USER_MPU | OCP_USER_SDMA, 1150 .user = OCP_USER_MPU | OCP_USER_SDMA,
1584}; 1151};
1585 1152
@@ -1590,6 +1157,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1590 .pa_end = 0x4801e1ff, 1157 .pa_end = 0x4801e1ff,
1591 .flags = ADDR_TYPE_RT 1158 .flags = ADDR_TYPE_RT
1592 }, 1159 },
1160 { }
1593}; 1161};
1594 1162
1595static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 1163static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
@@ -1597,7 +1165,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1597 .slave = &omap2420_gpio4_hwmod, 1165 .slave = &omap2420_gpio4_hwmod,
1598 .clk = "gpios_ick", 1166 .clk = "gpios_ick",
1599 .addr = omap2420_gpio4_addr_space, 1167 .addr = omap2420_gpio4_addr_space,
1600 .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
1601 .user = OCP_USER_MPU | OCP_USER_SDMA, 1168 .user = OCP_USER_MPU | OCP_USER_SDMA,
1602}; 1169};
1603 1170
@@ -1607,32 +1174,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1607 .dbck_flag = false, 1174 .dbck_flag = false,
1608}; 1175};
1609 1176
1610static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1611 .rev_offs = 0x0000,
1612 .sysc_offs = 0x0010,
1613 .syss_offs = 0x0014,
1614 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1615 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1616 SYSS_HAS_RESET_STATUS),
1617 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1618 .sysc_fields = &omap_hwmod_sysc_type1,
1619};
1620
1621/*
1622 * 'gpio' class
1623 * general purpose io module
1624 */
1625static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1626 .name = "gpio",
1627 .sysc = &omap242x_gpio_sysc,
1628 .rev = 0,
1629};
1630
1631/* gpio1 */ 1177/* gpio1 */
1632static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
1633 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1634};
1635
1636static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { 1178static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1637 &omap2420_l4_wkup__gpio1, 1179 &omap2420_l4_wkup__gpio1,
1638}; 1180};
@@ -1640,8 +1182,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1640static struct omap_hwmod omap2420_gpio1_hwmod = { 1182static struct omap_hwmod omap2420_gpio1_hwmod = {
1641 .name = "gpio1", 1183 .name = "gpio1",
1642 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1184 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1643 .mpu_irqs = omap242x_gpio1_irqs, 1185 .mpu_irqs = omap2_gpio1_irqs,
1644 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
1645 .main_clk = "gpios_fck", 1186 .main_clk = "gpios_fck",
1646 .prcm = { 1187 .prcm = {
1647 .omap2 = { 1188 .omap2 = {
@@ -1654,16 +1195,12 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
1654 }, 1195 },
1655 .slaves = omap2420_gpio1_slaves, 1196 .slaves = omap2420_gpio1_slaves,
1656 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), 1197 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1657 .class = &omap242x_gpio_hwmod_class, 1198 .class = &omap2xxx_gpio_hwmod_class,
1658 .dev_attr = &gpio_dev_attr, 1199 .dev_attr = &gpio_dev_attr,
1659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1660}; 1201};
1661 1202
1662/* gpio2 */ 1203/* gpio2 */
1663static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
1664 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1665};
1666
1667static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { 1204static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1668 &omap2420_l4_wkup__gpio2, 1205 &omap2420_l4_wkup__gpio2,
1669}; 1206};
@@ -1671,8 +1208,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1671static struct omap_hwmod omap2420_gpio2_hwmod = { 1208static struct omap_hwmod omap2420_gpio2_hwmod = {
1672 .name = "gpio2", 1209 .name = "gpio2",
1673 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1210 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1674 .mpu_irqs = omap242x_gpio2_irqs, 1211 .mpu_irqs = omap2_gpio2_irqs,
1675 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
1676 .main_clk = "gpios_fck", 1212 .main_clk = "gpios_fck",
1677 .prcm = { 1213 .prcm = {
1678 .omap2 = { 1214 .omap2 = {
@@ -1685,16 +1221,12 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
1685 }, 1221 },
1686 .slaves = omap2420_gpio2_slaves, 1222 .slaves = omap2420_gpio2_slaves,
1687 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), 1223 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1688 .class = &omap242x_gpio_hwmod_class, 1224 .class = &omap2xxx_gpio_hwmod_class,
1689 .dev_attr = &gpio_dev_attr, 1225 .dev_attr = &gpio_dev_attr,
1690 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1691}; 1227};
1692 1228
1693/* gpio3 */ 1229/* gpio3 */
1694static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
1695 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1696};
1697
1698static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { 1230static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1699 &omap2420_l4_wkup__gpio3, 1231 &omap2420_l4_wkup__gpio3,
1700}; 1232};
@@ -1702,8 +1234,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1702static struct omap_hwmod omap2420_gpio3_hwmod = { 1234static struct omap_hwmod omap2420_gpio3_hwmod = {
1703 .name = "gpio3", 1235 .name = "gpio3",
1704 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1236 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1705 .mpu_irqs = omap242x_gpio3_irqs, 1237 .mpu_irqs = omap2_gpio3_irqs,
1706 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
1707 .main_clk = "gpios_fck", 1238 .main_clk = "gpios_fck",
1708 .prcm = { 1239 .prcm = {
1709 .omap2 = { 1240 .omap2 = {
@@ -1716,16 +1247,12 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
1716 }, 1247 },
1717 .slaves = omap2420_gpio3_slaves, 1248 .slaves = omap2420_gpio3_slaves,
1718 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), 1249 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1719 .class = &omap242x_gpio_hwmod_class, 1250 .class = &omap2xxx_gpio_hwmod_class,
1720 .dev_attr = &gpio_dev_attr, 1251 .dev_attr = &gpio_dev_attr,
1721 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1252 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1722}; 1253};
1723 1254
1724/* gpio4 */ 1255/* gpio4 */
1725static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
1726 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1727};
1728
1729static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { 1256static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1730 &omap2420_l4_wkup__gpio4, 1257 &omap2420_l4_wkup__gpio4,
1731}; 1258};
@@ -1733,8 +1260,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1733static struct omap_hwmod omap2420_gpio4_hwmod = { 1260static struct omap_hwmod omap2420_gpio4_hwmod = {
1734 .name = "gpio4", 1261 .name = "gpio4",
1735 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1262 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1736 .mpu_irqs = omap242x_gpio4_irqs, 1263 .mpu_irqs = omap2_gpio4_irqs,
1737 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
1738 .main_clk = "gpios_fck", 1264 .main_clk = "gpios_fck",
1739 .prcm = { 1265 .prcm = {
1740 .omap2 = { 1266 .omap2 = {
@@ -1747,28 +1273,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
1747 }, 1273 },
1748 .slaves = omap2420_gpio4_slaves, 1274 .slaves = omap2420_gpio4_slaves,
1749 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), 1275 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1750 .class = &omap242x_gpio_hwmod_class, 1276 .class = &omap2xxx_gpio_hwmod_class,
1751 .dev_attr = &gpio_dev_attr, 1277 .dev_attr = &gpio_dev_attr,
1752 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1753}; 1279};
1754 1280
1755/* system dma */
1756static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1757 .rev_offs = 0x0000,
1758 .sysc_offs = 0x002c,
1759 .syss_offs = 0x0028,
1760 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1761 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1762 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1763 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1764 .sysc_fields = &omap_hwmod_sysc_type1,
1765};
1766
1767static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1768 .name = "dma",
1769 .sysc = &omap2420_dma_sysc,
1770};
1771
1772/* dma attributes */ 1281/* dma attributes */
1773static struct omap_dma_dev_attr dma_dev_attr = { 1282static struct omap_dma_dev_attr dma_dev_attr = {
1774 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1283 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1776,21 +1285,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
1776 .lch_count = 32, 1285 .lch_count = 32,
1777}; 1286};
1778 1287
1779static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
1780 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1781 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1782 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1783 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1784};
1785
1786static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
1787 {
1788 .pa_start = 0x48056000,
1789 .pa_end = 0x48056fff,
1790 .flags = ADDR_TYPE_RT
1791 },
1792};
1793
1794/* dma_system -> L3 */ 1288/* dma_system -> L3 */
1795static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 1289static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1796 .master = &omap2420_dma_system_hwmod, 1290 .master = &omap2420_dma_system_hwmod,
@@ -1809,8 +1303,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1809 .master = &omap2420_l4_core_hwmod, 1303 .master = &omap2420_l4_core_hwmod,
1810 .slave = &omap2420_dma_system_hwmod, 1304 .slave = &omap2420_dma_system_hwmod,
1811 .clk = "sdma_ick", 1305 .clk = "sdma_ick",
1812 .addr = omap2420_dma_system_addrs, 1306 .addr = omap2_dma_system_addrs,
1813 .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
1814 .user = OCP_USER_MPU | OCP_USER_SDMA, 1307 .user = OCP_USER_MPU | OCP_USER_SDMA,
1815}; 1308};
1816 1309
@@ -1821,9 +1314,8 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1821 1314
1822static struct omap_hwmod omap2420_dma_system_hwmod = { 1315static struct omap_hwmod omap2420_dma_system_hwmod = {
1823 .name = "dma", 1316 .name = "dma",
1824 .class = &omap2420_dma_hwmod_class, 1317 .class = &omap2xxx_dma_hwmod_class,
1825 .mpu_irqs = omap2420_dma_system_irqs, 1318 .mpu_irqs = omap2_dma_system_irqs,
1826 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
1827 .main_clk = "core_l3_ck", 1319 .main_clk = "core_l3_ck",
1828 .slaves = omap2420_dma_system_slaves, 1320 .slaves = omap2420_dma_system_slaves,
1829 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), 1321 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
@@ -1834,48 +1326,19 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
1834 .flags = HWMOD_NO_IDLEST, 1326 .flags = HWMOD_NO_IDLEST,
1835}; 1327};
1836 1328
1837/*
1838 * 'mailbox' class
1839 * mailbox module allowing communication between the on-chip processors
1840 * using a queued mailbox-interrupt mechanism.
1841 */
1842
1843static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1844 .rev_offs = 0x000,
1845 .sysc_offs = 0x010,
1846 .syss_offs = 0x014,
1847 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1848 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1849 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1850 .sysc_fields = &omap_hwmod_sysc_type1,
1851};
1852
1853static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1854 .name = "mailbox",
1855 .sysc = &omap2420_mailbox_sysc,
1856};
1857
1858/* mailbox */ 1329/* mailbox */
1859static struct omap_hwmod omap2420_mailbox_hwmod; 1330static struct omap_hwmod omap2420_mailbox_hwmod;
1860static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 1331static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1861 { .name = "dsp", .irq = 26 }, 1332 { .name = "dsp", .irq = 26 },
1862 { .name = "iva", .irq = 34 }, 1333 { .name = "iva", .irq = 34 },
1863}; 1334 { .irq = -1 }
1864
1865static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
1866 {
1867 .pa_start = 0x48094000,
1868 .pa_end = 0x480941ff,
1869 .flags = ADDR_TYPE_RT,
1870 },
1871}; 1335};
1872 1336
1873/* l4_core -> mailbox */ 1337/* l4_core -> mailbox */
1874static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 1338static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1875 .master = &omap2420_l4_core_hwmod, 1339 .master = &omap2420_l4_core_hwmod,
1876 .slave = &omap2420_mailbox_hwmod, 1340 .slave = &omap2420_mailbox_hwmod,
1877 .addr = omap2420_mailbox_addrs, 1341 .addr = omap2_mailbox_addrs,
1878 .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
1879 .user = OCP_USER_MPU | OCP_USER_SDMA, 1342 .user = OCP_USER_MPU | OCP_USER_SDMA,
1880}; 1343};
1881 1344
@@ -1886,9 +1349,8 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1886 1349
1887static struct omap_hwmod omap2420_mailbox_hwmod = { 1350static struct omap_hwmod omap2420_mailbox_hwmod = {
1888 .name = "mailbox", 1351 .name = "mailbox",
1889 .class = &omap2420_mailbox_hwmod_class, 1352 .class = &omap2xxx_mailbox_hwmod_class,
1890 .mpu_irqs = omap2420_mailbox_irqs, 1353 .mpu_irqs = omap2420_mailbox_irqs,
1891 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
1892 .main_clk = "mailboxes_ick", 1354 .main_clk = "mailboxes_ick",
1893 .prcm = { 1355 .prcm = {
1894 .omap2 = { 1356 .omap2 = {
@@ -1904,45 +1366,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
1904 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1905}; 1367};
1906 1368
1907/*
1908 * 'mcspi' class
1909 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1910 * bus
1911 */
1912
1913static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1914 .rev_offs = 0x0000,
1915 .sysc_offs = 0x0010,
1916 .syss_offs = 0x0014,
1917 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1918 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1919 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1921 .sysc_fields = &omap_hwmod_sysc_type1,
1922};
1923
1924static struct omap_hwmod_class omap2420_mcspi_class = {
1925 .name = "mcspi",
1926 .sysc = &omap2420_mcspi_sysc,
1927 .rev = OMAP2_MCSPI_REV,
1928};
1929
1930/* mcspi1 */ 1369/* mcspi1 */
1931static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
1932 { .irq = 65 },
1933};
1934
1935static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
1936 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1937 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1938 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1939 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1940 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1941 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1942 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1943 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1944};
1945
1946static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { 1370static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1947 &omap2420_l4_core__mcspi1, 1371 &omap2420_l4_core__mcspi1,
1948}; 1372};
@@ -1953,10 +1377,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1953 1377
1954static struct omap_hwmod omap2420_mcspi1_hwmod = { 1378static struct omap_hwmod omap2420_mcspi1_hwmod = {
1955 .name = "mcspi1_hwmod", 1379 .name = "mcspi1_hwmod",
1956 .mpu_irqs = omap2420_mcspi1_mpu_irqs, 1380 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1957 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), 1381 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1958 .sdma_reqs = omap2420_mcspi1_sdma_reqs,
1959 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
1960 .main_clk = "mcspi1_fck", 1382 .main_clk = "mcspi1_fck",
1961 .prcm = { 1383 .prcm = {
1962 .omap2 = { 1384 .omap2 = {
@@ -1969,23 +1391,12 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
1969 }, 1391 },
1970 .slaves = omap2420_mcspi1_slaves, 1392 .slaves = omap2420_mcspi1_slaves,
1971 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), 1393 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1972 .class = &omap2420_mcspi_class, 1394 .class = &omap2xxx_mcspi_class,
1973 .dev_attr = &omap_mcspi1_dev_attr, 1395 .dev_attr = &omap_mcspi1_dev_attr,
1974 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1396 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1975}; 1397};
1976 1398
1977/* mcspi2 */ 1399/* mcspi2 */
1978static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
1979 { .irq = 66 },
1980};
1981
1982static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
1983 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1984 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1985 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1986 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1987};
1988
1989static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { 1400static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1990 &omap2420_l4_core__mcspi2, 1401 &omap2420_l4_core__mcspi2,
1991}; 1402};
@@ -1996,10 +1407,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1996 1407
1997static struct omap_hwmod omap2420_mcspi2_hwmod = { 1408static struct omap_hwmod omap2420_mcspi2_hwmod = {
1998 .name = "mcspi2_hwmod", 1409 .name = "mcspi2_hwmod",
1999 .mpu_irqs = omap2420_mcspi2_mpu_irqs, 1410 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2000 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), 1411 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2001 .sdma_reqs = omap2420_mcspi2_sdma_reqs,
2002 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
2003 .main_clk = "mcspi2_fck", 1412 .main_clk = "mcspi2_fck",
2004 .prcm = { 1413 .prcm = {
2005 .omap2 = { 1414 .omap2 = {
@@ -2012,8 +1421,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
2012 }, 1421 },
2013 .slaves = omap2420_mcspi2_slaves, 1422 .slaves = omap2420_mcspi2_slaves,
2014 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), 1423 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
2015 .class = &omap2420_mcspi_class, 1424 .class = &omap2xxx_mcspi_class,
2016 .dev_attr = &omap_mcspi2_dev_attr, 1425 .dev_attr = &omap_mcspi2_dev_attr,
2017 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1426 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2018}; 1427};
2019 1428
@@ -2030,20 +1439,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
2030static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { 1439static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
2031 { .name = "tx", .irq = 59 }, 1440 { .name = "tx", .irq = 59 },
2032 { .name = "rx", .irq = 60 }, 1441 { .name = "rx", .irq = 60 },
2033}; 1442 { .irq = -1 }
2034
2035static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
2036 { .name = "rx", .dma_req = 32 },
2037 { .name = "tx", .dma_req = 31 },
2038};
2039
2040static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
2041 {
2042 .name = "mpu",
2043 .pa_start = 0x48074000,
2044 .pa_end = 0x480740ff,
2045 .flags = ADDR_TYPE_RT
2046 },
2047}; 1443};
2048 1444
2049/* l4_core -> mcbsp1 */ 1445/* l4_core -> mcbsp1 */
@@ -2051,8 +1447,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
2051 .master = &omap2420_l4_core_hwmod, 1447 .master = &omap2420_l4_core_hwmod,
2052 .slave = &omap2420_mcbsp1_hwmod, 1448 .slave = &omap2420_mcbsp1_hwmod,
2053 .clk = "mcbsp1_ick", 1449 .clk = "mcbsp1_ick",
2054 .addr = omap2420_mcbsp1_addrs, 1450 .addr = omap2_mcbsp1_addrs,
2055 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
2056 .user = OCP_USER_MPU | OCP_USER_SDMA, 1451 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057}; 1452};
2058 1453
@@ -2065,9 +1460,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2065 .name = "mcbsp1", 1460 .name = "mcbsp1",
2066 .class = &omap2420_mcbsp_hwmod_class, 1461 .class = &omap2420_mcbsp_hwmod_class,
2067 .mpu_irqs = omap2420_mcbsp1_irqs, 1462 .mpu_irqs = omap2420_mcbsp1_irqs,
2068 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), 1463 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2069 .sdma_reqs = omap2420_mcbsp1_sdma_chs,
2070 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
2071 .main_clk = "mcbsp1_fck", 1464 .main_clk = "mcbsp1_fck",
2072 .prcm = { 1465 .prcm = {
2073 .omap2 = { 1466 .omap2 = {
@@ -2087,20 +1480,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2087static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { 1480static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
2088 { .name = "tx", .irq = 62 }, 1481 { .name = "tx", .irq = 62 },
2089 { .name = "rx", .irq = 63 }, 1482 { .name = "rx", .irq = 63 },
2090}; 1483 { .irq = -1 }
2091
2092static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
2093 { .name = "rx", .dma_req = 34 },
2094 { .name = "tx", .dma_req = 33 },
2095};
2096
2097static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
2098 {
2099 .name = "mpu",
2100 .pa_start = 0x48076000,
2101 .pa_end = 0x480760ff,
2102 .flags = ADDR_TYPE_RT
2103 },
2104}; 1484};
2105 1485
2106/* l4_core -> mcbsp2 */ 1486/* l4_core -> mcbsp2 */
@@ -2108,8 +1488,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
2108 .master = &omap2420_l4_core_hwmod, 1488 .master = &omap2420_l4_core_hwmod,
2109 .slave = &omap2420_mcbsp2_hwmod, 1489 .slave = &omap2420_mcbsp2_hwmod,
2110 .clk = "mcbsp2_ick", 1490 .clk = "mcbsp2_ick",
2111 .addr = omap2420_mcbsp2_addrs, 1491 .addr = omap2xxx_mcbsp2_addrs,
2112 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
2113 .user = OCP_USER_MPU | OCP_USER_SDMA, 1492 .user = OCP_USER_MPU | OCP_USER_SDMA,
2114}; 1493};
2115 1494
@@ -2122,9 +1501,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
2122 .name = "mcbsp2", 1501 .name = "mcbsp2",
2123 .class = &omap2420_mcbsp_hwmod_class, 1502 .class = &omap2420_mcbsp_hwmod_class,
2124 .mpu_irqs = omap2420_mcbsp2_irqs, 1503 .mpu_irqs = omap2420_mcbsp2_irqs,
2125 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), 1504 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2126 .sdma_reqs = omap2420_mcbsp2_sdma_chs,
2127 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
2128 .main_clk = "mcbsp2_fck", 1505 .main_clk = "mcbsp2_fck",
2129 .prcm = { 1506 .prcm = {
2130 .omap2 = { 1507 .omap2 = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 05:28:32 -0500