diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_2420_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1305 |
1 files changed, 1304 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index b85c630b64d6..61e58bd27aec 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
@@ -18,6 +18,10 @@ | |||
18 | #include <plat/serial.h> | 18 | #include <plat/serial.h> |
19 | #include <plat/i2c.h> | 19 | #include <plat/i2c.h> |
20 | #include <plat/gpio.h> | 20 | #include <plat/gpio.h> |
21 | #include <plat/mcspi.h> | ||
22 | #include <plat/dmtimer.h> | ||
23 | #include <plat/l3_2xxx.h> | ||
24 | #include <plat/l4_2xxx.h> | ||
21 | 25 | ||
22 | #include "omap_hwmod_common_data.h" | 26 | #include "omap_hwmod_common_data.h" |
23 | 27 | ||
@@ -38,12 +42,18 @@ static struct omap_hwmod omap2420_mpu_hwmod; | |||
38 | static struct omap_hwmod omap2420_iva_hwmod; | 42 | static struct omap_hwmod omap2420_iva_hwmod; |
39 | static struct omap_hwmod omap2420_l3_main_hwmod; | 43 | static struct omap_hwmod omap2420_l3_main_hwmod; |
40 | static struct omap_hwmod omap2420_l4_core_hwmod; | 44 | static struct omap_hwmod omap2420_l4_core_hwmod; |
45 | static struct omap_hwmod omap2420_dss_core_hwmod; | ||
46 | static struct omap_hwmod omap2420_dss_dispc_hwmod; | ||
47 | static struct omap_hwmod omap2420_dss_rfbi_hwmod; | ||
48 | static struct omap_hwmod omap2420_dss_venc_hwmod; | ||
41 | static struct omap_hwmod omap2420_wd_timer2_hwmod; | 49 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
42 | static struct omap_hwmod omap2420_gpio1_hwmod; | 50 | static struct omap_hwmod omap2420_gpio1_hwmod; |
43 | static struct omap_hwmod omap2420_gpio2_hwmod; | 51 | static struct omap_hwmod omap2420_gpio2_hwmod; |
44 | static struct omap_hwmod omap2420_gpio3_hwmod; | 52 | static struct omap_hwmod omap2420_gpio3_hwmod; |
45 | static struct omap_hwmod omap2420_gpio4_hwmod; | 53 | static struct omap_hwmod omap2420_gpio4_hwmod; |
46 | static struct omap_hwmod omap2420_dma_system_hwmod; | 54 | static struct omap_hwmod omap2420_dma_system_hwmod; |
55 | static struct omap_hwmod omap2420_mcspi1_hwmod; | ||
56 | static struct omap_hwmod omap2420_mcspi2_hwmod; | ||
47 | 57 | ||
48 | /* L3 -> L4_CORE interface */ | 58 | /* L3 -> L4_CORE interface */ |
49 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { | 59 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
@@ -64,6 +74,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { | |||
64 | &omap2420_mpu__l3_main, | 74 | &omap2420_mpu__l3_main, |
65 | }; | 75 | }; |
66 | 76 | ||
77 | /* DSS -> l3 */ | ||
78 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { | ||
79 | .master = &omap2420_dss_core_hwmod, | ||
80 | .slave = &omap2420_l3_main_hwmod, | ||
81 | .fw = { | ||
82 | .omap2 = { | ||
83 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | ||
84 | .flags = OMAP_FIREWALL_L3, | ||
85 | } | ||
86 | }, | ||
87 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
88 | }; | ||
89 | |||
67 | /* Master interfaces on the L3 interconnect */ | 90 | /* Master interfaces on the L3 interconnect */ |
68 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { | 91 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
69 | &omap2420_l3_main__l4_core, | 92 | &omap2420_l3_main__l4_core, |
@@ -87,6 +110,44 @@ static struct omap_hwmod omap2420_uart2_hwmod; | |||
87 | static struct omap_hwmod omap2420_uart3_hwmod; | 110 | static struct omap_hwmod omap2420_uart3_hwmod; |
88 | static struct omap_hwmod omap2420_i2c1_hwmod; | 111 | static struct omap_hwmod omap2420_i2c1_hwmod; |
89 | static struct omap_hwmod omap2420_i2c2_hwmod; | 112 | static struct omap_hwmod omap2420_i2c2_hwmod; |
113 | static struct omap_hwmod omap2420_mcbsp1_hwmod; | ||
114 | static struct omap_hwmod omap2420_mcbsp2_hwmod; | ||
115 | |||
116 | /* l4 core -> mcspi1 interface */ | ||
117 | static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { | ||
118 | { | ||
119 | .pa_start = 0x48098000, | ||
120 | .pa_end = 0x480980ff, | ||
121 | .flags = ADDR_TYPE_RT, | ||
122 | }, | ||
123 | }; | ||
124 | |||
125 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { | ||
126 | .master = &omap2420_l4_core_hwmod, | ||
127 | .slave = &omap2420_mcspi1_hwmod, | ||
128 | .clk = "mcspi1_ick", | ||
129 | .addr = omap2420_mcspi1_addr_space, | ||
130 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), | ||
131 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
132 | }; | ||
133 | |||
134 | /* l4 core -> mcspi2 interface */ | ||
135 | static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { | ||
136 | { | ||
137 | .pa_start = 0x4809a000, | ||
138 | .pa_end = 0x4809a0ff, | ||
139 | .flags = ADDR_TYPE_RT, | ||
140 | }, | ||
141 | }; | ||
142 | |||
143 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { | ||
144 | .master = &omap2420_l4_core_hwmod, | ||
145 | .slave = &omap2420_mcspi2_hwmod, | ||
146 | .clk = "mcspi2_ick", | ||
147 | .addr = omap2420_mcspi2_addr_space, | ||
148 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), | ||
149 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
150 | }; | ||
90 | 151 | ||
91 | /* L4_CORE -> L4_WKUP interface */ | 152 | /* L4_CORE -> L4_WKUP interface */ |
92 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { | 153 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
@@ -279,6 +340,625 @@ static struct omap_hwmod omap2420_iva_hwmod = { | |||
279 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | 340 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
280 | }; | 341 | }; |
281 | 342 | ||
343 | /* Timer Common */ | ||
344 | static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { | ||
345 | .rev_offs = 0x0000, | ||
346 | .sysc_offs = 0x0010, | ||
347 | .syss_offs = 0x0014, | ||
348 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | ||
349 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | ||
350 | SYSC_HAS_AUTOIDLE), | ||
351 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
352 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
353 | }; | ||
354 | |||
355 | static struct omap_hwmod_class omap2420_timer_hwmod_class = { | ||
356 | .name = "timer", | ||
357 | .sysc = &omap2420_timer_sysc, | ||
358 | .rev = OMAP_TIMER_IP_VERSION_1, | ||
359 | }; | ||
360 | |||
361 | /* timer1 */ | ||
362 | static struct omap_hwmod omap2420_timer1_hwmod; | ||
363 | static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { | ||
364 | { .irq = 37, }, | ||
365 | }; | ||
366 | |||
367 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { | ||
368 | { | ||
369 | .pa_start = 0x48028000, | ||
370 | .pa_end = 0x48028000 + SZ_1K - 1, | ||
371 | .flags = ADDR_TYPE_RT | ||
372 | }, | ||
373 | }; | ||
374 | |||
375 | /* l4_wkup -> timer1 */ | ||
376 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { | ||
377 | .master = &omap2420_l4_wkup_hwmod, | ||
378 | .slave = &omap2420_timer1_hwmod, | ||
379 | .clk = "gpt1_ick", | ||
380 | .addr = omap2420_timer1_addrs, | ||
381 | .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs), | ||
382 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
383 | }; | ||
384 | |||
385 | /* timer1 slave port */ | ||
386 | static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { | ||
387 | &omap2420_l4_wkup__timer1, | ||
388 | }; | ||
389 | |||
390 | /* timer1 hwmod */ | ||
391 | static struct omap_hwmod omap2420_timer1_hwmod = { | ||
392 | .name = "timer1", | ||
393 | .mpu_irqs = omap2420_timer1_mpu_irqs, | ||
394 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs), | ||
395 | .main_clk = "gpt1_fck", | ||
396 | .prcm = { | ||
397 | .omap2 = { | ||
398 | .prcm_reg_id = 1, | ||
399 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | ||
400 | .module_offs = WKUP_MOD, | ||
401 | .idlest_reg_id = 1, | ||
402 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | ||
403 | }, | ||
404 | }, | ||
405 | .slaves = omap2420_timer1_slaves, | ||
406 | .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), | ||
407 | .class = &omap2420_timer_hwmod_class, | ||
408 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
409 | }; | ||
410 | |||
411 | /* timer2 */ | ||
412 | static struct omap_hwmod omap2420_timer2_hwmod; | ||
413 | static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { | ||
414 | { .irq = 38, }, | ||
415 | }; | ||
416 | |||
417 | static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = { | ||
418 | { | ||
419 | .pa_start = 0x4802a000, | ||
420 | .pa_end = 0x4802a000 + SZ_1K - 1, | ||
421 | .flags = ADDR_TYPE_RT | ||
422 | }, | ||
423 | }; | ||
424 | |||
425 | /* l4_core -> timer2 */ | ||
426 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { | ||
427 | .master = &omap2420_l4_core_hwmod, | ||
428 | .slave = &omap2420_timer2_hwmod, | ||
429 | .clk = "gpt2_ick", | ||
430 | .addr = omap2420_timer2_addrs, | ||
431 | .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs), | ||
432 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
433 | }; | ||
434 | |||
435 | /* timer2 slave port */ | ||
436 | static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { | ||
437 | &omap2420_l4_core__timer2, | ||
438 | }; | ||
439 | |||
440 | /* timer2 hwmod */ | ||
441 | static struct omap_hwmod omap2420_timer2_hwmod = { | ||
442 | .name = "timer2", | ||
443 | .mpu_irqs = omap2420_timer2_mpu_irqs, | ||
444 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs), | ||
445 | .main_clk = "gpt2_fck", | ||
446 | .prcm = { | ||
447 | .omap2 = { | ||
448 | .prcm_reg_id = 1, | ||
449 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | ||
450 | .module_offs = CORE_MOD, | ||
451 | .idlest_reg_id = 1, | ||
452 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | ||
453 | }, | ||
454 | }, | ||
455 | .slaves = omap2420_timer2_slaves, | ||
456 | .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), | ||
457 | .class = &omap2420_timer_hwmod_class, | ||
458 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
459 | }; | ||
460 | |||
461 | /* timer3 */ | ||
462 | static struct omap_hwmod omap2420_timer3_hwmod; | ||
463 | static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { | ||
464 | { .irq = 39, }, | ||
465 | }; | ||
466 | |||
467 | static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = { | ||
468 | { | ||
469 | .pa_start = 0x48078000, | ||
470 | .pa_end = 0x48078000 + SZ_1K - 1, | ||
471 | .flags = ADDR_TYPE_RT | ||
472 | }, | ||
473 | }; | ||
474 | |||
475 | /* l4_core -> timer3 */ | ||
476 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { | ||
477 | .master = &omap2420_l4_core_hwmod, | ||
478 | .slave = &omap2420_timer3_hwmod, | ||
479 | .clk = "gpt3_ick", | ||
480 | .addr = omap2420_timer3_addrs, | ||
481 | .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs), | ||
482 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
483 | }; | ||
484 | |||
485 | /* timer3 slave port */ | ||
486 | static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { | ||
487 | &omap2420_l4_core__timer3, | ||
488 | }; | ||
489 | |||
490 | /* timer3 hwmod */ | ||
491 | static struct omap_hwmod omap2420_timer3_hwmod = { | ||
492 | .name = "timer3", | ||
493 | .mpu_irqs = omap2420_timer3_mpu_irqs, | ||
494 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs), | ||
495 | .main_clk = "gpt3_fck", | ||
496 | .prcm = { | ||
497 | .omap2 = { | ||
498 | .prcm_reg_id = 1, | ||
499 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | ||
500 | .module_offs = CORE_MOD, | ||
501 | .idlest_reg_id = 1, | ||
502 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | ||
503 | }, | ||
504 | }, | ||
505 | .slaves = omap2420_timer3_slaves, | ||
506 | .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), | ||
507 | .class = &omap2420_timer_hwmod_class, | ||
508 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
509 | }; | ||
510 | |||
511 | /* timer4 */ | ||
512 | static struct omap_hwmod omap2420_timer4_hwmod; | ||
513 | static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { | ||
514 | { .irq = 40, }, | ||
515 | }; | ||
516 | |||
517 | static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = { | ||
518 | { | ||
519 | .pa_start = 0x4807a000, | ||
520 | .pa_end = 0x4807a000 + SZ_1K - 1, | ||
521 | .flags = ADDR_TYPE_RT | ||
522 | }, | ||
523 | }; | ||
524 | |||
525 | /* l4_core -> timer4 */ | ||
526 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { | ||
527 | .master = &omap2420_l4_core_hwmod, | ||
528 | .slave = &omap2420_timer4_hwmod, | ||
529 | .clk = "gpt4_ick", | ||
530 | .addr = omap2420_timer4_addrs, | ||
531 | .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs), | ||
532 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
533 | }; | ||
534 | |||
535 | /* timer4 slave port */ | ||
536 | static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { | ||
537 | &omap2420_l4_core__timer4, | ||
538 | }; | ||
539 | |||
540 | /* timer4 hwmod */ | ||
541 | static struct omap_hwmod omap2420_timer4_hwmod = { | ||
542 | .name = "timer4", | ||
543 | .mpu_irqs = omap2420_timer4_mpu_irqs, | ||
544 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs), | ||
545 | .main_clk = "gpt4_fck", | ||
546 | .prcm = { | ||
547 | .omap2 = { | ||
548 | .prcm_reg_id = 1, | ||
549 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | ||
550 | .module_offs = CORE_MOD, | ||
551 | .idlest_reg_id = 1, | ||
552 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | ||
553 | }, | ||
554 | }, | ||
555 | .slaves = omap2420_timer4_slaves, | ||
556 | .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), | ||
557 | .class = &omap2420_timer_hwmod_class, | ||
558 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
559 | }; | ||
560 | |||
561 | /* timer5 */ | ||
562 | static struct omap_hwmod omap2420_timer5_hwmod; | ||
563 | static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { | ||
564 | { .irq = 41, }, | ||
565 | }; | ||
566 | |||
567 | static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = { | ||
568 | { | ||
569 | .pa_start = 0x4807c000, | ||
570 | .pa_end = 0x4807c000 + SZ_1K - 1, | ||
571 | .flags = ADDR_TYPE_RT | ||
572 | }, | ||
573 | }; | ||
574 | |||
575 | /* l4_core -> timer5 */ | ||
576 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { | ||
577 | .master = &omap2420_l4_core_hwmod, | ||
578 | .slave = &omap2420_timer5_hwmod, | ||
579 | .clk = "gpt5_ick", | ||
580 | .addr = omap2420_timer5_addrs, | ||
581 | .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs), | ||
582 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
583 | }; | ||
584 | |||
585 | /* timer5 slave port */ | ||
586 | static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { | ||
587 | &omap2420_l4_core__timer5, | ||
588 | }; | ||
589 | |||
590 | /* timer5 hwmod */ | ||
591 | static struct omap_hwmod omap2420_timer5_hwmod = { | ||
592 | .name = "timer5", | ||
593 | .mpu_irqs = omap2420_timer5_mpu_irqs, | ||
594 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs), | ||
595 | .main_clk = "gpt5_fck", | ||
596 | .prcm = { | ||
597 | .omap2 = { | ||
598 | .prcm_reg_id = 1, | ||
599 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | ||
600 | .module_offs = CORE_MOD, | ||
601 | .idlest_reg_id = 1, | ||
602 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | ||
603 | }, | ||
604 | }, | ||
605 | .slaves = omap2420_timer5_slaves, | ||
606 | .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), | ||
607 | .class = &omap2420_timer_hwmod_class, | ||
608 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
609 | }; | ||
610 | |||
611 | |||
612 | /* timer6 */ | ||
613 | static struct omap_hwmod omap2420_timer6_hwmod; | ||
614 | static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { | ||
615 | { .irq = 42, }, | ||
616 | }; | ||
617 | |||
618 | static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = { | ||
619 | { | ||
620 | .pa_start = 0x4807e000, | ||
621 | .pa_end = 0x4807e000 + SZ_1K - 1, | ||
622 | .flags = ADDR_TYPE_RT | ||
623 | }, | ||
624 | }; | ||
625 | |||
626 | /* l4_core -> timer6 */ | ||
627 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { | ||
628 | .master = &omap2420_l4_core_hwmod, | ||
629 | .slave = &omap2420_timer6_hwmod, | ||
630 | .clk = "gpt6_ick", | ||
631 | .addr = omap2420_timer6_addrs, | ||
632 | .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs), | ||
633 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
634 | }; | ||
635 | |||
636 | /* timer6 slave port */ | ||
637 | static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { | ||
638 | &omap2420_l4_core__timer6, | ||
639 | }; | ||
640 | |||
641 | /* timer6 hwmod */ | ||
642 | static struct omap_hwmod omap2420_timer6_hwmod = { | ||
643 | .name = "timer6", | ||
644 | .mpu_irqs = omap2420_timer6_mpu_irqs, | ||
645 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs), | ||
646 | .main_clk = "gpt6_fck", | ||
647 | .prcm = { | ||
648 | .omap2 = { | ||
649 | .prcm_reg_id = 1, | ||
650 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | ||
651 | .module_offs = CORE_MOD, | ||
652 | .idlest_reg_id = 1, | ||
653 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | ||
654 | }, | ||
655 | }, | ||
656 | .slaves = omap2420_timer6_slaves, | ||
657 | .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), | ||
658 | .class = &omap2420_timer_hwmod_class, | ||
659 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
660 | }; | ||
661 | |||
662 | /* timer7 */ | ||
663 | static struct omap_hwmod omap2420_timer7_hwmod; | ||
664 | static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { | ||
665 | { .irq = 43, }, | ||
666 | }; | ||
667 | |||
668 | static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = { | ||
669 | { | ||
670 | .pa_start = 0x48080000, | ||
671 | .pa_end = 0x48080000 + SZ_1K - 1, | ||
672 | .flags = ADDR_TYPE_RT | ||
673 | }, | ||
674 | }; | ||
675 | |||
676 | /* l4_core -> timer7 */ | ||
677 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { | ||
678 | .master = &omap2420_l4_core_hwmod, | ||
679 | .slave = &omap2420_timer7_hwmod, | ||
680 | .clk = "gpt7_ick", | ||
681 | .addr = omap2420_timer7_addrs, | ||
682 | .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs), | ||
683 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
684 | }; | ||
685 | |||
686 | /* timer7 slave port */ | ||
687 | static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { | ||
688 | &omap2420_l4_core__timer7, | ||
689 | }; | ||
690 | |||
691 | /* timer7 hwmod */ | ||
692 | static struct omap_hwmod omap2420_timer7_hwmod = { | ||
693 | .name = "timer7", | ||
694 | .mpu_irqs = omap2420_timer7_mpu_irqs, | ||
695 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs), | ||
696 | .main_clk = "gpt7_fck", | ||
697 | .prcm = { | ||
698 | .omap2 = { | ||
699 | .prcm_reg_id = 1, | ||
700 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | ||
701 | .module_offs = CORE_MOD, | ||
702 | .idlest_reg_id = 1, | ||
703 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | ||
704 | }, | ||
705 | }, | ||
706 | .slaves = omap2420_timer7_slaves, | ||
707 | .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), | ||
708 | .class = &omap2420_timer_hwmod_class, | ||
709 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
710 | }; | ||
711 | |||
712 | /* timer8 */ | ||
713 | static struct omap_hwmod omap2420_timer8_hwmod; | ||
714 | static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { | ||
715 | { .irq = 44, }, | ||
716 | }; | ||
717 | |||
718 | static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = { | ||
719 | { | ||
720 | .pa_start = 0x48082000, | ||
721 | .pa_end = 0x48082000 + SZ_1K - 1, | ||
722 | .flags = ADDR_TYPE_RT | ||
723 | }, | ||
724 | }; | ||
725 | |||
726 | /* l4_core -> timer8 */ | ||
727 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { | ||
728 | .master = &omap2420_l4_core_hwmod, | ||
729 | .slave = &omap2420_timer8_hwmod, | ||
730 | .clk = "gpt8_ick", | ||
731 | .addr = omap2420_timer8_addrs, | ||
732 | .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs), | ||
733 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
734 | }; | ||
735 | |||
736 | /* timer8 slave port */ | ||
737 | static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { | ||
738 | &omap2420_l4_core__timer8, | ||
739 | }; | ||
740 | |||
741 | /* timer8 hwmod */ | ||
742 | static struct omap_hwmod omap2420_timer8_hwmod = { | ||
743 | .name = "timer8", | ||
744 | .mpu_irqs = omap2420_timer8_mpu_irqs, | ||
745 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs), | ||
746 | .main_clk = "gpt8_fck", | ||
747 | .prcm = { | ||
748 | .omap2 = { | ||
749 | .prcm_reg_id = 1, | ||
750 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | ||
751 | .module_offs = CORE_MOD, | ||
752 | .idlest_reg_id = 1, | ||
753 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | ||
754 | }, | ||
755 | }, | ||
756 | .slaves = omap2420_timer8_slaves, | ||
757 | .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), | ||
758 | .class = &omap2420_timer_hwmod_class, | ||
759 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
760 | }; | ||
761 | |||
762 | /* timer9 */ | ||
763 | static struct omap_hwmod omap2420_timer9_hwmod; | ||
764 | static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { | ||
765 | { .irq = 45, }, | ||
766 | }; | ||
767 | |||
768 | static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = { | ||
769 | { | ||
770 | .pa_start = 0x48084000, | ||
771 | .pa_end = 0x48084000 + SZ_1K - 1, | ||
772 | .flags = ADDR_TYPE_RT | ||
773 | }, | ||
774 | }; | ||
775 | |||
776 | /* l4_core -> timer9 */ | ||
777 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { | ||
778 | .master = &omap2420_l4_core_hwmod, | ||
779 | .slave = &omap2420_timer9_hwmod, | ||
780 | .clk = "gpt9_ick", | ||
781 | .addr = omap2420_timer9_addrs, | ||
782 | .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs), | ||
783 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
784 | }; | ||
785 | |||
786 | /* timer9 slave port */ | ||
787 | static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { | ||
788 | &omap2420_l4_core__timer9, | ||
789 | }; | ||
790 | |||
791 | /* timer9 hwmod */ | ||
792 | static struct omap_hwmod omap2420_timer9_hwmod = { | ||
793 | .name = "timer9", | ||
794 | .mpu_irqs = omap2420_timer9_mpu_irqs, | ||
795 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs), | ||
796 | .main_clk = "gpt9_fck", | ||
797 | .prcm = { | ||
798 | .omap2 = { | ||
799 | .prcm_reg_id = 1, | ||
800 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | ||
801 | .module_offs = CORE_MOD, | ||
802 | .idlest_reg_id = 1, | ||
803 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | ||
804 | }, | ||
805 | }, | ||
806 | .slaves = omap2420_timer9_slaves, | ||
807 | .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), | ||
808 | .class = &omap2420_timer_hwmod_class, | ||
809 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
810 | }; | ||
811 | |||
812 | /* timer10 */ | ||
813 | static struct omap_hwmod omap2420_timer10_hwmod; | ||
814 | static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { | ||
815 | { .irq = 46, }, | ||
816 | }; | ||
817 | |||
818 | static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = { | ||
819 | { | ||
820 | .pa_start = 0x48086000, | ||
821 | .pa_end = 0x48086000 + SZ_1K - 1, | ||
822 | .flags = ADDR_TYPE_RT | ||
823 | }, | ||
824 | }; | ||
825 | |||
826 | /* l4_core -> timer10 */ | ||
827 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { | ||
828 | .master = &omap2420_l4_core_hwmod, | ||
829 | .slave = &omap2420_timer10_hwmod, | ||
830 | .clk = "gpt10_ick", | ||
831 | .addr = omap2420_timer10_addrs, | ||
832 | .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs), | ||
833 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
834 | }; | ||
835 | |||
836 | /* timer10 slave port */ | ||
837 | static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { | ||
838 | &omap2420_l4_core__timer10, | ||
839 | }; | ||
840 | |||
841 | /* timer10 hwmod */ | ||
842 | static struct omap_hwmod omap2420_timer10_hwmod = { | ||
843 | .name = "timer10", | ||
844 | .mpu_irqs = omap2420_timer10_mpu_irqs, | ||
845 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs), | ||
846 | .main_clk = "gpt10_fck", | ||
847 | .prcm = { | ||
848 | .omap2 = { | ||
849 | .prcm_reg_id = 1, | ||
850 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | ||
851 | .module_offs = CORE_MOD, | ||
852 | .idlest_reg_id = 1, | ||
853 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | ||
854 | }, | ||
855 | }, | ||
856 | .slaves = omap2420_timer10_slaves, | ||
857 | .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), | ||
858 | .class = &omap2420_timer_hwmod_class, | ||
859 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
860 | }; | ||
861 | |||
862 | /* timer11 */ | ||
863 | static struct omap_hwmod omap2420_timer11_hwmod; | ||
864 | static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { | ||
865 | { .irq = 47, }, | ||
866 | }; | ||
867 | |||
868 | static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = { | ||
869 | { | ||
870 | .pa_start = 0x48088000, | ||
871 | .pa_end = 0x48088000 + SZ_1K - 1, | ||
872 | .flags = ADDR_TYPE_RT | ||
873 | }, | ||
874 | }; | ||
875 | |||
876 | /* l4_core -> timer11 */ | ||
877 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { | ||
878 | .master = &omap2420_l4_core_hwmod, | ||
879 | .slave = &omap2420_timer11_hwmod, | ||
880 | .clk = "gpt11_ick", | ||
881 | .addr = omap2420_timer11_addrs, | ||
882 | .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs), | ||
883 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
884 | }; | ||
885 | |||
886 | /* timer11 slave port */ | ||
887 | static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { | ||
888 | &omap2420_l4_core__timer11, | ||
889 | }; | ||
890 | |||
891 | /* timer11 hwmod */ | ||
892 | static struct omap_hwmod omap2420_timer11_hwmod = { | ||
893 | .name = "timer11", | ||
894 | .mpu_irqs = omap2420_timer11_mpu_irqs, | ||
895 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs), | ||
896 | .main_clk = "gpt11_fck", | ||
897 | .prcm = { | ||
898 | .omap2 = { | ||
899 | .prcm_reg_id = 1, | ||
900 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | ||
901 | .module_offs = CORE_MOD, | ||
902 | .idlest_reg_id = 1, | ||
903 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | ||
904 | }, | ||
905 | }, | ||
906 | .slaves = omap2420_timer11_slaves, | ||
907 | .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), | ||
908 | .class = &omap2420_timer_hwmod_class, | ||
909 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
910 | }; | ||
911 | |||
912 | /* timer12 */ | ||
913 | static struct omap_hwmod omap2420_timer12_hwmod; | ||
914 | static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { | ||
915 | { .irq = 48, }, | ||
916 | }; | ||
917 | |||
918 | static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = { | ||
919 | { | ||
920 | .pa_start = 0x4808a000, | ||
921 | .pa_end = 0x4808a000 + SZ_1K - 1, | ||
922 | .flags = ADDR_TYPE_RT | ||
923 | }, | ||
924 | }; | ||
925 | |||
926 | /* l4_core -> timer12 */ | ||
927 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { | ||
928 | .master = &omap2420_l4_core_hwmod, | ||
929 | .slave = &omap2420_timer12_hwmod, | ||
930 | .clk = "gpt12_ick", | ||
931 | .addr = omap2420_timer12_addrs, | ||
932 | .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs), | ||
933 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
934 | }; | ||
935 | |||
936 | /* timer12 slave port */ | ||
937 | static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { | ||
938 | &omap2420_l4_core__timer12, | ||
939 | }; | ||
940 | |||
941 | /* timer12 hwmod */ | ||
942 | static struct omap_hwmod omap2420_timer12_hwmod = { | ||
943 | .name = "timer12", | ||
944 | .mpu_irqs = omap2420_timer12_mpu_irqs, | ||
945 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs), | ||
946 | .main_clk = "gpt12_fck", | ||
947 | .prcm = { | ||
948 | .omap2 = { | ||
949 | .prcm_reg_id = 1, | ||
950 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | ||
951 | .module_offs = CORE_MOD, | ||
952 | .idlest_reg_id = 1, | ||
953 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | ||
954 | }, | ||
955 | }, | ||
956 | .slaves = omap2420_timer12_slaves, | ||
957 | .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), | ||
958 | .class = &omap2420_timer_hwmod_class, | ||
959 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
960 | }; | ||
961 | |||
282 | /* l4_wkup -> wd_timer2 */ | 962 | /* l4_wkup -> wd_timer2 */ |
283 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { | 963 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
284 | { | 964 | { |
@@ -470,6 +1150,292 @@ static struct omap_hwmod omap2420_uart3_hwmod = { | |||
470 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 1150 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
471 | }; | 1151 | }; |
472 | 1152 | ||
1153 | /* | ||
1154 | * 'dss' class | ||
1155 | * display sub-system | ||
1156 | */ | ||
1157 | |||
1158 | static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { | ||
1159 | .rev_offs = 0x0000, | ||
1160 | .sysc_offs = 0x0010, | ||
1161 | .syss_offs = 0x0014, | ||
1162 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
1163 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1164 | }; | ||
1165 | |||
1166 | static struct omap_hwmod_class omap2420_dss_hwmod_class = { | ||
1167 | .name = "dss", | ||
1168 | .sysc = &omap2420_dss_sysc, | ||
1169 | }; | ||
1170 | |||
1171 | /* dss */ | ||
1172 | static struct omap_hwmod_irq_info omap2420_dss_irqs[] = { | ||
1173 | { .irq = 25 }, | ||
1174 | }; | ||
1175 | |||
1176 | static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { | ||
1177 | { .name = "dispc", .dma_req = 5 }, | ||
1178 | }; | ||
1179 | |||
1180 | /* dss */ | ||
1181 | /* dss master ports */ | ||
1182 | static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { | ||
1183 | &omap2420_dss__l3, | ||
1184 | }; | ||
1185 | |||
1186 | static struct omap_hwmod_addr_space omap2420_dss_addrs[] = { | ||
1187 | { | ||
1188 | .pa_start = 0x48050000, | ||
1189 | .pa_end = 0x480503FF, | ||
1190 | .flags = ADDR_TYPE_RT | ||
1191 | }, | ||
1192 | }; | ||
1193 | |||
1194 | /* l4_core -> dss */ | ||
1195 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { | ||
1196 | .master = &omap2420_l4_core_hwmod, | ||
1197 | .slave = &omap2420_dss_core_hwmod, | ||
1198 | .clk = "dss_ick", | ||
1199 | .addr = omap2420_dss_addrs, | ||
1200 | .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs), | ||
1201 | .fw = { | ||
1202 | .omap2 = { | ||
1203 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | ||
1204 | .flags = OMAP_FIREWALL_L4, | ||
1205 | } | ||
1206 | }, | ||
1207 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1208 | }; | ||
1209 | |||
1210 | /* dss slave ports */ | ||
1211 | static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { | ||
1212 | &omap2420_l4_core__dss, | ||
1213 | }; | ||
1214 | |||
1215 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | ||
1216 | { .role = "tv_clk", .clk = "dss_54m_fck" }, | ||
1217 | { .role = "sys_clk", .clk = "dss2_fck" }, | ||
1218 | }; | ||
1219 | |||
1220 | static struct omap_hwmod omap2420_dss_core_hwmod = { | ||
1221 | .name = "dss_core", | ||
1222 | .class = &omap2420_dss_hwmod_class, | ||
1223 | .main_clk = "dss1_fck", /* instead of dss_fck */ | ||
1224 | .mpu_irqs = omap2420_dss_irqs, | ||
1225 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs), | ||
1226 | .sdma_reqs = omap2420_dss_sdma_chs, | ||
1227 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), | ||
1228 | .prcm = { | ||
1229 | .omap2 = { | ||
1230 | .prcm_reg_id = 1, | ||
1231 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
1232 | .module_offs = CORE_MOD, | ||
1233 | .idlest_reg_id = 1, | ||
1234 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | ||
1235 | }, | ||
1236 | }, | ||
1237 | .opt_clks = dss_opt_clks, | ||
1238 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | ||
1239 | .slaves = omap2420_dss_slaves, | ||
1240 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), | ||
1241 | .masters = omap2420_dss_masters, | ||
1242 | .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), | ||
1243 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
1244 | .flags = HWMOD_NO_IDLEST, | ||
1245 | }; | ||
1246 | |||
1247 | /* | ||
1248 | * 'dispc' class | ||
1249 | * display controller | ||
1250 | */ | ||
1251 | |||
1252 | static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { | ||
1253 | .rev_offs = 0x0000, | ||
1254 | .sysc_offs = 0x0010, | ||
1255 | .syss_offs = 0x0014, | ||
1256 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | ||
1257 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
1258 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1259 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
1260 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1261 | }; | ||
1262 | |||
1263 | static struct omap_hwmod_class omap2420_dispc_hwmod_class = { | ||
1264 | .name = "dispc", | ||
1265 | .sysc = &omap2420_dispc_sysc, | ||
1266 | }; | ||
1267 | |||
1268 | static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { | ||
1269 | { | ||
1270 | .pa_start = 0x48050400, | ||
1271 | .pa_end = 0x480507FF, | ||
1272 | .flags = ADDR_TYPE_RT | ||
1273 | }, | ||
1274 | }; | ||
1275 | |||
1276 | /* l4_core -> dss_dispc */ | ||
1277 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { | ||
1278 | .master = &omap2420_l4_core_hwmod, | ||
1279 | .slave = &omap2420_dss_dispc_hwmod, | ||
1280 | .clk = "dss_ick", | ||
1281 | .addr = omap2420_dss_dispc_addrs, | ||
1282 | .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs), | ||
1283 | .fw = { | ||
1284 | .omap2 = { | ||
1285 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, | ||
1286 | .flags = OMAP_FIREWALL_L4, | ||
1287 | } | ||
1288 | }, | ||
1289 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1290 | }; | ||
1291 | |||
1292 | /* dss_dispc slave ports */ | ||
1293 | static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { | ||
1294 | &omap2420_l4_core__dss_dispc, | ||
1295 | }; | ||
1296 | |||
1297 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { | ||
1298 | .name = "dss_dispc", | ||
1299 | .class = &omap2420_dispc_hwmod_class, | ||
1300 | .main_clk = "dss1_fck", | ||
1301 | .prcm = { | ||
1302 | .omap2 = { | ||
1303 | .prcm_reg_id = 1, | ||
1304 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
1305 | .module_offs = CORE_MOD, | ||
1306 | .idlest_reg_id = 1, | ||
1307 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | ||
1308 | }, | ||
1309 | }, | ||
1310 | .slaves = omap2420_dss_dispc_slaves, | ||
1311 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), | ||
1312 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
1313 | .flags = HWMOD_NO_IDLEST, | ||
1314 | }; | ||
1315 | |||
1316 | /* | ||
1317 | * 'rfbi' class | ||
1318 | * remote frame buffer interface | ||
1319 | */ | ||
1320 | |||
1321 | static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { | ||
1322 | .rev_offs = 0x0000, | ||
1323 | .sysc_offs = 0x0010, | ||
1324 | .syss_offs = 0x0014, | ||
1325 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
1326 | SYSC_HAS_AUTOIDLE), | ||
1327 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1328 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1329 | }; | ||
1330 | |||
1331 | static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { | ||
1332 | .name = "rfbi", | ||
1333 | .sysc = &omap2420_rfbi_sysc, | ||
1334 | }; | ||
1335 | |||
1336 | static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = { | ||
1337 | { | ||
1338 | .pa_start = 0x48050800, | ||
1339 | .pa_end = 0x48050BFF, | ||
1340 | .flags = ADDR_TYPE_RT | ||
1341 | }, | ||
1342 | }; | ||
1343 | |||
1344 | /* l4_core -> dss_rfbi */ | ||
1345 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { | ||
1346 | .master = &omap2420_l4_core_hwmod, | ||
1347 | .slave = &omap2420_dss_rfbi_hwmod, | ||
1348 | .clk = "dss_ick", | ||
1349 | .addr = omap2420_dss_rfbi_addrs, | ||
1350 | .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs), | ||
1351 | .fw = { | ||
1352 | .omap2 = { | ||
1353 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | ||
1354 | .flags = OMAP_FIREWALL_L4, | ||
1355 | } | ||
1356 | }, | ||
1357 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1358 | }; | ||
1359 | |||
1360 | /* dss_rfbi slave ports */ | ||
1361 | static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { | ||
1362 | &omap2420_l4_core__dss_rfbi, | ||
1363 | }; | ||
1364 | |||
1365 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { | ||
1366 | .name = "dss_rfbi", | ||
1367 | .class = &omap2420_rfbi_hwmod_class, | ||
1368 | .main_clk = "dss1_fck", | ||
1369 | .prcm = { | ||
1370 | .omap2 = { | ||
1371 | .prcm_reg_id = 1, | ||
1372 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
1373 | .module_offs = CORE_MOD, | ||
1374 | }, | ||
1375 | }, | ||
1376 | .slaves = omap2420_dss_rfbi_slaves, | ||
1377 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), | ||
1378 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
1379 | .flags = HWMOD_NO_IDLEST, | ||
1380 | }; | ||
1381 | |||
1382 | /* | ||
1383 | * 'venc' class | ||
1384 | * video encoder | ||
1385 | */ | ||
1386 | |||
1387 | static struct omap_hwmod_class omap2420_venc_hwmod_class = { | ||
1388 | .name = "venc", | ||
1389 | }; | ||
1390 | |||
1391 | /* dss_venc */ | ||
1392 | static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = { | ||
1393 | { | ||
1394 | .pa_start = 0x48050C00, | ||
1395 | .pa_end = 0x48050FFF, | ||
1396 | .flags = ADDR_TYPE_RT | ||
1397 | }, | ||
1398 | }; | ||
1399 | |||
1400 | /* l4_core -> dss_venc */ | ||
1401 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { | ||
1402 | .master = &omap2420_l4_core_hwmod, | ||
1403 | .slave = &omap2420_dss_venc_hwmod, | ||
1404 | .clk = "dss_54m_fck", | ||
1405 | .addr = omap2420_dss_venc_addrs, | ||
1406 | .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs), | ||
1407 | .fw = { | ||
1408 | .omap2 = { | ||
1409 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, | ||
1410 | .flags = OMAP_FIREWALL_L4, | ||
1411 | } | ||
1412 | }, | ||
1413 | .flags = OCPIF_SWSUP_IDLE, | ||
1414 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1415 | }; | ||
1416 | |||
1417 | /* dss_venc slave ports */ | ||
1418 | static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { | ||
1419 | &omap2420_l4_core__dss_venc, | ||
1420 | }; | ||
1421 | |||
1422 | static struct omap_hwmod omap2420_dss_venc_hwmod = { | ||
1423 | .name = "dss_venc", | ||
1424 | .class = &omap2420_venc_hwmod_class, | ||
1425 | .main_clk = "dss1_fck", | ||
1426 | .prcm = { | ||
1427 | .omap2 = { | ||
1428 | .prcm_reg_id = 1, | ||
1429 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
1430 | .module_offs = CORE_MOD, | ||
1431 | }, | ||
1432 | }, | ||
1433 | .slaves = omap2420_dss_venc_slaves, | ||
1434 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), | ||
1435 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
1436 | .flags = HWMOD_NO_IDLEST, | ||
1437 | }; | ||
1438 | |||
473 | /* I2C common */ | 1439 | /* I2C common */ |
474 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | 1440 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
475 | .rev_offs = 0x00, | 1441 | .rev_offs = 0x00, |
@@ -864,16 +1830,342 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { | |||
864 | .flags = HWMOD_NO_IDLEST, | 1830 | .flags = HWMOD_NO_IDLEST, |
865 | }; | 1831 | }; |
866 | 1832 | ||
1833 | /* | ||
1834 | * 'mailbox' class | ||
1835 | * mailbox module allowing communication between the on-chip processors | ||
1836 | * using a queued mailbox-interrupt mechanism. | ||
1837 | */ | ||
1838 | |||
1839 | static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = { | ||
1840 | .rev_offs = 0x000, | ||
1841 | .sysc_offs = 0x010, | ||
1842 | .syss_offs = 0x014, | ||
1843 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
1844 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
1845 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1846 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1847 | }; | ||
1848 | |||
1849 | static struct omap_hwmod_class omap2420_mailbox_hwmod_class = { | ||
1850 | .name = "mailbox", | ||
1851 | .sysc = &omap2420_mailbox_sysc, | ||
1852 | }; | ||
1853 | |||
1854 | /* mailbox */ | ||
1855 | static struct omap_hwmod omap2420_mailbox_hwmod; | ||
1856 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { | ||
1857 | { .name = "dsp", .irq = 26 }, | ||
1858 | { .name = "iva", .irq = 34 }, | ||
1859 | }; | ||
1860 | |||
1861 | static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = { | ||
1862 | { | ||
1863 | .pa_start = 0x48094000, | ||
1864 | .pa_end = 0x480941ff, | ||
1865 | .flags = ADDR_TYPE_RT, | ||
1866 | }, | ||
1867 | }; | ||
1868 | |||
1869 | /* l4_core -> mailbox */ | ||
1870 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { | ||
1871 | .master = &omap2420_l4_core_hwmod, | ||
1872 | .slave = &omap2420_mailbox_hwmod, | ||
1873 | .addr = omap2420_mailbox_addrs, | ||
1874 | .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs), | ||
1875 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1876 | }; | ||
1877 | |||
1878 | /* mailbox slave ports */ | ||
1879 | static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { | ||
1880 | &omap2420_l4_core__mailbox, | ||
1881 | }; | ||
1882 | |||
1883 | static struct omap_hwmod omap2420_mailbox_hwmod = { | ||
1884 | .name = "mailbox", | ||
1885 | .class = &omap2420_mailbox_hwmod_class, | ||
1886 | .mpu_irqs = omap2420_mailbox_irqs, | ||
1887 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs), | ||
1888 | .main_clk = "mailboxes_ick", | ||
1889 | .prcm = { | ||
1890 | .omap2 = { | ||
1891 | .prcm_reg_id = 1, | ||
1892 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | ||
1893 | .module_offs = CORE_MOD, | ||
1894 | .idlest_reg_id = 1, | ||
1895 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | ||
1896 | }, | ||
1897 | }, | ||
1898 | .slaves = omap2420_mailbox_slaves, | ||
1899 | .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), | ||
1900 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
1901 | }; | ||
1902 | |||
1903 | /* | ||
1904 | * 'mcspi' class | ||
1905 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | ||
1906 | * bus | ||
1907 | */ | ||
1908 | |||
1909 | static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { | ||
1910 | .rev_offs = 0x0000, | ||
1911 | .sysc_offs = 0x0010, | ||
1912 | .syss_offs = 0x0014, | ||
1913 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
1914 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | ||
1915 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | ||
1916 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1917 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1918 | }; | ||
1919 | |||
1920 | static struct omap_hwmod_class omap2420_mcspi_class = { | ||
1921 | .name = "mcspi", | ||
1922 | .sysc = &omap2420_mcspi_sysc, | ||
1923 | .rev = OMAP2_MCSPI_REV, | ||
1924 | }; | ||
1925 | |||
1926 | /* mcspi1 */ | ||
1927 | static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { | ||
1928 | { .irq = 65 }, | ||
1929 | }; | ||
1930 | |||
1931 | static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { | ||
1932 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ | ||
1933 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ | ||
1934 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ | ||
1935 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ | ||
1936 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ | ||
1937 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ | ||
1938 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ | ||
1939 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ | ||
1940 | }; | ||
1941 | |||
1942 | static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { | ||
1943 | &omap2420_l4_core__mcspi1, | ||
1944 | }; | ||
1945 | |||
1946 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | ||
1947 | .num_chipselect = 4, | ||
1948 | }; | ||
1949 | |||
1950 | static struct omap_hwmod omap2420_mcspi1_hwmod = { | ||
1951 | .name = "mcspi1_hwmod", | ||
1952 | .mpu_irqs = omap2420_mcspi1_mpu_irqs, | ||
1953 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), | ||
1954 | .sdma_reqs = omap2420_mcspi1_sdma_reqs, | ||
1955 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), | ||
1956 | .main_clk = "mcspi1_fck", | ||
1957 | .prcm = { | ||
1958 | .omap2 = { | ||
1959 | .module_offs = CORE_MOD, | ||
1960 | .prcm_reg_id = 1, | ||
1961 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | ||
1962 | .idlest_reg_id = 1, | ||
1963 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | ||
1964 | }, | ||
1965 | }, | ||
1966 | .slaves = omap2420_mcspi1_slaves, | ||
1967 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), | ||
1968 | .class = &omap2420_mcspi_class, | ||
1969 | .dev_attr = &omap_mcspi1_dev_attr, | ||
1970 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
1971 | }; | ||
1972 | |||
1973 | /* mcspi2 */ | ||
1974 | static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { | ||
1975 | { .irq = 66 }, | ||
1976 | }; | ||
1977 | |||
1978 | static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { | ||
1979 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ | ||
1980 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ | ||
1981 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ | ||
1982 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ | ||
1983 | }; | ||
1984 | |||
1985 | static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { | ||
1986 | &omap2420_l4_core__mcspi2, | ||
1987 | }; | ||
1988 | |||
1989 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | ||
1990 | .num_chipselect = 2, | ||
1991 | }; | ||
1992 | |||
1993 | static struct omap_hwmod omap2420_mcspi2_hwmod = { | ||
1994 | .name = "mcspi2_hwmod", | ||
1995 | .mpu_irqs = omap2420_mcspi2_mpu_irqs, | ||
1996 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), | ||
1997 | .sdma_reqs = omap2420_mcspi2_sdma_reqs, | ||
1998 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), | ||
1999 | .main_clk = "mcspi2_fck", | ||
2000 | .prcm = { | ||
2001 | .omap2 = { | ||
2002 | .module_offs = CORE_MOD, | ||
2003 | .prcm_reg_id = 1, | ||
2004 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | ||
2005 | .idlest_reg_id = 1, | ||
2006 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | ||
2007 | }, | ||
2008 | }, | ||
2009 | .slaves = omap2420_mcspi2_slaves, | ||
2010 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), | ||
2011 | .class = &omap2420_mcspi_class, | ||
2012 | .dev_attr = &omap_mcspi2_dev_attr, | ||
2013 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
2014 | }; | ||
2015 | |||
2016 | /* | ||
2017 | * 'mcbsp' class | ||
2018 | * multi channel buffered serial port controller | ||
2019 | */ | ||
2020 | |||
2021 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | ||
2022 | .name = "mcbsp", | ||
2023 | }; | ||
2024 | |||
2025 | /* mcbsp1 */ | ||
2026 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | ||
2027 | { .name = "tx", .irq = 59 }, | ||
2028 | { .name = "rx", .irq = 60 }, | ||
2029 | }; | ||
2030 | |||
2031 | static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = { | ||
2032 | { .name = "rx", .dma_req = 32 }, | ||
2033 | { .name = "tx", .dma_req = 31 }, | ||
2034 | }; | ||
2035 | |||
2036 | static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = { | ||
2037 | { | ||
2038 | .name = "mpu", | ||
2039 | .pa_start = 0x48074000, | ||
2040 | .pa_end = 0x480740ff, | ||
2041 | .flags = ADDR_TYPE_RT | ||
2042 | }, | ||
2043 | }; | ||
2044 | |||
2045 | /* l4_core -> mcbsp1 */ | ||
2046 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { | ||
2047 | .master = &omap2420_l4_core_hwmod, | ||
2048 | .slave = &omap2420_mcbsp1_hwmod, | ||
2049 | .clk = "mcbsp1_ick", | ||
2050 | .addr = omap2420_mcbsp1_addrs, | ||
2051 | .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs), | ||
2052 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2053 | }; | ||
2054 | |||
2055 | /* mcbsp1 slave ports */ | ||
2056 | static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { | ||
2057 | &omap2420_l4_core__mcbsp1, | ||
2058 | }; | ||
2059 | |||
2060 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { | ||
2061 | .name = "mcbsp1", | ||
2062 | .class = &omap2420_mcbsp_hwmod_class, | ||
2063 | .mpu_irqs = omap2420_mcbsp1_irqs, | ||
2064 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), | ||
2065 | .sdma_reqs = omap2420_mcbsp1_sdma_chs, | ||
2066 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs), | ||
2067 | .main_clk = "mcbsp1_fck", | ||
2068 | .prcm = { | ||
2069 | .omap2 = { | ||
2070 | .prcm_reg_id = 1, | ||
2071 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | ||
2072 | .module_offs = CORE_MOD, | ||
2073 | .idlest_reg_id = 1, | ||
2074 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | ||
2075 | }, | ||
2076 | }, | ||
2077 | .slaves = omap2420_mcbsp1_slaves, | ||
2078 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), | ||
2079 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
2080 | }; | ||
2081 | |||
2082 | /* mcbsp2 */ | ||
2083 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { | ||
2084 | { .name = "tx", .irq = 62 }, | ||
2085 | { .name = "rx", .irq = 63 }, | ||
2086 | }; | ||
2087 | |||
2088 | static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = { | ||
2089 | { .name = "rx", .dma_req = 34 }, | ||
2090 | { .name = "tx", .dma_req = 33 }, | ||
2091 | }; | ||
2092 | |||
2093 | static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = { | ||
2094 | { | ||
2095 | .name = "mpu", | ||
2096 | .pa_start = 0x48076000, | ||
2097 | .pa_end = 0x480760ff, | ||
2098 | .flags = ADDR_TYPE_RT | ||
2099 | }, | ||
2100 | }; | ||
2101 | |||
2102 | /* l4_core -> mcbsp2 */ | ||
2103 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { | ||
2104 | .master = &omap2420_l4_core_hwmod, | ||
2105 | .slave = &omap2420_mcbsp2_hwmod, | ||
2106 | .clk = "mcbsp2_ick", | ||
2107 | .addr = omap2420_mcbsp2_addrs, | ||
2108 | .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs), | ||
2109 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2110 | }; | ||
2111 | |||
2112 | /* mcbsp2 slave ports */ | ||
2113 | static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { | ||
2114 | &omap2420_l4_core__mcbsp2, | ||
2115 | }; | ||
2116 | |||
2117 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { | ||
2118 | .name = "mcbsp2", | ||
2119 | .class = &omap2420_mcbsp_hwmod_class, | ||
2120 | .mpu_irqs = omap2420_mcbsp2_irqs, | ||
2121 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), | ||
2122 | .sdma_reqs = omap2420_mcbsp2_sdma_chs, | ||
2123 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs), | ||
2124 | .main_clk = "mcbsp2_fck", | ||
2125 | .prcm = { | ||
2126 | .omap2 = { | ||
2127 | .prcm_reg_id = 1, | ||
2128 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | ||
2129 | .module_offs = CORE_MOD, | ||
2130 | .idlest_reg_id = 1, | ||
2131 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | ||
2132 | }, | ||
2133 | }, | ||
2134 | .slaves = omap2420_mcbsp2_slaves, | ||
2135 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), | ||
2136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
2137 | }; | ||
2138 | |||
867 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { | 2139 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
868 | &omap2420_l3_main_hwmod, | 2140 | &omap2420_l3_main_hwmod, |
869 | &omap2420_l4_core_hwmod, | 2141 | &omap2420_l4_core_hwmod, |
870 | &omap2420_l4_wkup_hwmod, | 2142 | &omap2420_l4_wkup_hwmod, |
871 | &omap2420_mpu_hwmod, | 2143 | &omap2420_mpu_hwmod, |
872 | &omap2420_iva_hwmod, | 2144 | &omap2420_iva_hwmod, |
2145 | |||
2146 | &omap2420_timer1_hwmod, | ||
2147 | &omap2420_timer2_hwmod, | ||
2148 | &omap2420_timer3_hwmod, | ||
2149 | &omap2420_timer4_hwmod, | ||
2150 | &omap2420_timer5_hwmod, | ||
2151 | &omap2420_timer6_hwmod, | ||
2152 | &omap2420_timer7_hwmod, | ||
2153 | &omap2420_timer8_hwmod, | ||
2154 | &omap2420_timer9_hwmod, | ||
2155 | &omap2420_timer10_hwmod, | ||
2156 | &omap2420_timer11_hwmod, | ||
2157 | &omap2420_timer12_hwmod, | ||
2158 | |||
873 | &omap2420_wd_timer2_hwmod, | 2159 | &omap2420_wd_timer2_hwmod, |
874 | &omap2420_uart1_hwmod, | 2160 | &omap2420_uart1_hwmod, |
875 | &omap2420_uart2_hwmod, | 2161 | &omap2420_uart2_hwmod, |
876 | &omap2420_uart3_hwmod, | 2162 | &omap2420_uart3_hwmod, |
2163 | /* dss class */ | ||
2164 | &omap2420_dss_core_hwmod, | ||
2165 | &omap2420_dss_dispc_hwmod, | ||
2166 | &omap2420_dss_rfbi_hwmod, | ||
2167 | &omap2420_dss_venc_hwmod, | ||
2168 | /* i2c class */ | ||
877 | &omap2420_i2c1_hwmod, | 2169 | &omap2420_i2c1_hwmod, |
878 | &omap2420_i2c2_hwmod, | 2170 | &omap2420_i2c2_hwmod, |
879 | 2171 | ||
@@ -885,10 +2177,21 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { | |||
885 | 2177 | ||
886 | /* dma_system class*/ | 2178 | /* dma_system class*/ |
887 | &omap2420_dma_system_hwmod, | 2179 | &omap2420_dma_system_hwmod, |
2180 | |||
2181 | /* mailbox class */ | ||
2182 | &omap2420_mailbox_hwmod, | ||
2183 | |||
2184 | /* mcbsp class */ | ||
2185 | &omap2420_mcbsp1_hwmod, | ||
2186 | &omap2420_mcbsp2_hwmod, | ||
2187 | |||
2188 | /* mcspi class */ | ||
2189 | &omap2420_mcspi1_hwmod, | ||
2190 | &omap2420_mcspi2_hwmod, | ||
888 | NULL, | 2191 | NULL, |
889 | }; | 2192 | }; |
890 | 2193 | ||
891 | int __init omap2420_hwmod_init(void) | 2194 | int __init omap2420_hwmod_init(void) |
892 | { | 2195 | { |
893 | return omap_hwmod_init(omap2420_hwmods); | 2196 | return omap_hwmod_register(omap2420_hwmods); |
894 | } | 2197 | } |