1 files changed, 18 insertions, 20 deletions

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 48ee295db275..38153e5fbca0 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -17,20 +17,17 @@
  */
 #include <linux/init.h>
 #include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
+#include <asm/cacheflush.h>
 #include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
-
-/* Registers used for communicating startup information */
-#define OMAP4_AUXCOREBOOT_REG0          (OMAP44XX_VA_WKUPGEN_BASE + 0x800)
-#define OMAP4_AUXCOREBOOT_REG1          (OMAP44XX_VA_WKUPGEN_BASE + 0x804)
+#include <plat/common.h>
 
 /* SCU base address */
-static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE;
+static void __iomem *scu_base;
 
 /*
  * Use SCU config register to count number of cores
@@ -53,8 +50,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-
-        gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+        gic_cpu_init(0, gic_cpu_base_addr);
 
         /*
          * Synchronise with the boot thread.
@@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        unsigned long timeout;
-
         /*
          * Set synchronisation state between this boot processor
          * and the secondary one
@@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         spin_lock(&boot_lock);
 
         /*
-         * Update the AuxCoreBoot1 with boot state for secondary core.
+         * Update the AuxCoreBoot0 with boot state for secondary core.
          * omap_secondary_startup() routine will hold the secondary core till
          * the AuxCoreBoot1 register is updated with cpu state
          * A barrier is added to ensure that write buffer is drained
          */
-        __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1);
+        omap_modify_auxcoreboot0(0x200, 0x0);
+        flush_cache_all();
         smp_wmb();
 
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout))
-                ;
-
         /*
          * Now the secondary core is starting up let it run its
          * calibrations, then wait for it to finish
@@ -99,17 +90,18 @@ static void __init wakeup_secondary(void)
 {
         /*
          * Write the address of secondary startup routine into the
-         * AuxCoreBoot0 where ROM code will jump and start executing
+         * AuxCoreBoot1 where ROM code will jump and start executing
          * on secondary core once out of WFE
          * A barrier is added to ensure that write buffer is drained
          */
-        __raw_writel(virt_to_phys(omap_secondary_startup),         \
-                                        OMAP4_AUXCOREBOOT_REG0);
+        omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
         smp_wmb();
 
         /*
          * Send a 'sev' to wake the secondary core from WFE.
+         * Drain the outstanding writes to memory
          */
+        dsb();
         set_event();
         mb();
 }
@@ -120,7 +112,13 @@ static void __init wakeup_secondary(void)
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i, ncores = get_core_count();
+        unsigned int i, ncores;
+
+        /* Never released */
+        scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
+        BUG_ON(!scu_base);
+
+        ncores = get_core_count();
 
         for (i = 0; i < ncores; i++)
                 set_cpu_possible(i, true);