diff options
Diffstat (limited to 'arch/arm/mach-omap2/mcbsp.c')
-rw-r--r-- | arch/arm/mach-omap2/mcbsp.c | 105 |
1 files changed, 73 insertions, 32 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 467aae245781..f9c9df5b5ff1 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
@@ -23,29 +23,86 @@ | |||
23 | #include <plat/cpu.h> | 23 | #include <plat/cpu.h> |
24 | #include <plat/mcbsp.h> | 24 | #include <plat/mcbsp.h> |
25 | 25 | ||
26 | #include "mux.h" | 26 | #include "control.h" |
27 | 27 | ||
28 | static void omap2_mcbsp2_mux_setup(void) | 28 | |
29 | /* McBSP internal signal muxing functions */ | ||
30 | |||
31 | void omap2_mcbsp1_mux_clkr_src(u8 mux) | ||
29 | { | 32 | { |
30 | omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); | 33 | u32 v; |
31 | omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); | 34 | |
32 | omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); | 35 | v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); |
33 | omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); | 36 | if (mux == CLKR_SRC_CLKR) |
34 | omap_mux_init_gpio(117, OMAP_PULL_ENA); | 37 | v &= ~OMAP2_MCBSP1_CLKR_MASK; |
35 | /* | 38 | else if (mux == CLKR_SRC_CLKX) |
36 | * TODO: Need to add MUX settings for OMAP 2430 SDP | 39 | v |= OMAP2_MCBSP1_CLKR_MASK; |
37 | */ | 40 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); |
38 | } | 41 | } |
42 | EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src); | ||
39 | 43 | ||
40 | static void omap2_mcbsp_request(unsigned int id) | 44 | void omap2_mcbsp1_mux_fsr_src(u8 mux) |
41 | { | 45 | { |
42 | if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) | 46 | u32 v; |
43 | omap2_mcbsp2_mux_setup(); | 47 | |
48 | v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
49 | if (mux == FSR_SRC_FSR) | ||
50 | v &= ~OMAP2_MCBSP1_FSR_MASK; | ||
51 | else if (mux == FSR_SRC_FSX) | ||
52 | v |= OMAP2_MCBSP1_FSR_MASK; | ||
53 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | ||
44 | } | 54 | } |
55 | EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); | ||
45 | 56 | ||
46 | static struct omap_mcbsp_ops omap2_mcbsp_ops = { | 57 | /* McBSP CLKS source switching function */ |
47 | .request = omap2_mcbsp_request, | 58 | |
48 | }; | 59 | int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) |
60 | { | ||
61 | struct omap_mcbsp *mcbsp; | ||
62 | struct clk *fck_src; | ||
63 | char *fck_src_name; | ||
64 | int r; | ||
65 | |||
66 | if (!omap_mcbsp_check_valid_id(id)) { | ||
67 | pr_err("%s: Invalid id (%d)\n", __func__, id + 1); | ||
68 | return -EINVAL; | ||
69 | } | ||
70 | mcbsp = id_to_mcbsp_ptr(id); | ||
71 | |||
72 | if (fck_src_id == MCBSP_CLKS_PAD_SRC) | ||
73 | fck_src_name = "pad_fck"; | ||
74 | else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) | ||
75 | fck_src_name = "prcm_fck"; | ||
76 | else | ||
77 | return -EINVAL; | ||
78 | |||
79 | fck_src = clk_get(mcbsp->dev, fck_src_name); | ||
80 | if (IS_ERR_OR_NULL(fck_src)) { | ||
81 | pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks", | ||
82 | fck_src_name); | ||
83 | return -EINVAL; | ||
84 | } | ||
85 | |||
86 | clk_disable(mcbsp->fclk); | ||
87 | |||
88 | r = clk_set_parent(mcbsp->fclk, fck_src); | ||
89 | if (IS_ERR_VALUE(r)) { | ||
90 | pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n", | ||
91 | "clks", fck_src_name); | ||
92 | clk_put(fck_src); | ||
93 | return -EINVAL; | ||
94 | } | ||
95 | |||
96 | clk_enable(mcbsp->fclk); | ||
97 | |||
98 | clk_put(fck_src); | ||
99 | |||
100 | return 0; | ||
101 | } | ||
102 | EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); | ||
103 | |||
104 | |||
105 | /* Platform data */ | ||
49 | 106 | ||
50 | #ifdef CONFIG_ARCH_OMAP2420 | 107 | #ifdef CONFIG_ARCH_OMAP2420 |
51 | static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | 108 | static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { |
@@ -55,7 +112,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
55 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, | 112 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, |
56 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 113 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
57 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 114 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
58 | .ops = &omap2_mcbsp_ops, | ||
59 | }, | 115 | }, |
60 | { | 116 | { |
61 | .phys_base = OMAP24XX_MCBSP2_BASE, | 117 | .phys_base = OMAP24XX_MCBSP2_BASE, |
@@ -63,7 +119,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
63 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, | 119 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, |
64 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 120 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
65 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 121 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
66 | .ops = &omap2_mcbsp_ops, | ||
67 | }, | 122 | }, |
68 | }; | 123 | }; |
69 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) | 124 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) |
@@ -82,7 +137,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
82 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, | 137 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, |
83 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 138 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
84 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 139 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
85 | .ops = &omap2_mcbsp_ops, | ||
86 | }, | 140 | }, |
87 | { | 141 | { |
88 | .phys_base = OMAP24XX_MCBSP2_BASE, | 142 | .phys_base = OMAP24XX_MCBSP2_BASE, |
@@ -90,7 +144,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
90 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, | 144 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, |
91 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 145 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
92 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 146 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
93 | .ops = &omap2_mcbsp_ops, | ||
94 | }, | 147 | }, |
95 | { | 148 | { |
96 | .phys_base = OMAP2430_MCBSP3_BASE, | 149 | .phys_base = OMAP2430_MCBSP3_BASE, |
@@ -98,7 +151,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
98 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, | 151 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, |
99 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 152 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
100 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 153 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
101 | .ops = &omap2_mcbsp_ops, | ||
102 | }, | 154 | }, |
103 | { | 155 | { |
104 | .phys_base = OMAP2430_MCBSP4_BASE, | 156 | .phys_base = OMAP2430_MCBSP4_BASE, |
@@ -106,7 +158,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
106 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, | 158 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, |
107 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 159 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
108 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 160 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
109 | .ops = &omap2_mcbsp_ops, | ||
110 | }, | 161 | }, |
111 | { | 162 | { |
112 | .phys_base = OMAP2430_MCBSP5_BASE, | 163 | .phys_base = OMAP2430_MCBSP5_BASE, |
@@ -114,7 +165,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
114 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, | 165 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, |
115 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 166 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
116 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 167 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
117 | .ops = &omap2_mcbsp_ops, | ||
118 | }, | 168 | }, |
119 | }; | 169 | }; |
120 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) | 170 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) |
@@ -133,7 +183,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
133 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, | 183 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, |
134 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 184 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
135 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 185 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
136 | .ops = &omap2_mcbsp_ops, | ||
137 | .buffer_size = 0x80, /* The FIFO has 128 locations */ | 186 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
138 | }, | 187 | }, |
139 | { | 188 | { |
@@ -143,7 +192,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
143 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, | 192 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, |
144 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 193 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
145 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 194 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
146 | .ops = &omap2_mcbsp_ops, | ||
147 | .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ | 195 | .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ |
148 | }, | 196 | }, |
149 | { | 197 | { |
@@ -153,7 +201,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
153 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, | 201 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, |
154 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 202 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
155 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 203 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
156 | .ops = &omap2_mcbsp_ops, | ||
157 | .buffer_size = 0x80, /* The FIFO has 128 locations */ | 204 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
158 | }, | 205 | }, |
159 | { | 206 | { |
@@ -162,7 +209,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
162 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, | 209 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, |
163 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 210 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
164 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 211 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
165 | .ops = &omap2_mcbsp_ops, | ||
166 | .buffer_size = 0x80, /* The FIFO has 128 locations */ | 212 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
167 | }, | 213 | }, |
168 | { | 214 | { |
@@ -171,7 +217,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
171 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, | 217 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, |
172 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 218 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
173 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 219 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
174 | .ops = &omap2_mcbsp_ops, | ||
175 | .buffer_size = 0x80, /* The FIFO has 128 locations */ | 220 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
176 | }, | 221 | }, |
177 | }; | 222 | }; |
@@ -189,28 +234,24 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { | |||
189 | .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, | 234 | .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, |
190 | .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, | 235 | .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, |
191 | .tx_irq = OMAP44XX_IRQ_MCBSP1, | 236 | .tx_irq = OMAP44XX_IRQ_MCBSP1, |
192 | .ops = &omap2_mcbsp_ops, | ||
193 | }, | 237 | }, |
194 | { | 238 | { |
195 | .phys_base = OMAP44XX_MCBSP2_BASE, | 239 | .phys_base = OMAP44XX_MCBSP2_BASE, |
196 | .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, | 240 | .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, |
197 | .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, | 241 | .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, |
198 | .tx_irq = OMAP44XX_IRQ_MCBSP2, | 242 | .tx_irq = OMAP44XX_IRQ_MCBSP2, |
199 | .ops = &omap2_mcbsp_ops, | ||
200 | }, | 243 | }, |
201 | { | 244 | { |
202 | .phys_base = OMAP44XX_MCBSP3_BASE, | 245 | .phys_base = OMAP44XX_MCBSP3_BASE, |
203 | .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, | 246 | .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, |
204 | .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, | 247 | .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, |
205 | .tx_irq = OMAP44XX_IRQ_MCBSP3, | 248 | .tx_irq = OMAP44XX_IRQ_MCBSP3, |
206 | .ops = &omap2_mcbsp_ops, | ||
207 | }, | 249 | }, |
208 | { | 250 | { |
209 | .phys_base = OMAP44XX_MCBSP4_BASE, | 251 | .phys_base = OMAP44XX_MCBSP4_BASE, |
210 | .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, | 252 | .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, |
211 | .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, | 253 | .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, |
212 | .tx_irq = OMAP44XX_IRQ_MCBSP4, | 254 | .tx_irq = OMAP44XX_IRQ_MCBSP4, |
213 | .ops = &omap2_mcbsp_ops, | ||
214 | }, | 255 | }, |
215 | }; | 256 | }; |
216 | #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) | 257 | #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) |