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-rw-r--r--arch/arm/mach-omap2/id.c305
1 files changed, 133 insertions, 172 deletions
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index bf45ff39a7b5..b0f8e7d62798 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,40 +22,15 @@
22#include <mach/control.h> 22#include <mach/control.h>
23#include <mach/cpu.h> 23#include <mach/cpu.h>
24 24
25static u32 class; 25static struct omap_chip_id omap_chip;
26static void __iomem *tap_base; 26static unsigned int omap_revision;
27static u16 tap_prod_id;
28
29#define OMAP_TAP_IDCODE 0x0204
30#define OMAP_TAP_DIE_ID_0 0x0218
31#define OMAP_TAP_DIE_ID_1 0x021C
32#define OMAP_TAP_DIE_ID_2 0x0220
33#define OMAP_TAP_DIE_ID_3 0x0224
34
35/* system_rev fields for OMAP2 processors:
36 * CPU id bits [31:16],
37 * CPU device type [15:12], (unprg,normal,POP)
38 * CPU revision [11:08]
39 * CPU class bits [07:00]
40 */
41
42struct omap_id {
43 u16 hawkeye; /* Silicon type (Hawkeye id) */
44 u8 dev; /* Device type from production_id reg */
45 u32 type; /* combined type id copied to system_rev */
46};
47 27
48/* Register values to detect the OMAP version */
49static struct omap_id omap_ids[] __initdata = {
50 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
51 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
52 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
53 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
54 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
55 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
56};
57 28
58static struct omap_chip_id omap_chip; 29unsigned int omap_rev(void)
30{
31 return omap_revision;
32}
33EXPORT_SYMBOL(omap_rev);
59 34
60/** 35/**
61 * omap_chip_is - test whether currently running OMAP matches a chip type 36 * omap_chip_is - test whether currently running OMAP matches a chip type
@@ -70,135 +45,41 @@ int omap_chip_is(struct omap_chip_id oci)
70} 45}
71EXPORT_SYMBOL(omap_chip_is); 46EXPORT_SYMBOL(omap_chip_is);
72 47
73static u32 __init read_tap_reg(int reg) 48/*----------------------------------------------------------------------------*/
74{
75 unsigned int regval = 0;
76 u32 cpuid;
77
78 /* Reading the IDCODE register on 3430 ES1 results in a
79 * data abort as the register is not exposed on the OCP
80 * Hence reading the Cortex Rev
81 */
82 cpuid = read_cpuid(CPUID_ID);
83
84 /* If the processor type is Cortex-A8 and the revision is 0x0
85 * it means its Cortex r0p0 which is 3430 ES1
86 */
87 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
88
89 if (reg == tap_prod_id) {
90 regval = 0x000F00F0;
91 goto out;
92 }
93
94 switch (reg) {
95 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
96 /* Making DevType as 0xF in ES1 to differ from ES2 */
97 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
98 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
99 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
100 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
101 }
102 } else
103 regval = __raw_readl(tap_base + reg);
104
105out:
106 return regval;
107
108}
109 49
110/* 50#define OMAP_TAP_IDCODE 0x0204
111 * _set_system_rev - set the system_rev global based on current OMAP chip type 51#define OMAP_TAP_DIE_ID_0 0x0218
112 * 52#define OMAP_TAP_DIE_ID_1 0x021C
113 * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx() 53#define OMAP_TAP_DIE_ID_2 0x0220
114 * macros. 54#define OMAP_TAP_DIE_ID_3 0x0224
115 */
116static void __init _set_system_rev(u32 type, u8 rev)
117{
118 u32 i, ctrl_status;
119
120 /*
121 * system_rev encoding is as follows
122 * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
123 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
124 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
125 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
126 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
127 * system_rev & 0x000000c0 -> IDCODE revision[6:7]
128 * system_rev & 0x0000003f -> sys_boot[0:5]
129 */
130 /* Embedding the ES revision info in type field */
131 system_rev = type;
132 /* Also add IDCODE revision info only two lower bits */
133 system_rev |= ((rev & 0x3) << 6);
134
135 /* Add in the device type and sys_boot fields (see above) */
136 if (cpu_is_omap24xx()) {
137 i = OMAP24XX_CONTROL_STATUS;
138 } else if (cpu_is_omap343x()) {
139 i = OMAP343X_CONTROL_STATUS;
140 } else {
141 printk(KERN_ERR "id: unknown CPU type\n");
142 BUG();
143 }
144 ctrl_status = omap_ctrl_readl(i);
145 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
146 OMAP2_SYSBOOT_4_MASK |
147 OMAP2_SYSBOOT_3_MASK |
148 OMAP2_SYSBOOT_2_MASK |
149 OMAP2_SYSBOOT_1_MASK |
150 OMAP2_SYSBOOT_0_MASK));
151 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
152}
153
154
155/*
156 * _set_omap_chip - set the omap_chip global based on OMAP chip type
157 *
158 * Build the omap_chip bits. This variable is used by powerdomain and
159 * clockdomain code to indicate whether structures are applicable for
160 * the current OMAP chip type by ANDing it against a 'platform' bitfield
161 * in the structure.
162 */
163static void __init _set_omap_chip(void)
164{
165 if (cpu_is_omap343x()) {
166
167 omap_chip.oc = CHIP_IS_OMAP3430;
168 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
169 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
170 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
171 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
172
173 } else if (cpu_is_omap243x()) {
174
175 /* Currently only supports 2430ES2.1 and 2430-all */
176 omap_chip.oc |= CHIP_IS_OMAP2430;
177
178 } else if (cpu_is_omap242x()) {
179
180 /* Currently only supports 2420ES2.1.1 and 2420-all */
181 omap_chip.oc |= CHIP_IS_OMAP2420;
182 55
183 } else { 56#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
184 57
185 /* Current CPU not supported by this code. */ 58struct omap_id {
186 printk(KERN_WARNING "OMAP chip type code does not yet support " 59 u16 hawkeye; /* Silicon type (Hawkeye id) */
187 "this CPU type.\n"); 60 u8 dev; /* Device type from production_id reg */
188 WARN_ON(1); 61 u32 type; /* Combined type id copied to omap_revision */
62};
189 63
190 } 64/* Register values to detect the OMAP version */
65static struct omap_id omap_ids[] __initdata = {
66 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
67 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
68 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
69 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
70 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
71 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
72};
191 73
192} 74static void __iomem *tap_base;
75static u16 tap_prod_id;
193 76
194void __init omap2_check_revision(void) 77void __init omap24xx_check_revision(void)
195{ 78{
196 int i, j; 79 int i, j;
197 u32 idcode; 80 u32 idcode, prod_id;
198 u32 prod_id;
199 u16 hawkeye; 81 u16 hawkeye;
200 u8 dev_type; 82 u8 dev_type, rev;
201 u8 rev;
202 83
203 idcode = read_tap_reg(OMAP_TAP_IDCODE); 84 idcode = read_tap_reg(OMAP_TAP_IDCODE);
204 prod_id = read_tap_reg(tap_prod_id); 85 prod_id = read_tap_reg(tap_prod_id);
@@ -220,18 +101,6 @@ void __init omap2_check_revision(void)
220 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 101 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
221 prod_id, dev_type); 102 prod_id, dev_type);
222 103
223 /*
224 * Detection for 34xx ES2.0 and above can be done with just
225 * hawkeye and rev. See TRM 1.5.2 Device Identification.
226 * Note that rev cannot be used directly as ES1.0 uses value 0.
227 */
228 if (hawkeye == 0xb7ae) {
229 system_rev = 0x34300000 | ((1 + rev) << 12);
230 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
231 _set_omap_chip();
232 return;
233 }
234
235 /* Check hawkeye ids */ 104 /* Check hawkeye ids */
236 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 105 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
237 if (hawkeye == omap_ids[i].hawkeye) 106 if (hawkeye == omap_ids[i].hawkeye)
@@ -255,23 +124,115 @@ void __init omap2_check_revision(void)
255 j = i; 124 j = i;
256 } 125 }
257 126
258 _set_system_rev(omap_ids[j].type, rev); 127 pr_info("OMAP%04x", omap_rev() >> 16);
128 if ((omap_rev() >> 8) & 0x0f)
129 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
130 pr_info("\n");
131}
259 132
260 _set_omap_chip(); 133void __init omap34xx_check_revision(void)
134{
135 u32 cpuid, idcode;
136 u16 hawkeye;
137 u8 rev;
138 char *rev_name = "ES1.0";
261 139
262 pr_info("OMAP%04x", system_rev >> 16); 140 /*
263 if ((system_rev >> 8) & 0x0f) 141 * We cannot access revision registers on ES1.0.
264 pr_info("ES%x", (system_rev >> 12) & 0xf); 142 * If the processor type is Cortex-A8 and the revision is 0x0
265 pr_info("\n"); 143 * it means its Cortex r0p0 which is 3430 ES1.0.
144 */
145 cpuid = read_cpuid(CPUID_ID);
146 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
147 omap_revision = OMAP3430_REV_ES1_0;
148 goto out;
149 }
266 150
151 /*
152 * Detection for 34xx ES2.0 and above can be done with just
153 * hawkeye and rev. See TRM 1.5.2 Device Identification.
154 * Note that rev does not map directly to our defined processor
155 * revision numbers as ES1.0 uses value 0.
156 */
157 idcode = read_tap_reg(OMAP_TAP_IDCODE);
158 hawkeye = (idcode >> 12) & 0xffff;
159 rev = (idcode >> 28) & 0xff;
160
161 if (hawkeye == 0xb7ae) {
162 switch (rev) {
163 case 0:
164 omap_revision = OMAP3430_REV_ES2_0;
165 rev_name = "ES2.0";
166 break;
167 case 2:
168 omap_revision = OMAP3430_REV_ES2_1;
169 rev_name = "ES2.1";
170 break;
171 case 3:
172 omap_revision = OMAP3430_REV_ES3_0;
173 rev_name = "ES3.0";
174 break;
175 default:
176 /* Use the latest known revision as default */
177 omap_revision = OMAP3430_REV_ES3_0;
178 rev_name = "Unknown revision\n";
179 }
180 }
181
182out:
183 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
267} 184}
268 185
186/*
187 * Try to detect the exact revision of the omap we're running on
188 */
189void __init omap2_check_revision(void)
190{
191 /*
192 * At this point we have an idea about the processor revision set
193 * earlier with omap2_set_globals_tap().
194 */
195 if (cpu_is_omap24xx())
196 omap24xx_check_revision();
197 else if (cpu_is_omap34xx())
198 omap34xx_check_revision();
199 else
200 pr_err("OMAP revision unknown, please fix!\n");
201
202 /*
203 * OK, now we know the exact revision. Initialize omap_chip bits
204 * for powerdowmain and clockdomain code.
205 */
206 if (cpu_is_omap243x()) {
207 /* Currently only supports 2430ES2.1 and 2430-all */
208 omap_chip.oc |= CHIP_IS_OMAP2430;
209 } else if (cpu_is_omap242x()) {
210 /* Currently only supports 2420ES2.1.1 and 2420-all */
211 omap_chip.oc |= CHIP_IS_OMAP2420;
212 } else if (cpu_is_omap343x()) {
213 omap_chip.oc = CHIP_IS_OMAP3430;
214 if (omap_rev() == OMAP3430_REV_ES1_0)
215 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
216 else if (omap_rev() > OMAP3430_REV_ES1_0)
217 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
218 } else {
219 pr_err("Uninitialized omap_chip, please fix!\n");
220 }
221}
222
223/*
224 * Set up things for map_io and processor detection later on. Gets called
225 * pretty much first thing from board init. For multi-omap, this gets
226 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
227 * detect the exact revision later on in omap2_detect_revision() once map_io
228 * is done.
229 */
269void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 230void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
270{ 231{
271 class = omap2_globals->class; 232 omap_revision = omap2_globals->class;
272 tap_base = omap2_globals->tap; 233 tap_base = omap2_globals->tap;
273 234
274 if (class == 0x3430) 235 if (cpu_is_omap34xx())
275 tap_prod_id = 0x0210; 236 tap_prod_id = 0x0210;
276 else 237 else
277 tap_prod_id = 0x0208; 238 tap_prod_id = 0x0208;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 21:26:10 -0500