1 files changed, 383 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 5f3aad977842..cdd1f35636dd 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,11 +15,127 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <mach/common.h>
+#include <plat/common.h>
-#include <mach/control.h>
+#include <plat/control.h>
+#include <plat/sdrc.h>
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "prm.h"
+#include "sdrc.h"
 static void __iomem *omap2_ctrl_base;
+#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
+struct omap3_scratchpad {
+        u32 boot_config_ptr;
+        u32 public_restore_ptr;
+        u32 secure_ram_restore_ptr;
+        u32 sdrc_module_semaphore;
+        u32 prcm_block_offset;
+        u32 sdrc_block_offset;
+};
+struct omap3_scratchpad_prcm_block {
+        u32 prm_clksrc_ctrl;
+        u32 prm_clksel;
+        u32 cm_clksel_core;
+        u32 cm_clksel_wkup;
+        u32 cm_clken_pll;
+        u32 cm_autoidle_pll;
+        u32 cm_clksel1_pll;
+        u32 cm_clksel2_pll;
+        u32 cm_clksel3_pll;
+        u32 cm_clken_pll_mpu;
+        u32 cm_autoidle_pll_mpu;
+        u32 cm_clksel1_pll_mpu;
+        u32 cm_clksel2_pll_mpu;
+        u32 prcm_block_size;
+};
+struct omap3_scratchpad_sdrc_block {
+        u16 sysconfig;
+        u16 cs_cfg;
+        u16 sharing;
+        u16 err_type;
+        u32 dll_a_ctrl;
+        u32 dll_b_ctrl;
+        u32 power;
+        u32 cs_0;
+        u32 mcfg_0;
+        u16 mr_0;
+        u16 emr_1_0;
+        u16 emr_2_0;
+        u16 emr_3_0;
+        u32 actim_ctrla_0;
+        u32 actim_ctrlb_0;
+        u32 rfr_ctrl_0;
+        u32 cs_1;
+        u32 mcfg_1;
+        u16 mr_1;
+        u16 emr_1_1;
+        u16 emr_2_1;
+        u16 emr_3_1;
+        u32 actim_ctrla_1;
+        u32 actim_ctrlb_1;
+        u32 rfr_ctrl_1;
+        u16 dcdl_1_ctrl;
+        u16 dcdl_2_ctrl;
+        u32 flags;
+        u32 block_size;
+};
+void *omap3_secure_ram_storage;
+/*
+ * This is used to store ARM registers in SDRAM before attempting
+ * an MPU OFF. The save and restore happens from the SRAM sleep code.
+ * The address is stored in scratchpad, so that it can be used
+ * during the restore path.
+ */
+u32 omap3_arm_context[128];
+struct omap3_control_regs {
+        u32 sysconfig;
+        u32 devconf0;
+        u32 mem_dftrw0;
+        u32 mem_dftrw1;
+        u32 msuspendmux_0;
+        u32 msuspendmux_1;
+        u32 msuspendmux_2;
+        u32 msuspendmux_3;
+        u32 msuspendmux_4;
+        u32 msuspendmux_5;
+        u32 sec_ctrl;
+        u32 devconf1;
+        u32 csirxfe;
+        u32 iva2_bootaddr;
+        u32 iva2_bootmod;
+        u32 debobs_0;
+        u32 debobs_1;
+        u32 debobs_2;
+        u32 debobs_3;
+        u32 debobs_4;
+        u32 debobs_5;
+        u32 debobs_6;
+        u32 debobs_7;
+        u32 debobs_8;
+        u32 prog_io0;
+        u32 prog_io1;
+        u32 dss_dpll_spreading;
+        u32 core_dpll_spreading;
+        u32 per_dpll_spreading;
+        u32 usbhost_dpll_spreading;
+        u32 pbias_lite;
+        u32 temp_sensor;
+        u32 sramldo4;
+        u32 sramldo5;
+        u32 csi;
+};
+static struct omap3_control_regs control_context;
+#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
@@ -62,3 +178,268 @@ void omap_ctrl_writel(u32 val, u16 offset)
        __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 }
+#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
+/*
+ * Clears the scratchpad contents in case of cold boot-
+ * called during bootup
+ */
+void omap3_clear_scratchpad_contents(void)
+{
+        u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
+        u32 *v_addr;
+        u32 offset = 0;
+        v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
+        if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
+                OMAP3430_GLOBAL_COLD_RST) {
+                for ( ; offset <= max_offset; offset += 0x4)
+                        __raw_writel(0x0, (v_addr + offset));
+                prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
+                        OMAP3_PRM_RSTST_OFFSET);
+        }
+}
+/* Populate the scratchpad structure with restore structure */
+void omap3_save_scratchpad_contents(void)
+{
+        void * __iomem scratchpad_address;
+        u32 arm_context_addr;
+        struct omap3_scratchpad scratchpad_contents;
+        struct omap3_scratchpad_prcm_block prcm_block_contents;
+        struct omap3_scratchpad_sdrc_block sdrc_block_contents;
+        /* Populate the Scratchpad contents */
+        scratchpad_contents.boot_config_ptr = 0x0;
+        if (omap_rev() != OMAP3430_REV_ES3_0 &&
+                                        omap_rev() != OMAP3430_REV_ES3_1)
+                scratchpad_contents.public_restore_ptr =
+                        virt_to_phys(get_restore_pointer());
+        else
+                scratchpad_contents.public_restore_ptr =
+                        virt_to_phys(get_es3_restore_pointer());
+        if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                scratchpad_contents.secure_ram_restore_ptr = 0x0;
+        else
+                scratchpad_contents.secure_ram_restore_ptr =
+                        (u32) __pa(omap3_secure_ram_storage);
+        scratchpad_contents.sdrc_module_semaphore = 0x0;
+        scratchpad_contents.prcm_block_offset = 0x2C;
+        scratchpad_contents.sdrc_block_offset = 0x64;
+        /* Populate the PRCM block contents */
+        prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
+                        OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+        prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
+                        OMAP3_PRM_CLKSEL_OFFSET);
+        prcm_block_contents.cm_clksel_core =
+                        cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
+        prcm_block_contents.cm_clksel_wkup =
+                        cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+        prcm_block_contents.cm_clken_pll =
+                        cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        prcm_block_contents.cm_autoidle_pll =
+                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+        prcm_block_contents.cm_clksel1_pll =
+                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
+        prcm_block_contents.cm_clksel2_pll =
+                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
+        prcm_block_contents.cm_clksel3_pll =
+                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
+        prcm_block_contents.cm_clken_pll_mpu =
+                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
+        prcm_block_contents.cm_autoidle_pll_mpu =
+                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+        prcm_block_contents.cm_clksel1_pll_mpu =
+                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
+        prcm_block_contents.cm_clksel2_pll_mpu =
+                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
+        prcm_block_contents.prcm_block_size = 0x0;
+        /* Populate the SDRC block contents */
+        sdrc_block_contents.sysconfig =
+                        (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
+        sdrc_block_contents.cs_cfg =
+                        (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
+        sdrc_block_contents.sharing =
+                        (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
+        sdrc_block_contents.err_type =
+                        (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
+        sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
+        sdrc_block_contents.dll_b_ctrl = 0x0;
+        /*
+         * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
+         * be programed to issue automatic self refresh on timeout
+         * of AUTO_CNT = 1 prior to any transition to OFF mode.
+         */
+        if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
+                        && (omap_rev() >= OMAP3430_REV_ES3_0))
+                sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
+                                ~(SDRC_POWER_AUTOCOUNT_MASK|
+                                SDRC_POWER_CLKCTRL_MASK)) |
+                                (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
+                                SDRC_SELF_REFRESH_ON_AUTOCOUNT;
+        else
+                sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
+        sdrc_block_contents.cs_0 = 0x0;
+        sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
+        sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
+        sdrc_block_contents.emr_1_0 = 0x0;
+        sdrc_block_contents.emr_2_0 = 0x0;
+        sdrc_block_contents.emr_3_0 = 0x0;
+        sdrc_block_contents.actim_ctrla_0 =
+                        sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
+        sdrc_block_contents.actim_ctrlb_0 =
+                        sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
+        sdrc_block_contents.rfr_ctrl_0 =
+                        sdrc_read_reg(SDRC_RFR_CTRL_0);
+        sdrc_block_contents.cs_1 = 0x0;
+        sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
+        sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
+        sdrc_block_contents.emr_1_1 = 0x0;
+        sdrc_block_contents.emr_2_1 = 0x0;
+        sdrc_block_contents.emr_3_1 = 0x0;
+        sdrc_block_contents.actim_ctrla_1 =
+                        sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
+        sdrc_block_contents.actim_ctrlb_1 =
+                        sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
+        sdrc_block_contents.rfr_ctrl_1 =
+                        sdrc_read_reg(SDRC_RFR_CTRL_1);
+        sdrc_block_contents.dcdl_1_ctrl = 0x0;
+        sdrc_block_contents.dcdl_2_ctrl = 0x0;
+        sdrc_block_contents.flags = 0x0;
+        sdrc_block_contents.block_size = 0x0;
+        arm_context_addr = virt_to_phys(omap3_arm_context);
+        /* Copy all the contents to the scratchpad location */
+        scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
+        memcpy_toio(scratchpad_address, &scratchpad_contents,
+                 sizeof(scratchpad_contents));
+        /* Scratchpad contents being 32 bits, a divide by 4 done here */
+        memcpy_toio(scratchpad_address +
+                scratchpad_contents.prcm_block_offset,
+                &prcm_block_contents, sizeof(prcm_block_contents));
+        memcpy_toio(scratchpad_address +
+                scratchpad_contents.sdrc_block_offset,
+                &sdrc_block_contents, sizeof(sdrc_block_contents));
+        /*
+         * Copies the address of the location in SDRAM where ARM
+         * registers get saved during a MPU OFF transition.
+         */
+        memcpy_toio(scratchpad_address +
+                scratchpad_contents.sdrc_block_offset +
+                sizeof(sdrc_block_contents), &arm_context_addr, 4);
+}
+void omap3_control_save_context(void)
+{
+        control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
+        control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        control_context.mem_dftrw0 =
+                        omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
+        control_context.mem_dftrw1 =
+                        omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
+        control_context.msuspendmux_0 =
+                        omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
+        control_context.msuspendmux_1 =
+                        omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
+        control_context.msuspendmux_2 =
+                        omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
+        control_context.msuspendmux_3 =
+                        omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
+        control_context.msuspendmux_4 =
+                        omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
+        control_context.msuspendmux_5 =
+                        omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
+        control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
+        control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
+        control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
+        control_context.iva2_bootaddr =
+                        omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
+        control_context.iva2_bootmod =
+                        omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
+        control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
+        control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
+        control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
+        control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
+        control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
+        control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
+        control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
+        control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
+        control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
+        control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
+        control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
+        control_context.dss_dpll_spreading =
+                        omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
+        control_context.core_dpll_spreading =
+                        omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
+        control_context.per_dpll_spreading =
+                        omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
+        control_context.usbhost_dpll_spreading =
+                omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
+        control_context.pbias_lite =
+                        omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
+        control_context.temp_sensor =
+                        omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
+        control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
+        control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
+        control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
+        return;
+}
+void omap3_control_restore_context(void)
+{
+        omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
+        omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
+        omap_ctrl_writel(control_context.mem_dftrw0,
+                                        OMAP343X_CONTROL_MEM_DFTRW0);
+        omap_ctrl_writel(control_context.mem_dftrw1,
+                                        OMAP343X_CONTROL_MEM_DFTRW1);
+        omap_ctrl_writel(control_context.msuspendmux_0,
+                                        OMAP2_CONTROL_MSUSPENDMUX_0);
+        omap_ctrl_writel(control_context.msuspendmux_1,
+                                        OMAP2_CONTROL_MSUSPENDMUX_1);
+        omap_ctrl_writel(control_context.msuspendmux_2,
+                                        OMAP2_CONTROL_MSUSPENDMUX_2);
+        omap_ctrl_writel(control_context.msuspendmux_3,
+                                        OMAP2_CONTROL_MSUSPENDMUX_3);
+        omap_ctrl_writel(control_context.msuspendmux_4,
+                                        OMAP2_CONTROL_MSUSPENDMUX_4);
+        omap_ctrl_writel(control_context.msuspendmux_5,
+                                        OMAP2_CONTROL_MSUSPENDMUX_5);
+        omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
+        omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
+        omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
+        omap_ctrl_writel(control_context.iva2_bootaddr,
+                                        OMAP343X_CONTROL_IVA2_BOOTADDR);
+        omap_ctrl_writel(control_context.iva2_bootmod,
+                                        OMAP343X_CONTROL_IVA2_BOOTMOD);
+        omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
+        omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
+        omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
+        omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
+        omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
+        omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
+        omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
+        omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
+        omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
+        omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
+        omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
+        omap_ctrl_writel(control_context.dss_dpll_spreading,
+                                        OMAP343X_CONTROL_DSS_DPLL_SPREADING);
+        omap_ctrl_writel(control_context.core_dpll_spreading,
+                                        OMAP343X_CONTROL_CORE_DPLL_SPREADING);
+        omap_ctrl_writel(control_context.per_dpll_spreading,
+                                        OMAP343X_CONTROL_PER_DPLL_SPREADING);
+        omap_ctrl_writel(control_context.usbhost_dpll_spreading,
+                                OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
+        omap_ctrl_writel(control_context.pbias_lite,
+                                        OMAP343X_CONTROL_PBIAS_LITE);
+        omap_ctrl_writel(control_context.temp_sensor,
+                                        OMAP343X_CONTROL_TEMP_SENSOR);
+        omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
+        omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
+        omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
+        return;
+}
+#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */

diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 5f3aad977842..cdd1f35636dd 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c
@@ -15,11 +15,127 @@
15	#include <linux/kernel.h>	15	#include <linux/kernel.h>
16	#include <linux/io.h>	16	#include <linux/io.h>
17		17
18	#include <mach/common.h>	18	#include <plat/common.h>
19	#include <mach/control.h>	19	#include <plat/control.h>
		20	#include <plat/sdrc.h>
		21	#include "cm-regbits-34xx.h"
		22	#include "prm-regbits-34xx.h"
		23	#include "cm.h"
		24	#include "prm.h"
		25	#include "sdrc.h"
20		26
21	static void __iomem *omap2_ctrl_base;	27	static void __iomem *omap2_ctrl_base;
22		28
		29	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
		30	struct omap3_scratchpad {
		31	u32 boot_config_ptr;
		32	u32 public_restore_ptr;
		33	u32 secure_ram_restore_ptr;
		34	u32 sdrc_module_semaphore;
		35	u32 prcm_block_offset;
		36	u32 sdrc_block_offset;
		37	};
		38
		39	struct omap3_scratchpad_prcm_block {
		40	u32 prm_clksrc_ctrl;
		41	u32 prm_clksel;
		42	u32 cm_clksel_core;
		43	u32 cm_clksel_wkup;
		44	u32 cm_clken_pll;
		45	u32 cm_autoidle_pll;
		46	u32 cm_clksel1_pll;
		47	u32 cm_clksel2_pll;
		48	u32 cm_clksel3_pll;
		49	u32 cm_clken_pll_mpu;
		50	u32 cm_autoidle_pll_mpu;
		51	u32 cm_clksel1_pll_mpu;
		52	u32 cm_clksel2_pll_mpu;
		53	u32 prcm_block_size;
		54	};
		55
		56	struct omap3_scratchpad_sdrc_block {
		57	u16 sysconfig;
		58	u16 cs_cfg;
		59	u16 sharing;
		60	u16 err_type;
		61	u32 dll_a_ctrl;
		62	u32 dll_b_ctrl;
		63	u32 power;
		64	u32 cs_0;
		65	u32 mcfg_0;
		66	u16 mr_0;
		67	u16 emr_1_0;
		68	u16 emr_2_0;
		69	u16 emr_3_0;
		70	u32 actim_ctrla_0;
		71	u32 actim_ctrlb_0;
		72	u32 rfr_ctrl_0;
		73	u32 cs_1;
		74	u32 mcfg_1;
		75	u16 mr_1;
		76	u16 emr_1_1;
		77	u16 emr_2_1;
		78	u16 emr_3_1;
		79	u32 actim_ctrla_1;
		80	u32 actim_ctrlb_1;
		81	u32 rfr_ctrl_1;
		82	u16 dcdl_1_ctrl;
		83	u16 dcdl_2_ctrl;
		84	u32 flags;
		85	u32 block_size;
		86	};
		87
		88	void *omap3_secure_ram_storage;
		89
		90	/*
		91	* This is used to store ARM registers in SDRAM before attempting
		92	* an MPU OFF. The save and restore happens from the SRAM sleep code.
		93	* The address is stored in scratchpad, so that it can be used
		94	* during the restore path.
		95	*/
		96	u32 omap3_arm_context[128];
		97
		98	struct omap3_control_regs {
		99	u32 sysconfig;
		100	u32 devconf0;
		101	u32 mem_dftrw0;
		102	u32 mem_dftrw1;
		103	u32 msuspendmux_0;
		104	u32 msuspendmux_1;
		105	u32 msuspendmux_2;
		106	u32 msuspendmux_3;
		107	u32 msuspendmux_4;
		108	u32 msuspendmux_5;
		109	u32 sec_ctrl;
		110	u32 devconf1;
		111	u32 csirxfe;
		112	u32 iva2_bootaddr;
		113	u32 iva2_bootmod;
		114	u32 debobs_0;
		115	u32 debobs_1;
		116	u32 debobs_2;
		117	u32 debobs_3;
		118	u32 debobs_4;
		119	u32 debobs_5;
		120	u32 debobs_6;
		121	u32 debobs_7;
		122	u32 debobs_8;
		123	u32 prog_io0;
		124	u32 prog_io1;
		125	u32 dss_dpll_spreading;
		126	u32 core_dpll_spreading;
		127	u32 per_dpll_spreading;
		128	u32 usbhost_dpll_spreading;
		129	u32 pbias_lite;
		130	u32 temp_sensor;
		131	u32 sramldo4;
		132	u32 sramldo5;
		133	u32 csi;
		134	};
		135
		136	static struct omap3_control_regs control_context;
		137	#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
		138
23	#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))	139	#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
24		140
25	void __init omap2_set_globals_control(struct omap_globals *omap2_globals)	141	void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
@@ -62,3 +178,268 @@ void omap_ctrl_writel(u32 val, u16 offset)
62	__raw_writel(val, OMAP_CTRL_REGADDR(offset));	178	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
63	}	179	}
64		180
		181	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
		182	/*
		183	* Clears the scratchpad contents in case of cold boot-
		184	* called during bootup
		185	*/
		186	void omap3_clear_scratchpad_contents(void)
		187	{
		188	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
		189	u32 *v_addr;
		190	u32 offset = 0;
		191	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
		192	if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
		193	OMAP3430_GLOBAL_COLD_RST) {
		194	for ( ; offset <= max_offset; offset += 0x4)
		195	__raw_writel(0x0, (v_addr + offset));
		196	prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
		197	OMAP3_PRM_RSTST_OFFSET);
		198	}
		199	}
		200
		201	/* Populate the scratchpad structure with restore structure */
		202	void omap3_save_scratchpad_contents(void)
		203	{
		204	void * __iomem scratchpad_address;
		205	u32 arm_context_addr;
		206	struct omap3_scratchpad scratchpad_contents;
		207	struct omap3_scratchpad_prcm_block prcm_block_contents;
		208	struct omap3_scratchpad_sdrc_block sdrc_block_contents;
		209
		210	/* Populate the Scratchpad contents */
		211	scratchpad_contents.boot_config_ptr = 0x0;
		212	if (omap_rev() != OMAP3430_REV_ES3_0 &&
		213	omap_rev() != OMAP3430_REV_ES3_1)
		214	scratchpad_contents.public_restore_ptr =
		215	virt_to_phys(get_restore_pointer());
		216	else
		217	scratchpad_contents.public_restore_ptr =
		218	virt_to_phys(get_es3_restore_pointer());
		219	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
		220	scratchpad_contents.secure_ram_restore_ptr = 0x0;
		221	else
		222	scratchpad_contents.secure_ram_restore_ptr =
		223	(u32) __pa(omap3_secure_ram_storage);
		224	scratchpad_contents.sdrc_module_semaphore = 0x0;
		225	scratchpad_contents.prcm_block_offset = 0x2C;
		226	scratchpad_contents.sdrc_block_offset = 0x64;
		227
		228	/* Populate the PRCM block contents */
		229	prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
		230	OMAP3_PRM_CLKSRC_CTRL_OFFSET);
		231	prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
		232	OMAP3_PRM_CLKSEL_OFFSET);
		233	prcm_block_contents.cm_clksel_core =
		234	cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
		235	prcm_block_contents.cm_clksel_wkup =
		236	cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
		237	prcm_block_contents.cm_clken_pll =
		238	cm_read_mod_reg(PLL_MOD, CM_CLKEN);
		239	prcm_block_contents.cm_autoidle_pll =
		240	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
		241	prcm_block_contents.cm_clksel1_pll =
		242	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
		243	prcm_block_contents.cm_clksel2_pll =
		244	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
		245	prcm_block_contents.cm_clksel3_pll =
		246	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
		247	prcm_block_contents.cm_clken_pll_mpu =
		248	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
		249	prcm_block_contents.cm_autoidle_pll_mpu =
		250	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
		251	prcm_block_contents.cm_clksel1_pll_mpu =
		252	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
		253	prcm_block_contents.cm_clksel2_pll_mpu =
		254	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
		255	prcm_block_contents.prcm_block_size = 0x0;
		256
		257	/* Populate the SDRC block contents */
		258	sdrc_block_contents.sysconfig =
		259	(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
		260	sdrc_block_contents.cs_cfg =
		261	(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
		262	sdrc_block_contents.sharing =
		263	(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
		264	sdrc_block_contents.err_type =
		265	(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
		266	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
		267	sdrc_block_contents.dll_b_ctrl = 0x0;
		268	/*
		269	* Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
		270	* be programed to issue automatic self refresh on timeout
		271	* of AUTO_CNT = 1 prior to any transition to OFF mode.
		272	*/
		273	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
		274	&& (omap_rev() >= OMAP3430_REV_ES3_0))
		275	sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
		276	~(SDRC_POWER_AUTOCOUNT_MASK\|
		277	SDRC_POWER_CLKCTRL_MASK)) \|
		278	(1 << SDRC_POWER_AUTOCOUNT_SHIFT) \|
		279	SDRC_SELF_REFRESH_ON_AUTOCOUNT;
		280	else
		281	sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
		282
		283	sdrc_block_contents.cs_0 = 0x0;
		284	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
		285	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
		286	sdrc_block_contents.emr_1_0 = 0x0;
		287	sdrc_block_contents.emr_2_0 = 0x0;
		288	sdrc_block_contents.emr_3_0 = 0x0;
		289	sdrc_block_contents.actim_ctrla_0 =
		290	sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
		291	sdrc_block_contents.actim_ctrlb_0 =
		292	sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
		293	sdrc_block_contents.rfr_ctrl_0 =
		294	sdrc_read_reg(SDRC_RFR_CTRL_0);
		295	sdrc_block_contents.cs_1 = 0x0;
		296	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
		297	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
		298	sdrc_block_contents.emr_1_1 = 0x0;
		299	sdrc_block_contents.emr_2_1 = 0x0;
		300	sdrc_block_contents.emr_3_1 = 0x0;
		301	sdrc_block_contents.actim_ctrla_1 =
		302	sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
		303	sdrc_block_contents.actim_ctrlb_1 =
		304	sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
		305	sdrc_block_contents.rfr_ctrl_1 =
		306	sdrc_read_reg(SDRC_RFR_CTRL_1);
		307	sdrc_block_contents.dcdl_1_ctrl = 0x0;
		308	sdrc_block_contents.dcdl_2_ctrl = 0x0;
		309	sdrc_block_contents.flags = 0x0;
		310	sdrc_block_contents.block_size = 0x0;
		311
		312	arm_context_addr = virt_to_phys(omap3_arm_context);
		313
		314	/* Copy all the contents to the scratchpad location */
		315	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
		316	memcpy_toio(scratchpad_address, &scratchpad_contents,
		317	sizeof(scratchpad_contents));
		318	/* Scratchpad contents being 32 bits, a divide by 4 done here */
		319	memcpy_toio(scratchpad_address +
		320	scratchpad_contents.prcm_block_offset,
		321	&prcm_block_contents, sizeof(prcm_block_contents));
		322	memcpy_toio(scratchpad_address +
		323	scratchpad_contents.sdrc_block_offset,
		324	&sdrc_block_contents, sizeof(sdrc_block_contents));
		325	/*
		326	* Copies the address of the location in SDRAM where ARM
		327	* registers get saved during a MPU OFF transition.
		328	*/
		329	memcpy_toio(scratchpad_address +
		330	scratchpad_contents.sdrc_block_offset +
		331	sizeof(sdrc_block_contents), &arm_context_addr, 4);
		332	}
		333
		334	void omap3_control_save_context(void)
		335	{
		336	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
		337	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
		338	control_context.mem_dftrw0 =
		339	omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
		340	control_context.mem_dftrw1 =
		341	omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
		342	control_context.msuspendmux_0 =
		343	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
		344	control_context.msuspendmux_1 =
		345	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
		346	control_context.msuspendmux_2 =
		347	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
		348	control_context.msuspendmux_3 =
		349	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
		350	control_context.msuspendmux_4 =
		351	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
		352	control_context.msuspendmux_5 =
		353	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
		354	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
		355	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
		356	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
		357	control_context.iva2_bootaddr =
		358	omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
		359	control_context.iva2_bootmod =
		360	omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
		361	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
		362	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
		363	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
		364	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
		365	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
		366	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
		367	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
		368	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
		369	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
		370	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
		371	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
		372	control_context.dss_dpll_spreading =
		373	omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
		374	control_context.core_dpll_spreading =
		375	omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
		376	control_context.per_dpll_spreading =
		377	omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
		378	control_context.usbhost_dpll_spreading =
		379	omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
		380	control_context.pbias_lite =
		381	omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
		382	control_context.temp_sensor =
		383	omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
		384	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
		385	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
		386	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
		387	return;
		388	}
		389
		390	void omap3_control_restore_context(void)
		391	{
		392	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
		393	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
		394	omap_ctrl_writel(control_context.mem_dftrw0,
		395	OMAP343X_CONTROL_MEM_DFTRW0);
		396	omap_ctrl_writel(control_context.mem_dftrw1,
		397	OMAP343X_CONTROL_MEM_DFTRW1);
		398	omap_ctrl_writel(control_context.msuspendmux_0,
		399	OMAP2_CONTROL_MSUSPENDMUX_0);
		400	omap_ctrl_writel(control_context.msuspendmux_1,
		401	OMAP2_CONTROL_MSUSPENDMUX_1);
		402	omap_ctrl_writel(control_context.msuspendmux_2,
		403	OMAP2_CONTROL_MSUSPENDMUX_2);
		404	omap_ctrl_writel(control_context.msuspendmux_3,
		405	OMAP2_CONTROL_MSUSPENDMUX_3);
		406	omap_ctrl_writel(control_context.msuspendmux_4,
		407	OMAP2_CONTROL_MSUSPENDMUX_4);
		408	omap_ctrl_writel(control_context.msuspendmux_5,
		409	OMAP2_CONTROL_MSUSPENDMUX_5);
		410	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
		411	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
		412	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
		413	omap_ctrl_writel(control_context.iva2_bootaddr,
		414	OMAP343X_CONTROL_IVA2_BOOTADDR);
		415	omap_ctrl_writel(control_context.iva2_bootmod,
		416	OMAP343X_CONTROL_IVA2_BOOTMOD);
		417	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
		418	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
		419	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
		420	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
		421	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
		422	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
		423	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
		424	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
		425	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
		426	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
		427	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
		428	omap_ctrl_writel(control_context.dss_dpll_spreading,
		429	OMAP343X_CONTROL_DSS_DPLL_SPREADING);
		430	omap_ctrl_writel(control_context.core_dpll_spreading,
		431	OMAP343X_CONTROL_CORE_DPLL_SPREADING);
		432	omap_ctrl_writel(control_context.per_dpll_spreading,
		433	OMAP343X_CONTROL_PER_DPLL_SPREADING);
		434	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
		435	OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
		436	omap_ctrl_writel(control_context.pbias_lite,
		437	OMAP343X_CONTROL_PBIAS_LITE);
		438	omap_ctrl_writel(control_context.temp_sensor,
		439	OMAP343X_CONTROL_TEMP_SENSOR);
		440	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
		441	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
		442	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
		443	return;
		444	}
		445	#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */