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-rw-r--r--arch/arm/mach-omap2/cminst44xx.c105
1 files changed, 105 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index c13613b513b5..c04bbbea17a5 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -26,6 +26,7 @@
26#include "cm2_44xx.h" 26#include "cm2_44xx.h"
27#include "cm44xx.h" 27#include "cm44xx.h"
28#include "cminst44xx.h" 28#include "cminst44xx.h"
29#include "cm-regbits-34xx.h"
29#include "cm-regbits-44xx.h" 30#include "cm-regbits-44xx.h"
30#include "prcm44xx.h" 31#include "prcm44xx.h"
31#include "prm44xx.h" 32#include "prm44xx.h"
@@ -72,6 +73,110 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
72 return v; 73 return v;
73} 74}
74 75
76/*
77 *
78 */
79
80/**
81 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
82 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
83 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
84 * @inst: CM instance register offset (*_INST macro)
85 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
86 *
87 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
88 * will handle the shift itself.
89 */
90static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
91{
92 u32 v;
93
94 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
95 v &= ~OMAP4430_CLKTRCTRL_MASK;
96 v |= c << OMAP4430_CLKTRCTRL_SHIFT;
97 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
98}
99
100/**
101 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
102 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
103 * @inst: CM instance register offset (*_INST macro)
104 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
105 *
106 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
107 * is in hardware-supervised idle mode, or 0 otherwise.
108 */
109bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
110{
111 u32 v;
112
113 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
114 v &= OMAP4430_CLKTRCTRL_MASK;
115 v >>= OMAP4430_CLKTRCTRL_SHIFT;
116
117 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
118}
119
120/**
121 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
122 * @part: PRCM partition ID that the clockdomain registers exist in
123 * @inst: CM instance register offset (*_INST macro)
124 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
125 *
126 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
127 * hardware-supervised idle mode. No return value.
128 */
129void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
130{
131 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
132}
133
134/**
135 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
136 * @part: PRCM partition ID that the clockdomain registers exist in
137 * @inst: CM instance register offset (*_INST macro)
138 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
139 *
140 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
141 * software-supervised idle mode, i.e., controlled manually by the
142 * Linux OMAP clockdomain code. No return value.
143 */
144void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
145{
146 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
147}
148
149/**
150 * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
151 * @part: PRCM partition ID that the clockdomain registers exist in
152 * @inst: CM instance register offset (*_INST macro)
153 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
154 *
155 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
156 * No return value.
157 */
158void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
159{
160 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
161}
162
163/**
164 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
165 * @part: PRCM partition ID that the clockdomain registers exist in
166 * @inst: CM instance register offset (*_INST macro)
167 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
168 *
169 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
170 * waking it up. No return value.
171 */
172void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
173{
174 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
175}
176
177/*
178 *
179 */
75 180
76/** 181/**
77 * omap4_cm_wait_module_ready - wait for a module to be in 'func' state 182 * omap4_cm_wait_module_ready - wait for a module to be in 'func' state