aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/cm1_44xx.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2/cm1_44xx.h')
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h64
1 files changed, 14 insertions, 50 deletions
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index e2d7a56b2ad6..1bc00dc4876c 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP44xx CM1 instance offset macros 2 * OMAP44xx CM1 instance offset macros
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -41,9 +41,9 @@
41#define OMAP4430_CM1_INSTR_INST 0x0f00 41#define OMAP4430_CM1_INSTR_INST 0x0f00
42 42
43/* CM1 clockdomain register offsets (from instance start) */ 43/* CM1 clockdomain register offsets (from instance start) */
44#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 44#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
45#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 45#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
46#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 46#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
47 47
48/* CM1 */ 48/* CM1 */
49 49
@@ -82,8 +82,8 @@
82#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 82#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
83#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 83#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
84#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 84#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
85#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c 85#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
86#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 86#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
87#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 87#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
88#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 88#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
89#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 89#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
@@ -98,8 +98,8 @@
98#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 98#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
99#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 99#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
101#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c 101#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
102#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 102#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
@@ -116,8 +116,8 @@
116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
119#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc 119#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
120#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 120#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
@@ -134,8 +134,8 @@
134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
137#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c 137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
138#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
@@ -154,8 +154,8 @@
154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
157#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 157#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
158#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 158#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
@@ -217,42 +217,6 @@
217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
219 219
220/* CM1.RESTORE_CM1 register offsets */
221#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
222#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
223#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
224#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
225#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
226#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
227#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
228#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
229#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
230#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
231#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
232#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
233#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
234#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
235#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
236#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
237#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
238#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
239#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
240#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
241#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
242#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
243#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
244#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
245#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
246#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
247#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
248#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
249#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
250#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
251#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
252#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
253#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
254#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
255
256/* Function prototypes */ 220/* Function prototypes */
257extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); 221extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
258extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); 222extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 21:31:03 -0400