1 files changed, 22 insertions, 7 deletions

diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index cfd0b726ba44..94728b1ee3c4 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -4,8 +4,8 @@
 /*
  * OMAP2/3 Clock Management (CM) register definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -17,11 +17,17 @@
 #include "prcm-common.h"
 
 #define OMAP2420_CM_REGADDR(module, reg)                                \
-                        OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
 #define OMAP2430_CM_REGADDR(module, reg)                                \
-                        OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
 #define OMAP34XX_CM_REGADDR(module, reg)                                \
-                        OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#define OMAP44XX_CM1_REGADDR(module, reg)                               \
+                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
+#define OMAP44XX_CM2_REGADDR(module, reg)                               \
+                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
+
+#include "cm44xx.h"
 
 /*
  * Architecture-specific global CM registers
@@ -61,7 +67,8 @@
 #define CM_CLKSEL                                       0x0040
 #define CM_CLKSEL1                                      CM_CLKSEL
 #define CM_CLKSEL2                                      0x0044
-#define CM_CLKSTCTRL                                    0x0048
+#define OMAP2_CM_CLKSTCTRL                              0x0048
+#define OMAP4_CM_CLKSTCTRL                              0x0000
 
 
 /* Architecture-specific registers */
@@ -82,13 +89,18 @@
 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
 #define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
 #define OMAP3430_CM_CLKSTST                             0x004c
 #define OMAP3430ES2_CM_CLKSEL4                          0x004c
 #define OMAP3430ES2_CM_CLKSEL5                          0x0050
 #define OMAP3430_CM_CLKSEL2_EMU                         0x0050
 #define OMAP3430_CM_CLKSEL3_EMU                         0x0054
 
+/* CM2.CEFUSE_CM2 register offsets */
+
+/* OMAP4 modulemode control */
+#define OMAP4430_MODULEMODE_HWCTRL                      0
+#define OMAP4430_MODULEMODE_SWCTRL                      1
 
 /* Clock management domain register get/set */
 
@@ -127,5 +139,8 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 /* CM_IDLEST_GFX */
 #define OMAP_ST_GFX                                     (1 << 0)
 
+/* CM_IDLEST indicator */
+#define OMAP24XX_CM_IDLEST_VAL          0
+#define OMAP34XX_CM_IDLEST_VAL          1
 
 #endif