diff options
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 42 |
1 files changed, 31 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index ee4c0ca1a708..219f5c8d9659 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
@@ -96,7 +96,8 @@ | |||
96 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | 96 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) |
97 | 97 | ||
98 | /* CM_CLKSTST_IVA2 */ | 98 | /* CM_CLKSTST_IVA2 */ |
99 | #define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) | 99 | #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 |
100 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) | ||
100 | 101 | ||
101 | /* CM_REVISION specific bits */ | 102 | /* CM_REVISION specific bits */ |
102 | 103 | ||
@@ -140,7 +141,8 @@ | |||
140 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | 141 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) |
141 | 142 | ||
142 | /* CM_CLKSTST_MPU */ | 143 | /* CM_CLKSTST_MPU */ |
143 | #define OMAP3430_CLKACTIVITY_MPU (1 << 0) | 144 | #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 |
145 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | ||
144 | 146 | ||
145 | /* CM_FCLKEN1_CORE specific bits */ | 147 | /* CM_FCLKEN1_CORE specific bits */ |
146 | 148 | ||
@@ -300,9 +302,12 @@ | |||
300 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | 302 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) |
301 | 303 | ||
302 | /* CM_CLKSTST_CORE */ | 304 | /* CM_CLKSTST_CORE */ |
303 | #define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) | 305 | #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 |
304 | #define OMAP3430_CLKACTIVITY_L4 (1 << 1) | 306 | #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) |
305 | #define OMAP3430_CLKACTIVITY_L3 (1 << 0) | 307 | #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 |
308 | #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) | ||
309 | #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 | ||
310 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | ||
306 | 311 | ||
307 | /* CM_FCLKEN_GFX */ | 312 | /* CM_FCLKEN_GFX */ |
308 | #define OMAP3430ES1_EN_3D (1 << 2) | 313 | #define OMAP3430ES1_EN_3D (1 << 2) |
@@ -323,7 +328,8 @@ | |||
323 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | 328 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) |
324 | 329 | ||
325 | /* CM_CLKSTST_GFX */ | 330 | /* CM_CLKSTST_GFX */ |
326 | #define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) | 331 | #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 |
332 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | ||
327 | 333 | ||
328 | /* CM_FCLKEN_SGX */ | 334 | /* CM_FCLKEN_SGX */ |
329 | #define OMAP3430ES2_EN_SGX_SHIFT 1 | 335 | #define OMAP3430ES2_EN_SGX_SHIFT 1 |
@@ -333,6 +339,14 @@ | |||
333 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | 339 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 |
334 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | 340 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) |
335 | 341 | ||
342 | /* CM_CLKSTCTRL_SGX */ | ||
343 | #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 | ||
344 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) | ||
345 | |||
346 | /* CM_CLKSTST_SGX */ | ||
347 | #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 | ||
348 | #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) | ||
349 | |||
336 | /* CM_FCLKEN_WKUP specific bits */ | 350 | /* CM_FCLKEN_WKUP specific bits */ |
337 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | 351 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 |
338 | 352 | ||
@@ -498,7 +512,8 @@ | |||
498 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | 512 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) |
499 | 513 | ||
500 | /* CM_CLKSTST_DSS */ | 514 | /* CM_CLKSTST_DSS */ |
501 | #define OMAP3430_CLKACTIVITY_DSS (1 << 0) | 515 | #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 |
516 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | ||
502 | 517 | ||
503 | /* CM_FCLKEN_CAM specific bits */ | 518 | /* CM_FCLKEN_CAM specific bits */ |
504 | 519 | ||
@@ -522,7 +537,8 @@ | |||
522 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | 537 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) |
523 | 538 | ||
524 | /* CM_CLKSTST_CAM */ | 539 | /* CM_CLKSTST_CAM */ |
525 | #define OMAP3430_CLKACTIVITY_CAM (1 << 0) | 540 | #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 |
541 | #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) | ||
526 | 542 | ||
527 | /* CM_FCLKEN_PER specific bits */ | 543 | /* CM_FCLKEN_PER specific bits */ |
528 | 544 | ||
@@ -598,7 +614,8 @@ | |||
598 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | 614 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) |
599 | 615 | ||
600 | /* CM_CLKSTST_PER */ | 616 | /* CM_CLKSTST_PER */ |
601 | #define OMAP3430_CLKACTIVITY_PER (1 << 0) | 617 | #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 |
618 | #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) | ||
602 | 619 | ||
603 | /* CM_CLKSEL1_EMU */ | 620 | /* CM_CLKSEL1_EMU */ |
604 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 621 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
@@ -623,7 +640,8 @@ | |||
623 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | 640 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) |
624 | 641 | ||
625 | /* CM_CLKSTST_EMU */ | 642 | /* CM_CLKSTST_EMU */ |
626 | #define OMAP3430_CLKACTIVITY_EMU (1 << 0) | 643 | #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 |
644 | #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) | ||
627 | 645 | ||
628 | /* CM_CLKSEL2_EMU specific bits */ | 646 | /* CM_CLKSEL2_EMU specific bits */ |
629 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | 647 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 |
@@ -673,6 +691,8 @@ | |||
673 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | 691 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 |
674 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | 692 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) |
675 | 693 | ||
676 | 694 | /* CM_CLKSTST_USBHOST */ | |
695 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | ||
696 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | ||
677 | 697 | ||
678 | #endif | 698 | #endif |