diff options
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 59598ffd8783..adf78d325804 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -81,6 +81,7 @@ | |||
| 81 | /* CM_CLKSEL1_PLL_IVA2 */ | 81 | /* CM_CLKSEL1_PLL_IVA2 */ |
| 82 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | 82 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 |
| 83 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) | 83 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) |
| 84 | #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 | ||
| 84 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 | 85 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 |
| 85 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | 86 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) |
| 86 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | 87 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 |
| @@ -89,6 +90,7 @@ | |||
| 89 | /* CM_CLKSEL2_PLL_IVA2 */ | 90 | /* CM_CLKSEL2_PLL_IVA2 */ |
| 90 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | 91 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 |
| 91 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | 92 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
| 93 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 | ||
| 92 | 94 | ||
| 93 | /* CM_CLKSTCTRL_IVA2 */ | 95 | /* CM_CLKSTCTRL_IVA2 */ |
| 94 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | 96 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 |
| @@ -118,6 +120,7 @@ | |||
| 118 | /* CM_IDLEST_PLL_MPU */ | 120 | /* CM_IDLEST_PLL_MPU */ |
| 119 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 | 121 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
| 120 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) | 122 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
| 123 | #define OMAP3430_ST_MPU_CLK_WIDTH 1 | ||
| 121 | 124 | ||
| 122 | /* CM_AUTOIDLE_PLL_MPU */ | 125 | /* CM_AUTOIDLE_PLL_MPU */ |
| 123 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | 126 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 |
| @@ -126,6 +129,7 @@ | |||
| 126 | /* CM_CLKSEL1_PLL_MPU */ | 129 | /* CM_CLKSEL1_PLL_MPU */ |
| 127 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | 130 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 |
| 128 | #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) | 131 | #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) |
| 132 | #define OMAP3430_MPU_CLK_SRC_WIDTH 3 | ||
| 129 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 | 133 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 |
| 130 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | 134 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) |
| 131 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | 135 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 |
| @@ -134,6 +138,7 @@ | |||
| 134 | /* CM_CLKSEL2_PLL_MPU */ | 138 | /* CM_CLKSEL2_PLL_MPU */ |
| 135 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | 139 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 |
| 136 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | 140 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
| 141 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 | ||
| 137 | 142 | ||
| 138 | /* CM_CLKSTCTRL_MPU */ | 143 | /* CM_CLKSTCTRL_MPU */ |
| 139 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | 144 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 |
| @@ -345,10 +350,13 @@ | |||
| 345 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | 350 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) |
| 346 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | 351 | #define OMAP3430_CLKSEL_L4_SHIFT 2 |
| 347 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | 352 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) |
| 353 | #define OMAP3430_CLKSEL_L4_WIDTH 2 | ||
| 348 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | 354 | #define OMAP3430_CLKSEL_L3_SHIFT 0 |
| 349 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | 355 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) |
| 356 | #define OMAP3430_CLKSEL_L3_WIDTH 2 | ||
| 350 | #define OMAP3630_CLKSEL_96M_SHIFT 12 | 357 | #define OMAP3630_CLKSEL_96M_SHIFT 12 |
| 351 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | 358 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) |
| 359 | #define OMAP3630_CLKSEL_96M_WIDTH 2 | ||
| 352 | 360 | ||
| 353 | /* CM_CLKSTCTRL_CORE */ | 361 | /* CM_CLKSTCTRL_CORE */ |
| 354 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | 362 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 |
| @@ -452,6 +460,7 @@ | |||
| 452 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | 460 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) |
| 453 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | 461 | #define OMAP3430_CLKSEL_RM_SHIFT 1 |
| 454 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | 462 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) |
| 463 | #define OMAP3430_CLKSEL_RM_WIDTH 2 | ||
| 455 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | 464 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 |
| 456 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | 465 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) |
| 457 | 466 | ||
| @@ -520,14 +529,17 @@ | |||
| 520 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | 529 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ |
| 521 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | 530 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 |
| 522 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | 531 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) |
| 532 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 | ||
| 523 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | 533 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 |
| 524 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | 534 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) |
| 525 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | 535 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 |
| 526 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | 536 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) |
| 527 | #define OMAP3430_SOURCE_96M_SHIFT 6 | 537 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
| 528 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) | 538 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) |
| 539 | #define OMAP3430_SOURCE_96M_WIDTH 1 | ||
| 529 | #define OMAP3430_SOURCE_54M_SHIFT 5 | 540 | #define OMAP3430_SOURCE_54M_SHIFT 5 |
| 530 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | 541 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) |
| 542 | #define OMAP3430_SOURCE_54M_WIDTH 1 | ||
| 531 | #define OMAP3430_SOURCE_48M_SHIFT 3 | 543 | #define OMAP3430_SOURCE_48M_SHIFT 3 |
| 532 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | 544 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) |
| 533 | 545 | ||
| @@ -545,7 +557,9 @@ | |||
| 545 | /* CM_CLKSEL3_PLL */ | 557 | /* CM_CLKSEL3_PLL */ |
| 546 | #define OMAP3430_DIV_96M_SHIFT 0 | 558 | #define OMAP3430_DIV_96M_SHIFT 0 |
| 547 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | 559 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) |
| 560 | #define OMAP3430_DIV_96M_WIDTH 5 | ||
| 548 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) | 561 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) |
| 562 | #define OMAP3630_DIV_96M_WIDTH 6 | ||
| 549 | 563 | ||
| 550 | /* CM_CLKSEL4_PLL */ | 564 | /* CM_CLKSEL4_PLL */ |
| 551 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | 565 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 |
| @@ -556,12 +570,14 @@ | |||
| 556 | /* CM_CLKSEL5_PLL */ | 570 | /* CM_CLKSEL5_PLL */ |
| 557 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | 571 | #define OMAP3430ES2_DIV_120M_SHIFT 0 |
| 558 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | 572 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) |
| 573 | #define OMAP3430ES2_DIV_120M_WIDTH 5 | ||
| 559 | 574 | ||
| 560 | /* CM_CLKOUT_CTRL */ | 575 | /* CM_CLKOUT_CTRL */ |
| 561 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | 576 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 |
| 562 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) | 577 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) |
| 563 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 | 578 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 |
| 564 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | 579 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) |
| 580 | #define OMAP3430_CLKOUT2_DIV_WIDTH 3 | ||
| 565 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | 581 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 |
| 566 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | 582 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) |
| 567 | 583 | ||
| @@ -592,10 +608,14 @@ | |||
| 592 | /* CM_CLKSEL_DSS */ | 608 | /* CM_CLKSEL_DSS */ |
| 593 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | 609 | #define OMAP3430_CLKSEL_TV_SHIFT 8 |
| 594 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | 610 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) |
| 611 | #define OMAP3430_CLKSEL_TV_WIDTH 5 | ||
| 595 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) | 612 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) |
| 613 | #define OMAP3630_CLKSEL_TV_WIDTH 6 | ||
| 596 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | 614 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
| 597 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | 615 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) |
| 616 | #define OMAP3430_CLKSEL_DSS1_WIDTH 5 | ||
| 598 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) | 617 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) |
| 618 | #define OMAP3630_CLKSEL_DSS1_WIDTH 6 | ||
| 599 | 619 | ||
| 600 | /* CM_SLEEPDEP_DSS specific bits */ | 620 | /* CM_SLEEPDEP_DSS specific bits */ |
| 601 | 621 | ||
| @@ -623,7 +643,9 @@ | |||
| 623 | /* CM_CLKSEL_CAM */ | 643 | /* CM_CLKSEL_CAM */ |
| 624 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | 644 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 |
| 625 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | 645 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) |
| 646 | #define OMAP3430_CLKSEL_CAM_WIDTH 5 | ||
| 626 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) | 647 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) |
| 648 | #define OMAP3630_CLKSEL_CAM_WIDTH 6 | ||
| 627 | 649 | ||
| 628 | /* CM_SLEEPDEP_CAM specific bits */ | 650 | /* CM_SLEEPDEP_CAM specific bits */ |
| 629 | 651 | ||
| @@ -721,21 +743,30 @@ | |||
| 721 | /* CM_CLKSEL1_EMU */ | 743 | /* CM_CLKSEL1_EMU */ |
| 722 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 744 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
| 723 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | 745 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) |
| 746 | #define OMAP3430_DIV_DPLL4_WIDTH 5 | ||
| 724 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) | 747 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) |
| 748 | #define OMAP3630_DIV_DPLL4_WIDTH 6 | ||
| 725 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | 749 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
| 726 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | 750 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) |
| 751 | #define OMAP3430_DIV_DPLL3_WIDTH 5 | ||
| 727 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | 752 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 |
| 728 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | 753 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) |
| 754 | #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 | ||
| 729 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | 755 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 |
| 730 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | 756 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) |
| 757 | #define OMAP3430_CLKSEL_PCLK_WIDTH 3 | ||
| 731 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | 758 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 |
| 732 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | 759 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) |
| 760 | #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 | ||
| 733 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | 761 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 |
| 734 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | 762 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) |
| 763 | #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 | ||
| 735 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | 764 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 |
| 736 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | 765 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) |
| 766 | #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 | ||
| 737 | #define OMAP3430_MUX_CTRL_SHIFT 0 | 767 | #define OMAP3430_MUX_CTRL_SHIFT 0 |
| 738 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | 768 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) |
| 769 | #define OMAP3430_MUX_CTRL_WIDTH 2 | ||
| 739 | 770 | ||
| 740 | /* CM_CLKSTCTRL_EMU */ | 771 | /* CM_CLKSTCTRL_EMU */ |
| 741 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | 772 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 |