diff options
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 632 |
1 files changed, 0 insertions, 632 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index adf78d325804..04dab2fcf862 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -14,833 +14,201 @@ | |||
| 14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | /* Bits shared between registers */ | ||
| 18 | |||
| 19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
| 20 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | ||
| 21 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | 17 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 |
| 22 | #define OMAP3430_EN_MSPRO_MASK (1 << 23) | ||
| 23 | #define OMAP3430_EN_MSPRO_SHIFT 23 | 18 | #define OMAP3430_EN_MSPRO_SHIFT 23 |
| 24 | #define OMAP3430_EN_HDQ_MASK (1 << 22) | ||
| 25 | #define OMAP3430_EN_HDQ_SHIFT 22 | 19 | #define OMAP3430_EN_HDQ_SHIFT 22 |
| 26 | #define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) | ||
| 27 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 | 20 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 |
| 28 | #define OMAP3430ES1_EN_D2D_MASK (1 << 3) | ||
| 29 | #define OMAP3430ES1_EN_D2D_SHIFT 3 | 21 | #define OMAP3430ES1_EN_D2D_SHIFT 3 |
| 30 | #define OMAP3430_EN_SSI_MASK (1 << 0) | ||
| 31 | #define OMAP3430_EN_SSI_SHIFT 0 | 22 | #define OMAP3430_EN_SSI_SHIFT 0 |
| 32 | |||
| 33 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | ||
| 34 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 | 23 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 |
| 35 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | ||
| 36 | |||
| 37 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
| 38 | #define OMAP3430_EN_WDT2_MASK (1 << 5) | ||
| 39 | #define OMAP3430_EN_WDT2_SHIFT 5 | 24 | #define OMAP3430_EN_WDT2_SHIFT 5 |
| 40 | |||
| 41 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | ||
| 42 | #define OMAP3430_EN_CAM_MASK (1 << 0) | ||
| 43 | #define OMAP3430_EN_CAM_SHIFT 0 | 25 | #define OMAP3430_EN_CAM_SHIFT 0 |
| 44 | |||
| 45 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | ||
| 46 | #define OMAP3430_EN_WDT3_MASK (1 << 12) | ||
| 47 | #define OMAP3430_EN_WDT3_SHIFT 12 | 26 | #define OMAP3430_EN_WDT3_SHIFT 12 |
| 48 | |||
| 49 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | ||
| 50 | #define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) | ||
| 51 | |||
| 52 | |||
| 53 | /* Bits specific to each register */ | ||
| 54 | |||
| 55 | /* CM_FCLKEN_IVA2 */ | ||
| 56 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) | 27 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
| 57 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 | 28 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
| 58 | |||
| 59 | /* CM_CLKEN_PLL_IVA2 */ | ||
| 60 | #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 | ||
| 61 | #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 62 | #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 | ||
| 63 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) | 29 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) |
| 64 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 | 30 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 |
| 65 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 66 | #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 | ||
| 67 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | 31 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) |
| 68 | |||
| 69 | /* CM_IDLEST_IVA2 */ | ||
| 70 | #define OMAP3430_ST_IVA2_SHIFT 0 | 32 | #define OMAP3430_ST_IVA2_SHIFT 0 |
| 71 | #define OMAP3430_ST_IVA2_MASK (1 << 0) | ||
| 72 | |||
| 73 | /* CM_IDLEST_PLL_IVA2 */ | ||
| 74 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 | ||
| 75 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | 33 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) |
| 76 | |||
| 77 | /* CM_AUTOIDLE_PLL_IVA2 */ | ||
| 78 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | ||
| 79 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) | 34 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) |
| 80 | |||
| 81 | /* CM_CLKSEL1_PLL_IVA2 */ | ||
| 82 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | 35 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 |
| 83 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) | ||
| 84 | #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 | 36 | #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 |
| 85 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 | ||
| 86 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | 37 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) |
| 87 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | ||
| 88 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) | 38 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) |
| 89 | |||
| 90 | /* CM_CLKSEL2_PLL_IVA2 */ | ||
| 91 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | 39 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 |
| 92 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 93 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 | 40 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 |
| 94 | |||
| 95 | /* CM_CLKSTCTRL_IVA2 */ | ||
| 96 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | ||
| 97 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | 41 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) |
| 98 | |||
| 99 | /* CM_CLKSTST_IVA2 */ | ||
| 100 | #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 | ||
| 101 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) | 42 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) |
| 102 | |||
| 103 | /* CM_REVISION specific bits */ | ||
| 104 | |||
| 105 | /* CM_SYSCONFIG specific bits */ | ||
| 106 | |||
| 107 | /* CM_CLKEN_PLL_MPU */ | ||
| 108 | #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 | ||
| 109 | #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 110 | #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 | ||
| 111 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) | 43 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) |
| 112 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 | 44 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 |
| 113 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 114 | #define OMAP3430_EN_MPU_DPLL_SHIFT 0 | ||
| 115 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | 45 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) |
| 116 | |||
| 117 | /* CM_IDLEST_MPU */ | ||
| 118 | #define OMAP3430_ST_MPU_MASK (1 << 0) | ||
| 119 | |||
| 120 | /* CM_IDLEST_PLL_MPU */ | ||
| 121 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 | 46 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
| 122 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) | 47 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
| 123 | #define OMAP3430_ST_MPU_CLK_WIDTH 1 | 48 | #define OMAP3430_ST_MPU_CLK_WIDTH 1 |
| 124 | |||
| 125 | /* CM_AUTOIDLE_PLL_MPU */ | ||
| 126 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | ||
| 127 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) | 49 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) |
| 128 | |||
| 129 | /* CM_CLKSEL1_PLL_MPU */ | ||
| 130 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | 50 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 |
| 131 | #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) | ||
| 132 | #define OMAP3430_MPU_CLK_SRC_WIDTH 3 | 51 | #define OMAP3430_MPU_CLK_SRC_WIDTH 3 |
| 133 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 | ||
| 134 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | 52 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) |
| 135 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | ||
| 136 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) | 53 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) |
| 137 | |||
| 138 | /* CM_CLKSEL2_PLL_MPU */ | ||
| 139 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | 54 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 |
| 140 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 141 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 | 55 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 |
| 142 | |||
| 143 | /* CM_CLKSTCTRL_MPU */ | ||
| 144 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | ||
| 145 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | 56 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) |
| 146 | |||
| 147 | /* CM_CLKSTST_MPU */ | ||
| 148 | #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 | ||
| 149 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | ||
| 150 | |||
| 151 | /* CM_FCLKEN1_CORE specific bits */ | ||
| 152 | #define OMAP3430_EN_MODEM_MASK (1 << 31) | ||
| 153 | #define OMAP3430_EN_MODEM_SHIFT 31 | 57 | #define OMAP3430_EN_MODEM_SHIFT 31 |
| 154 | |||
| 155 | /* CM_ICLKEN1_CORE specific bits */ | ||
| 156 | #define OMAP3430_EN_ICR_MASK (1 << 29) | ||
| 157 | #define OMAP3430_EN_ICR_SHIFT 29 | 58 | #define OMAP3430_EN_ICR_SHIFT 29 |
| 158 | #define OMAP3430_EN_AES2_MASK (1 << 28) | ||
| 159 | #define OMAP3430_EN_AES2_SHIFT 28 | 59 | #define OMAP3430_EN_AES2_SHIFT 28 |
| 160 | #define OMAP3430_EN_SHA12_MASK (1 << 27) | ||
| 161 | #define OMAP3430_EN_SHA12_SHIFT 27 | 60 | #define OMAP3430_EN_SHA12_SHIFT 27 |
| 162 | #define OMAP3430_EN_DES2_MASK (1 << 26) | ||
| 163 | #define OMAP3430_EN_DES2_SHIFT 26 | 61 | #define OMAP3430_EN_DES2_SHIFT 26 |
| 164 | #define OMAP3430ES1_EN_FAC_MASK (1 << 8) | ||
| 165 | #define OMAP3430ES1_EN_FAC_SHIFT 8 | 62 | #define OMAP3430ES1_EN_FAC_SHIFT 8 |
| 166 | #define OMAP3430_EN_MAILBOXES_MASK (1 << 7) | ||
| 167 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 | 63 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 |
| 168 | #define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) | ||
| 169 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 | 64 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 |
| 170 | #define OMAP3430_EN_SAD2D_MASK (1 << 3) | ||
| 171 | #define OMAP3430_EN_SAD2D_SHIFT 3 | 65 | #define OMAP3430_EN_SAD2D_SHIFT 3 |
| 172 | #define OMAP3430_EN_SDRC_MASK (1 << 1) | ||
| 173 | #define OMAP3430_EN_SDRC_SHIFT 1 | 66 | #define OMAP3430_EN_SDRC_SHIFT 1 |
| 174 | |||
| 175 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | ||
| 176 | #define AM35XX_EN_IPSS_MASK (1 << 4) | ||
| 177 | #define AM35XX_EN_IPSS_SHIFT 4 | 67 | #define AM35XX_EN_IPSS_SHIFT 4 |
| 178 | |||
| 179 | /* CM_ICLKEN2_CORE */ | ||
| 180 | #define OMAP3430_EN_PKA_MASK (1 << 4) | ||
| 181 | #define OMAP3430_EN_PKA_SHIFT 4 | 68 | #define OMAP3430_EN_PKA_SHIFT 4 |
| 182 | #define OMAP3430_EN_AES1_MASK (1 << 3) | ||
| 183 | #define OMAP3430_EN_AES1_SHIFT 3 | 69 | #define OMAP3430_EN_AES1_SHIFT 3 |
| 184 | #define OMAP3430_EN_RNG_MASK (1 << 2) | ||
| 185 | #define OMAP3430_EN_RNG_SHIFT 2 | 70 | #define OMAP3430_EN_RNG_SHIFT 2 |
| 186 | #define OMAP3430_EN_SHA11_MASK (1 << 1) | ||
| 187 | #define OMAP3430_EN_SHA11_SHIFT 1 | 71 | #define OMAP3430_EN_SHA11_SHIFT 1 |
| 188 | #define OMAP3430_EN_DES1_MASK (1 << 0) | ||
| 189 | #define OMAP3430_EN_DES1_SHIFT 0 | 72 | #define OMAP3430_EN_DES1_SHIFT 0 |
| 190 | |||
| 191 | /* CM_ICLKEN3_CORE */ | ||
| 192 | #define OMAP3430_EN_MAD2D_SHIFT 3 | 73 | #define OMAP3430_EN_MAD2D_SHIFT 3 |
| 193 | #define OMAP3430_EN_MAD2D_MASK (1 << 3) | ||
| 194 | |||
| 195 | /* CM_FCLKEN3_CORE specific bits */ | ||
| 196 | #define OMAP3430ES2_EN_TS_SHIFT 1 | 74 | #define OMAP3430ES2_EN_TS_SHIFT 1 |
| 197 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | ||
| 198 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 | 75 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 |
| 199 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | ||
| 200 | |||
| 201 | /* CM_IDLEST1_CORE specific bits */ | ||
| 202 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 | ||
| 203 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) | ||
| 204 | #define OMAP3430_ST_ICR_SHIFT 29 | ||
| 205 | #define OMAP3430_ST_ICR_MASK (1 << 29) | ||
| 206 | #define OMAP3430_ST_AES2_SHIFT 28 | 76 | #define OMAP3430_ST_AES2_SHIFT 28 |
| 207 | #define OMAP3430_ST_AES2_MASK (1 << 28) | ||
| 208 | #define OMAP3430_ST_SHA12_SHIFT 27 | 77 | #define OMAP3430_ST_SHA12_SHIFT 27 |
| 209 | #define OMAP3430_ST_SHA12_MASK (1 << 27) | ||
| 210 | #define OMAP3430_ST_DES2_SHIFT 26 | ||
| 211 | #define OMAP3430_ST_DES2_MASK (1 << 26) | ||
| 212 | #define OMAP3430_ST_MSPRO_SHIFT 23 | ||
| 213 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | ||
| 214 | #define AM35XX_ST_UART4_SHIFT 23 | 78 | #define AM35XX_ST_UART4_SHIFT 23 |
| 215 | #define AM35XX_ST_UART4_MASK (1 << 23) | ||
| 216 | #define OMAP3430_ST_HDQ_SHIFT 22 | 79 | #define OMAP3430_ST_HDQ_SHIFT 22 |
| 217 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | ||
| 218 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | ||
| 219 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | ||
| 220 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | 80 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 |
| 221 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | ||
| 222 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | 81 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 |
| 223 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | ||
| 224 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | ||
| 225 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | ||
| 226 | #define OMAP3430_ST_SAD2D_SHIFT 3 | 82 | #define OMAP3430_ST_SAD2D_SHIFT 3 |
| 227 | #define OMAP3430_ST_SAD2D_MASK (1 << 3) | ||
| 228 | #define OMAP3430_ST_SDMA_SHIFT 2 | 83 | #define OMAP3430_ST_SDMA_SHIFT 2 |
| 229 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | ||
| 230 | #define OMAP3430_ST_SDRC_SHIFT 1 | ||
| 231 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | ||
| 232 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | ||
| 233 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | ||
| 234 | |||
| 235 | /* AM35xx specific CM_IDLEST1_CORE bits */ | ||
| 236 | #define AM35XX_ST_IPSS_SHIFT 5 | 84 | #define AM35XX_ST_IPSS_SHIFT 5 |
| 237 | #define AM35XX_ST_IPSS_MASK (1 << 5) | ||
| 238 | |||
| 239 | /* CM_IDLEST2_CORE */ | ||
| 240 | #define OMAP3430_ST_PKA_SHIFT 4 | ||
| 241 | #define OMAP3430_ST_PKA_MASK (1 << 4) | ||
| 242 | #define OMAP3430_ST_AES1_SHIFT 3 | ||
| 243 | #define OMAP3430_ST_AES1_MASK (1 << 3) | ||
| 244 | #define OMAP3430_ST_RNG_SHIFT 2 | ||
| 245 | #define OMAP3430_ST_RNG_MASK (1 << 2) | ||
| 246 | #define OMAP3430_ST_SHA11_SHIFT 1 | ||
| 247 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | ||
| 248 | #define OMAP3430_ST_DES1_SHIFT 0 | ||
| 249 | #define OMAP3430_ST_DES1_MASK (1 << 0) | ||
| 250 | |||
| 251 | /* CM_IDLEST3_CORE */ | ||
| 252 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | 85 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 |
| 253 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | ||
| 254 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 | ||
| 255 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | ||
| 256 | |||
| 257 | /* CM_AUTOIDLE1_CORE */ | ||
| 258 | #define OMAP3430_AUTO_MODEM_MASK (1 << 31) | ||
| 259 | #define OMAP3430_AUTO_MODEM_SHIFT 31 | ||
| 260 | #define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) | ||
| 261 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | ||
| 262 | #define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) | ||
| 263 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 | ||
| 264 | #define OMAP3430_AUTO_AES2_MASK (1 << 28) | ||
| 265 | #define OMAP3430_AUTO_AES2_SHIFT 28 | ||
| 266 | #define OMAP3430_AUTO_SHA12_MASK (1 << 27) | ||
| 267 | #define OMAP3430_AUTO_SHA12_SHIFT 27 | ||
| 268 | #define OMAP3430_AUTO_DES2_MASK (1 << 26) | ||
| 269 | #define OMAP3430_AUTO_DES2_SHIFT 26 | ||
| 270 | #define OMAP3430_AUTO_MMC2_MASK (1 << 25) | ||
| 271 | #define OMAP3430_AUTO_MMC2_SHIFT 25 | ||
| 272 | #define OMAP3430_AUTO_MMC1_MASK (1 << 24) | ||
| 273 | #define OMAP3430_AUTO_MMC1_SHIFT 24 | ||
| 274 | #define OMAP3430_AUTO_MSPRO_MASK (1 << 23) | ||
| 275 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 | ||
| 276 | #define OMAP3430_AUTO_HDQ_MASK (1 << 22) | ||
| 277 | #define OMAP3430_AUTO_HDQ_SHIFT 22 | ||
| 278 | #define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) | ||
| 279 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 | ||
| 280 | #define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) | ||
| 281 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 | ||
| 282 | #define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) | ||
| 283 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 | ||
| 284 | #define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) | ||
| 285 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 | ||
| 286 | #define OMAP3430_AUTO_I2C3_MASK (1 << 17) | ||
| 287 | #define OMAP3430_AUTO_I2C3_SHIFT 17 | ||
| 288 | #define OMAP3430_AUTO_I2C2_MASK (1 << 16) | ||
| 289 | #define OMAP3430_AUTO_I2C2_SHIFT 16 | ||
| 290 | #define OMAP3430_AUTO_I2C1_MASK (1 << 15) | ||
| 291 | #define OMAP3430_AUTO_I2C1_SHIFT 15 | ||
| 292 | #define OMAP3430_AUTO_UART2_MASK (1 << 14) | ||
| 293 | #define OMAP3430_AUTO_UART2_SHIFT 14 | ||
| 294 | #define OMAP3430_AUTO_UART1_MASK (1 << 13) | ||
| 295 | #define OMAP3430_AUTO_UART1_SHIFT 13 | ||
| 296 | #define OMAP3430_AUTO_GPT11_MASK (1 << 12) | ||
| 297 | #define OMAP3430_AUTO_GPT11_SHIFT 12 | ||
| 298 | #define OMAP3430_AUTO_GPT10_MASK (1 << 11) | ||
| 299 | #define OMAP3430_AUTO_GPT10_SHIFT 11 | ||
| 300 | #define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) | ||
| 301 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 | ||
| 302 | #define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) | ||
| 303 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 | ||
| 304 | #define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) | ||
| 305 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 | ||
| 306 | #define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) | ||
| 307 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 | ||
| 308 | #define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) | ||
| 309 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 | ||
| 310 | #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) | ||
| 311 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 | ||
| 312 | #define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) | ||
| 313 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 | ||
| 314 | #define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) | ||
| 315 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 | ||
| 316 | #define OMAP3430_AUTO_SAD2D_MASK (1 << 3) | ||
| 317 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 | ||
| 318 | #define OMAP3430_AUTO_SSI_MASK (1 << 0) | ||
| 319 | #define OMAP3430_AUTO_SSI_SHIFT 0 | ||
| 320 | |||
| 321 | /* CM_AUTOIDLE2_CORE */ | ||
| 322 | #define OMAP3430_AUTO_PKA_MASK (1 << 4) | ||
| 323 | #define OMAP3430_AUTO_PKA_SHIFT 4 | ||
| 324 | #define OMAP3430_AUTO_AES1_MASK (1 << 3) | ||
| 325 | #define OMAP3430_AUTO_AES1_SHIFT 3 | ||
| 326 | #define OMAP3430_AUTO_RNG_MASK (1 << 2) | ||
| 327 | #define OMAP3430_AUTO_RNG_SHIFT 2 | ||
| 328 | #define OMAP3430_AUTO_SHA11_MASK (1 << 1) | ||
| 329 | #define OMAP3430_AUTO_SHA11_SHIFT 1 | ||
| 330 | #define OMAP3430_AUTO_DES1_MASK (1 << 0) | ||
| 331 | #define OMAP3430_AUTO_DES1_SHIFT 0 | ||
| 332 | |||
| 333 | /* CM_AUTOIDLE3_CORE */ | ||
| 334 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) | ||
| 335 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
| 336 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | ||
| 337 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | ||
| 338 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | ||
| 339 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 | ||
| 340 | #define OMAP3430_AUTO_MAD2D_MASK (1 << 3) | ||
| 341 | |||
| 342 | /* CM_CLKSEL_CORE */ | ||
| 343 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | ||
| 344 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) | 86 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) |
| 345 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) | 87 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) |
| 346 | #define OMAP3430_CLKSEL_GPT11_SHIFT 7 | ||
| 347 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) | 88 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) |
| 348 | #define OMAP3430_CLKSEL_GPT10_SHIFT 6 | ||
| 349 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 | ||
| 350 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | 89 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) |
| 351 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | 90 | #define OMAP3430_CLKSEL_L4_SHIFT 2 |
| 352 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | ||
| 353 | #define OMAP3430_CLKSEL_L4_WIDTH 2 | 91 | #define OMAP3430_CLKSEL_L4_WIDTH 2 |
| 354 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | 92 | #define OMAP3430_CLKSEL_L3_SHIFT 0 |
| 355 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | ||
| 356 | #define OMAP3430_CLKSEL_L3_WIDTH 2 | 93 | #define OMAP3430_CLKSEL_L3_WIDTH 2 |
| 357 | #define OMAP3630_CLKSEL_96M_SHIFT 12 | ||
| 358 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | 94 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) |
| 359 | #define OMAP3630_CLKSEL_96M_WIDTH 2 | ||
| 360 | |||
| 361 | /* CM_CLKSTCTRL_CORE */ | ||
| 362 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | ||
| 363 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) | 95 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) |
| 364 | #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 | ||
| 365 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) | 96 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) |
| 366 | #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 | ||
| 367 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | 97 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) |
| 368 | |||
| 369 | /* CM_CLKSTST_CORE */ | ||
| 370 | #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 | ||
| 371 | #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) | ||
| 372 | #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 | ||
| 373 | #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) | ||
| 374 | #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 | ||
| 375 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | ||
| 376 | |||
| 377 | /* CM_FCLKEN_GFX */ | ||
| 378 | #define OMAP3430ES1_EN_3D_MASK (1 << 2) | ||
| 379 | #define OMAP3430ES1_EN_3D_SHIFT 2 | 98 | #define OMAP3430ES1_EN_3D_SHIFT 2 |
| 380 | #define OMAP3430ES1_EN_2D_MASK (1 << 1) | ||
| 381 | #define OMAP3430ES1_EN_2D_SHIFT 1 | 99 | #define OMAP3430ES1_EN_2D_SHIFT 1 |
| 382 | |||
| 383 | /* CM_ICLKEN_GFX specific bits */ | ||
| 384 | |||
| 385 | /* CM_IDLEST_GFX specific bits */ | ||
| 386 | |||
| 387 | /* CM_CLKSEL_GFX specific bits */ | ||
| 388 | |||
| 389 | /* CM_SLEEPDEP_GFX specific bits */ | ||
| 390 | |||
| 391 | /* CM_CLKSTCTRL_GFX */ | ||
| 392 | #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 | ||
| 393 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | 100 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) |
| 394 | |||
| 395 | /* CM_CLKSTST_GFX */ | ||
| 396 | #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 | ||
| 397 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | ||
| 398 | |||
| 399 | /* CM_FCLKEN_SGX */ | ||
| 400 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 | 101 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
| 401 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | ||
| 402 | |||
| 403 | /* CM_IDLEST_SGX */ | ||
| 404 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | ||
| 405 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | ||
| 406 | |||
| 407 | /* CM_ICLKEN_SGX */ | ||
| 408 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | 102 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 |
| 409 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | ||
| 410 | |||
| 411 | /* CM_CLKSEL_SGX */ | ||
| 412 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | ||
| 413 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | 103 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) |
| 414 | |||
| 415 | /* CM_CLKSTCTRL_SGX */ | ||
| 416 | #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 | ||
| 417 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) | 104 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) |
| 418 | |||
| 419 | /* CM_CLKSTST_SGX */ | ||
| 420 | #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 | ||
| 421 | #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) | ||
| 422 | |||
| 423 | /* CM_FCLKEN_WKUP specific bits */ | ||
| 424 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | 105 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 |
| 425 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) | ||
| 426 | |||
| 427 | /* CM_ICLKEN_WKUP specific bits */ | ||
| 428 | #define OMAP3430_EN_WDT1_MASK (1 << 4) | ||
| 429 | #define OMAP3430_EN_WDT1_SHIFT 4 | 106 | #define OMAP3430_EN_WDT1_SHIFT 4 |
| 430 | #define OMAP3430_EN_32KSYNC_MASK (1 << 2) | ||
| 431 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | 107 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
| 432 | |||
| 433 | /* CM_IDLEST_WKUP specific bits */ | ||
| 434 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 | ||
| 435 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) | ||
| 436 | #define OMAP3430_ST_WDT2_SHIFT 5 | 108 | #define OMAP3430_ST_WDT2_SHIFT 5 |
| 437 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | ||
| 438 | #define OMAP3430_ST_WDT1_SHIFT 4 | ||
| 439 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | ||
| 440 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | 109 | #define OMAP3430_ST_32KSYNC_SHIFT 2 |
| 441 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | ||
| 442 | |||
| 443 | /* CM_AUTOIDLE_WKUP */ | ||
| 444 | #define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) | ||
| 445 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | ||
| 446 | #define OMAP3430_AUTO_WDT2_MASK (1 << 5) | ||
| 447 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | ||
| 448 | #define OMAP3430_AUTO_WDT1_MASK (1 << 4) | ||
| 449 | #define OMAP3430_AUTO_WDT1_SHIFT 4 | ||
| 450 | #define OMAP3430_AUTO_GPIO1_MASK (1 << 3) | ||
| 451 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 | ||
| 452 | #define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) | ||
| 453 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 | ||
| 454 | #define OMAP3430_AUTO_GPT12_MASK (1 << 1) | ||
| 455 | #define OMAP3430_AUTO_GPT12_SHIFT 1 | ||
| 456 | #define OMAP3430_AUTO_GPT1_MASK (1 << 0) | ||
| 457 | #define OMAP3430_AUTO_GPT1_SHIFT 0 | ||
| 458 | |||
| 459 | /* CM_CLKSEL_WKUP */ | ||
| 460 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | 110 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) |
| 461 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | 111 | #define OMAP3430_CLKSEL_RM_SHIFT 1 |
| 462 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | ||
| 463 | #define OMAP3430_CLKSEL_RM_WIDTH 2 | 112 | #define OMAP3430_CLKSEL_RM_WIDTH 2 |
| 464 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | ||
| 465 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | 113 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) |
| 466 | |||
| 467 | /* CM_CLKEN_PLL */ | ||
| 468 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 | 114 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 |
| 469 | #define OMAP3430_PWRDN_CAM_SHIFT 30 | 115 | #define OMAP3430_PWRDN_CAM_SHIFT 30 |
| 470 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 | 116 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 |
| 471 | #define OMAP3430_PWRDN_TV_SHIFT 28 | 117 | #define OMAP3430_PWRDN_TV_SHIFT 28 |
| 472 | #define OMAP3430_PWRDN_96M_SHIFT 27 | 118 | #define OMAP3430_PWRDN_96M_SHIFT 27 |
| 473 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 | ||
| 474 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) | ||
| 475 | #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 | ||
| 476 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) | 119 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) |
| 477 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 | 120 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 |
| 478 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) | ||
| 479 | #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 | ||
| 480 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) | 121 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) |
| 481 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 | 122 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 |
| 482 | #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 | ||
| 483 | #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 484 | #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 | ||
| 485 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) | 123 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) |
| 486 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 | 124 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 |
| 487 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 488 | #define OMAP3430_EN_CORE_DPLL_SHIFT 0 | ||
| 489 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | 125 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) |
| 490 | |||
| 491 | /* CM_CLKEN2_PLL */ | ||
| 492 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 | ||
| 493 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 494 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | ||
| 495 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | 126 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) |
| 496 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 | 127 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 |
| 497 | #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 | ||
| 498 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | 128 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) |
| 499 | |||
| 500 | /* CM_IDLEST_CKGEN */ | ||
| 501 | #define OMAP3430_ST_54M_CLK_MASK (1 << 5) | ||
| 502 | #define OMAP3430_ST_12M_CLK_MASK (1 << 4) | ||
| 503 | #define OMAP3430_ST_48M_CLK_MASK (1 << 3) | ||
| 504 | #define OMAP3430_ST_96M_CLK_MASK (1 << 2) | ||
| 505 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 | ||
| 506 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) | 129 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) |
| 507 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | ||
| 508 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | 130 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) |
| 509 | |||
| 510 | /* CM_IDLEST2_CKGEN */ | ||
| 511 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 | ||
| 512 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | ||
| 513 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | ||
| 514 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | ||
| 515 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | ||
| 516 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) | 131 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) |
| 517 | |||
| 518 | /* CM_AUTOIDLE_PLL */ | ||
| 519 | #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 | ||
| 520 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) | 132 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) |
| 521 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | ||
| 522 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | 133 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) |
| 523 | |||
| 524 | /* CM_AUTOIDLE2_PLL */ | ||
| 525 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 | ||
| 526 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) | 134 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) |
| 527 | |||
| 528 | /* CM_CLKSEL1_PLL */ | ||
| 529 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | ||
| 530 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | 135 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 |
| 531 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | ||
| 532 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 | 136 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 |
| 533 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | ||
| 534 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | 137 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) |
| 535 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | ||
| 536 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | 138 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) |
| 537 | #define OMAP3430_SOURCE_96M_SHIFT 6 | 139 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
| 538 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) | ||
| 539 | #define OMAP3430_SOURCE_96M_WIDTH 1 | 140 | #define OMAP3430_SOURCE_96M_WIDTH 1 |
| 540 | #define OMAP3430_SOURCE_54M_SHIFT 5 | 141 | #define OMAP3430_SOURCE_54M_SHIFT 5 |
| 541 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | ||
| 542 | #define OMAP3430_SOURCE_54M_WIDTH 1 | 142 | #define OMAP3430_SOURCE_54M_WIDTH 1 |
| 543 | #define OMAP3430_SOURCE_48M_SHIFT 3 | ||
| 544 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | 143 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) |
| 545 | |||
| 546 | /* CM_CLKSEL2_PLL */ | ||
| 547 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | ||
| 548 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | 144 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) |
| 549 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) | 145 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) |
| 550 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 | ||
| 551 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | 146 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) |
| 552 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 | ||
| 553 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) | 147 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) |
| 554 | #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 | ||
| 555 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) | 148 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) |
| 556 | |||
| 557 | /* CM_CLKSEL3_PLL */ | ||
| 558 | #define OMAP3430_DIV_96M_SHIFT 0 | 149 | #define OMAP3430_DIV_96M_SHIFT 0 |
| 559 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | ||
| 560 | #define OMAP3430_DIV_96M_WIDTH 5 | ||
| 561 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) | ||
| 562 | #define OMAP3630_DIV_96M_WIDTH 6 | 150 | #define OMAP3630_DIV_96M_WIDTH 6 |
| 563 | |||
| 564 | /* CM_CLKSEL4_PLL */ | ||
| 565 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | ||
| 566 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) | 151 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) |
| 567 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 | ||
| 568 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) | 152 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) |
| 569 | |||
| 570 | /* CM_CLKSEL5_PLL */ | ||
| 571 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | 153 | #define OMAP3430ES2_DIV_120M_SHIFT 0 |
| 572 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | ||
| 573 | #define OMAP3430ES2_DIV_120M_WIDTH 5 | 154 | #define OMAP3430ES2_DIV_120M_WIDTH 5 |
| 574 | |||
| 575 | /* CM_CLKOUT_CTRL */ | ||
| 576 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | 155 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 |
| 577 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) | ||
| 578 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 | 156 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 |
| 579 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | ||
| 580 | #define OMAP3430_CLKOUT2_DIV_WIDTH 3 | 157 | #define OMAP3430_CLKOUT2_DIV_WIDTH 3 |
| 581 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | ||
| 582 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | 158 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) |
| 583 | |||
| 584 | /* CM_FCLKEN_DSS */ | ||
| 585 | #define OMAP3430_EN_TV_MASK (1 << 2) | ||
| 586 | #define OMAP3430_EN_TV_SHIFT 2 | 159 | #define OMAP3430_EN_TV_SHIFT 2 |
| 587 | #define OMAP3430_EN_DSS2_MASK (1 << 1) | ||
| 588 | #define OMAP3430_EN_DSS2_SHIFT 1 | 160 | #define OMAP3430_EN_DSS2_SHIFT 1 |
| 589 | #define OMAP3430_EN_DSS1_MASK (1 << 0) | ||
| 590 | #define OMAP3430_EN_DSS1_SHIFT 0 | 161 | #define OMAP3430_EN_DSS1_SHIFT 0 |
| 591 | |||
| 592 | /* CM_ICLKEN_DSS */ | ||
| 593 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) | ||
| 594 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | 162 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
| 595 | |||
| 596 | /* CM_IDLEST_DSS */ | ||
| 597 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 | 163 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
| 598 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | ||
| 599 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | 164 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 |
| 600 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | ||
| 601 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | 165 | #define OMAP3430ES1_ST_DSS_SHIFT 0 |
| 602 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | ||
| 603 | |||
| 604 | /* CM_AUTOIDLE_DSS */ | ||
| 605 | #define OMAP3430_AUTO_DSS_MASK (1 << 0) | ||
| 606 | #define OMAP3430_AUTO_DSS_SHIFT 0 | ||
| 607 | |||
| 608 | /* CM_CLKSEL_DSS */ | ||
| 609 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | 166 | #define OMAP3430_CLKSEL_TV_SHIFT 8 |
| 610 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | ||
| 611 | #define OMAP3430_CLKSEL_TV_WIDTH 5 | ||
| 612 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) | ||
| 613 | #define OMAP3630_CLKSEL_TV_WIDTH 6 | 167 | #define OMAP3630_CLKSEL_TV_WIDTH 6 |
| 614 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | 168 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
| 615 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | ||
| 616 | #define OMAP3430_CLKSEL_DSS1_WIDTH 5 | ||
| 617 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) | ||
| 618 | #define OMAP3630_CLKSEL_DSS1_WIDTH 6 | 169 | #define OMAP3630_CLKSEL_DSS1_WIDTH 6 |
| 619 | |||
| 620 | /* CM_SLEEPDEP_DSS specific bits */ | ||
| 621 | |||
| 622 | /* CM_CLKSTCTRL_DSS */ | ||
| 623 | #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 | ||
| 624 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | 170 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) |
| 625 | |||
| 626 | /* CM_CLKSTST_DSS */ | ||
| 627 | #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 | ||
| 628 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | ||
| 629 | |||
| 630 | /* CM_FCLKEN_CAM specific bits */ | ||
| 631 | #define OMAP3430_EN_CSI2_MASK (1 << 1) | ||
| 632 | #define OMAP3430_EN_CSI2_SHIFT 1 | 171 | #define OMAP3430_EN_CSI2_SHIFT 1 |
| 633 | |||
| 634 | /* CM_ICLKEN_CAM specific bits */ | ||
| 635 | |||
| 636 | /* CM_IDLEST_CAM */ | ||
| 637 | #define OMAP3430_ST_CAM_MASK (1 << 0) | ||
| 638 | |||
| 639 | /* CM_AUTOIDLE_CAM */ | ||
| 640 | #define OMAP3430_AUTO_CAM_MASK (1 << 0) | ||
| 641 | #define OMAP3430_AUTO_CAM_SHIFT 0 | ||
| 642 | |||
| 643 | /* CM_CLKSEL_CAM */ | ||
| 644 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | 172 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 |
| 645 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | ||
| 646 | #define OMAP3430_CLKSEL_CAM_WIDTH 5 | ||
| 647 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) | ||
| 648 | #define OMAP3630_CLKSEL_CAM_WIDTH 6 | 173 | #define OMAP3630_CLKSEL_CAM_WIDTH 6 |
| 649 | |||
| 650 | /* CM_SLEEPDEP_CAM specific bits */ | ||
| 651 | |||
| 652 | /* CM_CLKSTCTRL_CAM */ | ||
| 653 | #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 | ||
| 654 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | 174 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) |
| 655 | |||
| 656 | /* CM_CLKSTST_CAM */ | ||
| 657 | #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 | ||
| 658 | #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) | ||
| 659 | |||
| 660 | /* CM_FCLKEN_PER specific bits */ | ||
| 661 | |||
| 662 | /* CM_ICLKEN_PER specific bits */ | ||
| 663 | |||
| 664 | /* CM_IDLEST_PER */ | ||
| 665 | #define OMAP3430_ST_WDT3_SHIFT 12 | ||
| 666 | #define OMAP3430_ST_WDT3_MASK (1 << 12) | ||
| 667 | #define OMAP3430_ST_MCBSP4_SHIFT 2 | 175 | #define OMAP3430_ST_MCBSP4_SHIFT 2 |
| 668 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) | ||
| 669 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | 176 | #define OMAP3430_ST_MCBSP3_SHIFT 1 |
| 670 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | ||
| 671 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | 177 | #define OMAP3430_ST_MCBSP2_SHIFT 0 |
| 672 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | ||
| 673 | |||
| 674 | /* CM_AUTOIDLE_PER */ | ||
| 675 | #define OMAP3630_AUTO_UART4_MASK (1 << 18) | ||
| 676 | #define OMAP3630_AUTO_UART4_SHIFT 18 | ||
| 677 | #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) | ||
| 678 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 | ||
| 679 | #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) | ||
| 680 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 | ||
| 681 | #define OMAP3430_AUTO_GPIO4_MASK (1 << 15) | ||
| 682 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 | ||
| 683 | #define OMAP3430_AUTO_GPIO3_MASK (1 << 14) | ||
| 684 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 | ||
| 685 | #define OMAP3430_AUTO_GPIO2_MASK (1 << 13) | ||
| 686 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 | ||
| 687 | #define OMAP3430_AUTO_WDT3_MASK (1 << 12) | ||
| 688 | #define OMAP3430_AUTO_WDT3_SHIFT 12 | ||
| 689 | #define OMAP3430_AUTO_UART3_MASK (1 << 11) | ||
| 690 | #define OMAP3430_AUTO_UART3_SHIFT 11 | ||
| 691 | #define OMAP3430_AUTO_GPT9_MASK (1 << 10) | ||
| 692 | #define OMAP3430_AUTO_GPT9_SHIFT 10 | ||
| 693 | #define OMAP3430_AUTO_GPT8_MASK (1 << 9) | ||
| 694 | #define OMAP3430_AUTO_GPT8_SHIFT 9 | ||
| 695 | #define OMAP3430_AUTO_GPT7_MASK (1 << 8) | ||
| 696 | #define OMAP3430_AUTO_GPT7_SHIFT 8 | ||
| 697 | #define OMAP3430_AUTO_GPT6_MASK (1 << 7) | ||
| 698 | #define OMAP3430_AUTO_GPT6_SHIFT 7 | ||
| 699 | #define OMAP3430_AUTO_GPT5_MASK (1 << 6) | ||
| 700 | #define OMAP3430_AUTO_GPT5_SHIFT 6 | ||
| 701 | #define OMAP3430_AUTO_GPT4_MASK (1 << 5) | ||
| 702 | #define OMAP3430_AUTO_GPT4_SHIFT 5 | ||
| 703 | #define OMAP3430_AUTO_GPT3_MASK (1 << 4) | ||
| 704 | #define OMAP3430_AUTO_GPT3_SHIFT 4 | ||
| 705 | #define OMAP3430_AUTO_GPT2_MASK (1 << 3) | ||
| 706 | #define OMAP3430_AUTO_GPT2_SHIFT 3 | ||
| 707 | #define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) | ||
| 708 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 | ||
| 709 | #define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) | ||
| 710 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 | ||
| 711 | #define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) | ||
| 712 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 | ||
| 713 | |||
| 714 | /* CM_CLKSEL_PER */ | ||
| 715 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) | 178 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) |
| 716 | #define OMAP3430_CLKSEL_GPT9_SHIFT 7 | ||
| 717 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) | 179 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) |
| 718 | #define OMAP3430_CLKSEL_GPT8_SHIFT 6 | ||
| 719 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) | 180 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) |
| 720 | #define OMAP3430_CLKSEL_GPT7_SHIFT 5 | ||
| 721 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) | 181 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) |
| 722 | #define OMAP3430_CLKSEL_GPT6_SHIFT 4 | ||
| 723 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) | 182 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) |
| 724 | #define OMAP3430_CLKSEL_GPT5_SHIFT 3 | ||
| 725 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) | 183 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) |
| 726 | #define OMAP3430_CLKSEL_GPT4_SHIFT 2 | ||
| 727 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) | 184 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) |
| 728 | #define OMAP3430_CLKSEL_GPT3_SHIFT 1 | ||
| 729 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) | 185 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) |
| 730 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | ||
| 731 | |||
| 732 | /* CM_SLEEPDEP_PER specific bits */ | ||
| 733 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) | ||
| 734 | |||
| 735 | /* CM_CLKSTCTRL_PER */ | ||
| 736 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | ||
| 737 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | 186 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) |
| 738 | |||
| 739 | /* CM_CLKSTST_PER */ | ||
| 740 | #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 | ||
| 741 | #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) | ||
| 742 | |||
| 743 | /* CM_CLKSEL1_EMU */ | ||
| 744 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 187 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
| 745 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | ||
| 746 | #define OMAP3430_DIV_DPLL4_WIDTH 5 | ||
| 747 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) | ||
| 748 | #define OMAP3630_DIV_DPLL4_WIDTH 6 | 188 | #define OMAP3630_DIV_DPLL4_WIDTH 6 |
| 749 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | 189 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
| 750 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | ||
| 751 | #define OMAP3430_DIV_DPLL3_WIDTH 5 | 190 | #define OMAP3430_DIV_DPLL3_WIDTH 5 |
| 752 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | 191 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 |
| 753 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | ||
| 754 | #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 | 192 | #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 |
| 755 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | 193 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 |
| 756 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | ||
| 757 | #define OMAP3430_CLKSEL_PCLK_WIDTH 3 | 194 | #define OMAP3430_CLKSEL_PCLK_WIDTH 3 |
| 758 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | 195 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 |
| 759 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | ||
| 760 | #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 | 196 | #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 |
| 761 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | 197 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 |
| 762 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | ||
| 763 | #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 | 198 | #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 |
| 764 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | 199 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 |
| 765 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | ||
| 766 | #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 | 200 | #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 |
| 767 | #define OMAP3430_MUX_CTRL_SHIFT 0 | ||
| 768 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | 201 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) |
| 769 | #define OMAP3430_MUX_CTRL_WIDTH 2 | ||
| 770 | |||
| 771 | /* CM_CLKSTCTRL_EMU */ | ||
| 772 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | ||
| 773 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | 202 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) |
| 774 | |||
| 775 | /* CM_CLKSTST_EMU */ | ||
| 776 | #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 | ||
| 777 | #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) | ||
| 778 | |||
| 779 | /* CM_CLKSEL2_EMU specific bits */ | ||
| 780 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | ||
| 781 | #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
| 782 | #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 | ||
| 783 | #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
| 784 | |||
| 785 | /* CM_CLKSEL3_EMU specific bits */ | ||
| 786 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 | ||
| 787 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
| 788 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 | ||
| 789 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
| 790 | |||
| 791 | /* CM_POLCTRL */ | ||
| 792 | #define OMAP3430_CLKOUT2_POL_MASK (1 << 0) | ||
| 793 | |||
| 794 | /* CM_IDLEST_NEON */ | ||
| 795 | #define OMAP3430_ST_NEON_MASK (1 << 0) | ||
| 796 | |||
| 797 | /* CM_CLKSTCTRL_NEON */ | ||
| 798 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | ||
| 799 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) | 203 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) |
| 800 | |||
| 801 | /* CM_FCLKEN_USBHOST */ | ||
| 802 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 | 204 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 |
| 803 | #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) | ||
| 804 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 | 205 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 |
| 805 | #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) | ||
| 806 | |||
| 807 | /* CM_ICLKEN_USBHOST */ | ||
| 808 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 | 206 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 |
| 809 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | ||
| 810 | |||
| 811 | /* CM_IDLEST_USBHOST */ | ||
| 812 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 | 207 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 |
| 813 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | ||
| 814 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | 208 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 |
| 815 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | ||
| 816 | |||
| 817 | /* CM_AUTOIDLE_USBHOST */ | ||
| 818 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
| 819 | #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) | ||
| 820 | |||
| 821 | /* CM_SLEEPDEP_USBHOST */ | ||
| 822 | #define OMAP3430ES2_EN_MPU_SHIFT 1 | ||
| 823 | #define OMAP3430ES2_EN_MPU_MASK (1 << 1) | ||
| 824 | #define OMAP3430ES2_EN_IVA2_SHIFT 2 | ||
| 825 | #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) | ||
| 826 | |||
| 827 | /* CM_CLKSTCTRL_USBHOST */ | ||
| 828 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | ||
| 829 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | 209 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) |
| 830 | |||
| 831 | /* CM_CLKSTST_USBHOST */ | ||
| 832 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | ||
| 833 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | ||
| 834 | |||
| 835 | /* | ||
| 836 | * | ||
| 837 | */ | ||
| 838 | |||
| 839 | /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ | ||
| 840 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 | 210 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 |
| 841 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 | 211 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 |
| 842 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | 212 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 |
| 843 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | 213 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 |
| 844 | |||
| 845 | |||
| 846 | #endif | 214 | #endif |