diff options
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 222 |
1 files changed, 111 insertions, 111 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index a3a3ca07e383..fe82b79d5f3b 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -21,15 +21,15 @@ | |||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ |
| 22 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | 22 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) |
| 23 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | 23 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 |
| 24 | #define OMAP3430_EN_MSPRO (1 << 23) | 24 | #define OMAP3430_EN_MSPRO_MASK (1 << 23) |
| 25 | #define OMAP3430_EN_MSPRO_SHIFT 23 | 25 | #define OMAP3430_EN_MSPRO_SHIFT 23 |
| 26 | #define OMAP3430_EN_HDQ (1 << 22) | 26 | #define OMAP3430_EN_HDQ_MASK (1 << 22) |
| 27 | #define OMAP3430_EN_HDQ_SHIFT 22 | 27 | #define OMAP3430_EN_HDQ_SHIFT 22 |
| 28 | #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) | 28 | #define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) |
| 29 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 | 29 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 |
| 30 | #define OMAP3430ES1_EN_D2D (1 << 3) | 30 | #define OMAP3430ES1_EN_D2D_MASK (1 << 3) |
| 31 | #define OMAP3430ES1_EN_D2D_SHIFT 3 | 31 | #define OMAP3430ES1_EN_D2D_SHIFT 3 |
| 32 | #define OMAP3430_EN_SSI (1 << 0) | 32 | #define OMAP3430_EN_SSI_MASK (1 << 0) |
| 33 | #define OMAP3430_EN_SSI_SHIFT 0 | 33 | #define OMAP3430_EN_SSI_SHIFT 0 |
| 34 | 34 | ||
| 35 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | 35 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ |
| @@ -37,19 +37,19 @@ | |||
| 37 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | 37 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) |
| 38 | 38 | ||
| 39 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | 39 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ |
| 40 | #define OMAP3430_EN_WDT2 (1 << 5) | 40 | #define OMAP3430_EN_WDT2_MASK (1 << 5) |
| 41 | #define OMAP3430_EN_WDT2_SHIFT 5 | 41 | #define OMAP3430_EN_WDT2_SHIFT 5 |
| 42 | 42 | ||
| 43 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | 43 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ |
| 44 | #define OMAP3430_EN_CAM (1 << 0) | 44 | #define OMAP3430_EN_CAM_MASK (1 << 0) |
| 45 | #define OMAP3430_EN_CAM_SHIFT 0 | 45 | #define OMAP3430_EN_CAM_SHIFT 0 |
| 46 | 46 | ||
| 47 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | 47 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ |
| 48 | #define OMAP3430_EN_WDT3 (1 << 12) | 48 | #define OMAP3430_EN_WDT3_MASK (1 << 12) |
| 49 | #define OMAP3430_EN_WDT3_SHIFT 12 | 49 | #define OMAP3430_EN_WDT3_SHIFT 12 |
| 50 | 50 | ||
| 51 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | 51 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ |
| 52 | #define OMAP3430_OVERRIDE_ENABLE (1 << 19) | 52 | #define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) |
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | /* Bits specific to each register */ | 55 | /* Bits specific to each register */ |
| @@ -69,7 +69,7 @@ | |||
| 69 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | 69 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) |
| 70 | 70 | ||
| 71 | /* CM_IDLEST_IVA2 */ | 71 | /* CM_IDLEST_IVA2 */ |
| 72 | #define OMAP3430_ST_IVA2 (1 << 0) | 72 | #define OMAP3430_ST_IVA2_MASK (1 << 0) |
| 73 | 73 | ||
| 74 | /* CM_IDLEST_PLL_IVA2 */ | 74 | /* CM_IDLEST_PLL_IVA2 */ |
| 75 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 | 75 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 |
| @@ -114,7 +114,7 @@ | |||
| 114 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | 114 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) |
| 115 | 115 | ||
| 116 | /* CM_IDLEST_MPU */ | 116 | /* CM_IDLEST_MPU */ |
| 117 | #define OMAP3430_ST_MPU (1 << 0) | 117 | #define OMAP3430_ST_MPU_MASK (1 << 0) |
| 118 | 118 | ||
| 119 | /* CM_IDLEST_PLL_MPU */ | 119 | /* CM_IDLEST_PLL_MPU */ |
| 120 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 | 120 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
| @@ -145,50 +145,50 @@ | |||
| 145 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | 145 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) |
| 146 | 146 | ||
| 147 | /* CM_FCLKEN1_CORE specific bits */ | 147 | /* CM_FCLKEN1_CORE specific bits */ |
| 148 | #define OMAP3430_EN_MODEM (1 << 31) | 148 | #define OMAP3430_EN_MODEM_MASK (1 << 31) |
| 149 | #define OMAP3430_EN_MODEM_SHIFT 31 | 149 | #define OMAP3430_EN_MODEM_SHIFT 31 |
| 150 | 150 | ||
| 151 | /* CM_ICLKEN1_CORE specific bits */ | 151 | /* CM_ICLKEN1_CORE specific bits */ |
| 152 | #define OMAP3430_EN_ICR (1 << 29) | 152 | #define OMAP3430_EN_ICR_MASK (1 << 29) |
| 153 | #define OMAP3430_EN_ICR_SHIFT 29 | 153 | #define OMAP3430_EN_ICR_SHIFT 29 |
| 154 | #define OMAP3430_EN_AES2 (1 << 28) | 154 | #define OMAP3430_EN_AES2_MASK (1 << 28) |
| 155 | #define OMAP3430_EN_AES2_SHIFT 28 | 155 | #define OMAP3430_EN_AES2_SHIFT 28 |
| 156 | #define OMAP3430_EN_SHA12 (1 << 27) | 156 | #define OMAP3430_EN_SHA12_MASK (1 << 27) |
| 157 | #define OMAP3430_EN_SHA12_SHIFT 27 | 157 | #define OMAP3430_EN_SHA12_SHIFT 27 |
| 158 | #define OMAP3430_EN_DES2 (1 << 26) | 158 | #define OMAP3430_EN_DES2_MASK (1 << 26) |
| 159 | #define OMAP3430_EN_DES2_SHIFT 26 | 159 | #define OMAP3430_EN_DES2_SHIFT 26 |
| 160 | #define OMAP3430ES1_EN_FAC (1 << 8) | 160 | #define OMAP3430ES1_EN_FAC_MASK (1 << 8) |
| 161 | #define OMAP3430ES1_EN_FAC_SHIFT 8 | 161 | #define OMAP3430ES1_EN_FAC_SHIFT 8 |
| 162 | #define OMAP3430_EN_MAILBOXES (1 << 7) | 162 | #define OMAP3430_EN_MAILBOXES_MASK (1 << 7) |
| 163 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 | 163 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 |
| 164 | #define OMAP3430_EN_OMAPCTRL (1 << 6) | 164 | #define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) |
| 165 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 | 165 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 |
| 166 | #define OMAP3430_EN_SAD2D (1 << 3) | 166 | #define OMAP3430_EN_SAD2D_MASK (1 << 3) |
| 167 | #define OMAP3430_EN_SAD2D_SHIFT 3 | 167 | #define OMAP3430_EN_SAD2D_SHIFT 3 |
| 168 | #define OMAP3430_EN_SDRC (1 << 1) | 168 | #define OMAP3430_EN_SDRC_MASK (1 << 1) |
| 169 | #define OMAP3430_EN_SDRC_SHIFT 1 | 169 | #define OMAP3430_EN_SDRC_SHIFT 1 |
| 170 | 170 | ||
| 171 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | 171 | /* AM35XX specific CM_ICLKEN1_CORE bits */ |
| 172 | #define AM35XX_EN_IPSS_MASK (1 << 4) | 172 | #define AM35XX_EN_IPSS_MASK (1 << 4) |
| 173 | #define AM35XX_EN_IPSS_SHIFT 4 | 173 | #define AM35XX_EN_IPSS_SHIFT 4 |
| 174 | #define AM35XX_EN_UART4_MASK (1 << 23) | 174 | #define AM35XX_EN_UART4_MASK (1 << 23) |
| 175 | #define AM35XX_EN_UART4_SHIFT 23 | 175 | #define AM35XX_EN_UART4_SHIFT 23 |
| 176 | 176 | ||
| 177 | /* CM_ICLKEN2_CORE */ | 177 | /* CM_ICLKEN2_CORE */ |
| 178 | #define OMAP3430_EN_PKA (1 << 4) | 178 | #define OMAP3430_EN_PKA_MASK (1 << 4) |
| 179 | #define OMAP3430_EN_PKA_SHIFT 4 | 179 | #define OMAP3430_EN_PKA_SHIFT 4 |
| 180 | #define OMAP3430_EN_AES1 (1 << 3) | 180 | #define OMAP3430_EN_AES1_MASK (1 << 3) |
| 181 | #define OMAP3430_EN_AES1_SHIFT 3 | 181 | #define OMAP3430_EN_AES1_SHIFT 3 |
| 182 | #define OMAP3430_EN_RNG (1 << 2) | 182 | #define OMAP3430_EN_RNG_MASK (1 << 2) |
| 183 | #define OMAP3430_EN_RNG_SHIFT 2 | 183 | #define OMAP3430_EN_RNG_SHIFT 2 |
| 184 | #define OMAP3430_EN_SHA11 (1 << 1) | 184 | #define OMAP3430_EN_SHA11_MASK (1 << 1) |
| 185 | #define OMAP3430_EN_SHA11_SHIFT 1 | 185 | #define OMAP3430_EN_SHA11_SHIFT 1 |
| 186 | #define OMAP3430_EN_DES1 (1 << 0) | 186 | #define OMAP3430_EN_DES1_MASK (1 << 0) |
| 187 | #define OMAP3430_EN_DES1_SHIFT 0 | 187 | #define OMAP3430_EN_DES1_SHIFT 0 |
| 188 | 188 | ||
| 189 | /* CM_ICLKEN3_CORE */ | 189 | /* CM_ICLKEN3_CORE */ |
| 190 | #define OMAP3430_EN_MAD2D_SHIFT 3 | 190 | #define OMAP3430_EN_MAD2D_SHIFT 3 |
| 191 | #define OMAP3430_EN_MAD2D (1 << 3) | 191 | #define OMAP3430_EN_MAD2D_MASK (1 << 3) |
| 192 | 192 | ||
| 193 | /* CM_FCLKEN3_CORE specific bits */ | 193 | /* CM_FCLKEN3_CORE specific bits */ |
| 194 | #define OMAP3430ES2_EN_TS_SHIFT 1 | 194 | #define OMAP3430ES2_EN_TS_SHIFT 1 |
| @@ -249,79 +249,79 @@ | |||
| 249 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | 249 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) |
| 250 | 250 | ||
| 251 | /* CM_AUTOIDLE1_CORE */ | 251 | /* CM_AUTOIDLE1_CORE */ |
| 252 | #define OMAP3430_AUTO_MODEM (1 << 31) | 252 | #define OMAP3430_AUTO_MODEM_MASK (1 << 31) |
| 253 | #define OMAP3430_AUTO_MODEM_SHIFT 31 | 253 | #define OMAP3430_AUTO_MODEM_SHIFT 31 |
| 254 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) | 254 | #define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) |
| 255 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | 255 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 |
| 256 | #define OMAP3430ES2_AUTO_ICR (1 << 29) | 256 | #define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) |
| 257 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 | 257 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 |
| 258 | #define OMAP3430_AUTO_AES2 (1 << 28) | 258 | #define OMAP3430_AUTO_AES2_MASK (1 << 28) |
| 259 | #define OMAP3430_AUTO_AES2_SHIFT 28 | 259 | #define OMAP3430_AUTO_AES2_SHIFT 28 |
| 260 | #define OMAP3430_AUTO_SHA12 (1 << 27) | 260 | #define OMAP3430_AUTO_SHA12_MASK (1 << 27) |
| 261 | #define OMAP3430_AUTO_SHA12_SHIFT 27 | 261 | #define OMAP3430_AUTO_SHA12_SHIFT 27 |
| 262 | #define OMAP3430_AUTO_DES2 (1 << 26) | 262 | #define OMAP3430_AUTO_DES2_MASK (1 << 26) |
| 263 | #define OMAP3430_AUTO_DES2_SHIFT 26 | 263 | #define OMAP3430_AUTO_DES2_SHIFT 26 |
| 264 | #define OMAP3430_AUTO_MMC2 (1 << 25) | 264 | #define OMAP3430_AUTO_MMC2_MASK (1 << 25) |
| 265 | #define OMAP3430_AUTO_MMC2_SHIFT 25 | 265 | #define OMAP3430_AUTO_MMC2_SHIFT 25 |
| 266 | #define OMAP3430_AUTO_MMC1 (1 << 24) | 266 | #define OMAP3430_AUTO_MMC1_MASK (1 << 24) |
| 267 | #define OMAP3430_AUTO_MMC1_SHIFT 24 | 267 | #define OMAP3430_AUTO_MMC1_SHIFT 24 |
| 268 | #define OMAP3430_AUTO_MSPRO (1 << 23) | 268 | #define OMAP3430_AUTO_MSPRO_MASK (1 << 23) |
| 269 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 | 269 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 |
| 270 | #define OMAP3430_AUTO_HDQ (1 << 22) | 270 | #define OMAP3430_AUTO_HDQ_MASK (1 << 22) |
| 271 | #define OMAP3430_AUTO_HDQ_SHIFT 22 | 271 | #define OMAP3430_AUTO_HDQ_SHIFT 22 |
| 272 | #define OMAP3430_AUTO_MCSPI4 (1 << 21) | 272 | #define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) |
| 273 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 | 273 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 |
| 274 | #define OMAP3430_AUTO_MCSPI3 (1 << 20) | 274 | #define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) |
| 275 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 | 275 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 |
| 276 | #define OMAP3430_AUTO_MCSPI2 (1 << 19) | 276 | #define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) |
| 277 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 | 277 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 |
| 278 | #define OMAP3430_AUTO_MCSPI1 (1 << 18) | 278 | #define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) |
| 279 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 | 279 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 |
| 280 | #define OMAP3430_AUTO_I2C3 (1 << 17) | 280 | #define OMAP3430_AUTO_I2C3_MASK (1 << 17) |
| 281 | #define OMAP3430_AUTO_I2C3_SHIFT 17 | 281 | #define OMAP3430_AUTO_I2C3_SHIFT 17 |
| 282 | #define OMAP3430_AUTO_I2C2 (1 << 16) | 282 | #define OMAP3430_AUTO_I2C2_MASK (1 << 16) |
| 283 | #define OMAP3430_AUTO_I2C2_SHIFT 16 | 283 | #define OMAP3430_AUTO_I2C2_SHIFT 16 |
| 284 | #define OMAP3430_AUTO_I2C1 (1 << 15) | 284 | #define OMAP3430_AUTO_I2C1_MASK (1 << 15) |
| 285 | #define OMAP3430_AUTO_I2C1_SHIFT 15 | 285 | #define OMAP3430_AUTO_I2C1_SHIFT 15 |
| 286 | #define OMAP3430_AUTO_UART2 (1 << 14) | 286 | #define OMAP3430_AUTO_UART2_MASK (1 << 14) |
| 287 | #define OMAP3430_AUTO_UART2_SHIFT 14 | 287 | #define OMAP3430_AUTO_UART2_SHIFT 14 |
| 288 | #define OMAP3430_AUTO_UART1 (1 << 13) | 288 | #define OMAP3430_AUTO_UART1_MASK (1 << 13) |
| 289 | #define OMAP3430_AUTO_UART1_SHIFT 13 | 289 | #define OMAP3430_AUTO_UART1_SHIFT 13 |
| 290 | #define OMAP3430_AUTO_GPT11 (1 << 12) | 290 | #define OMAP3430_AUTO_GPT11_MASK (1 << 12) |
| 291 | #define OMAP3430_AUTO_GPT11_SHIFT 12 | 291 | #define OMAP3430_AUTO_GPT11_SHIFT 12 |
| 292 | #define OMAP3430_AUTO_GPT10 (1 << 11) | 292 | #define OMAP3430_AUTO_GPT10_MASK (1 << 11) |
| 293 | #define OMAP3430_AUTO_GPT10_SHIFT 11 | 293 | #define OMAP3430_AUTO_GPT10_SHIFT 11 |
| 294 | #define OMAP3430_AUTO_MCBSP5 (1 << 10) | 294 | #define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) |
| 295 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 | 295 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 |
| 296 | #define OMAP3430_AUTO_MCBSP1 (1 << 9) | 296 | #define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) |
| 297 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 | 297 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 |
| 298 | #define OMAP3430ES1_AUTO_FAC (1 << 8) | 298 | #define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) |
| 299 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 | 299 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 |
| 300 | #define OMAP3430_AUTO_MAILBOXES (1 << 7) | 300 | #define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) |
| 301 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 | 301 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 |
| 302 | #define OMAP3430_AUTO_OMAPCTRL (1 << 6) | 302 | #define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) |
| 303 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 | 303 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 |
| 304 | #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) | 304 | #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) |
| 305 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 | 305 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 |
| 306 | #define OMAP3430_AUTO_HSOTGUSB (1 << 4) | 306 | #define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) |
| 307 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 | 307 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 |
| 308 | #define OMAP3430ES1_AUTO_D2D (1 << 3) | 308 | #define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) |
| 309 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 | 309 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 |
| 310 | #define OMAP3430_AUTO_SAD2D (1 << 3) | 310 | #define OMAP3430_AUTO_SAD2D_MASK (1 << 3) |
| 311 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 | 311 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 |
| 312 | #define OMAP3430_AUTO_SSI (1 << 0) | 312 | #define OMAP3430_AUTO_SSI_MASK (1 << 0) |
| 313 | #define OMAP3430_AUTO_SSI_SHIFT 0 | 313 | #define OMAP3430_AUTO_SSI_SHIFT 0 |
| 314 | 314 | ||
| 315 | /* CM_AUTOIDLE2_CORE */ | 315 | /* CM_AUTOIDLE2_CORE */ |
| 316 | #define OMAP3430_AUTO_PKA (1 << 4) | 316 | #define OMAP3430_AUTO_PKA_MASK (1 << 4) |
| 317 | #define OMAP3430_AUTO_PKA_SHIFT 4 | 317 | #define OMAP3430_AUTO_PKA_SHIFT 4 |
| 318 | #define OMAP3430_AUTO_AES1 (1 << 3) | 318 | #define OMAP3430_AUTO_AES1_MASK (1 << 3) |
| 319 | #define OMAP3430_AUTO_AES1_SHIFT 3 | 319 | #define OMAP3430_AUTO_AES1_SHIFT 3 |
| 320 | #define OMAP3430_AUTO_RNG (1 << 2) | 320 | #define OMAP3430_AUTO_RNG_MASK (1 << 2) |
| 321 | #define OMAP3430_AUTO_RNG_SHIFT 2 | 321 | #define OMAP3430_AUTO_RNG_SHIFT 2 |
| 322 | #define OMAP3430_AUTO_SHA11 (1 << 1) | 322 | #define OMAP3430_AUTO_SHA11_MASK (1 << 1) |
| 323 | #define OMAP3430_AUTO_SHA11_SHIFT 1 | 323 | #define OMAP3430_AUTO_SHA11_SHIFT 1 |
| 324 | #define OMAP3430_AUTO_DES1 (1 << 0) | 324 | #define OMAP3430_AUTO_DES1_MASK (1 << 0) |
| 325 | #define OMAP3430_AUTO_DES1_SHIFT 0 | 325 | #define OMAP3430_AUTO_DES1_SHIFT 0 |
| 326 | 326 | ||
| 327 | /* CM_AUTOIDLE3_CORE */ | 327 | /* CM_AUTOIDLE3_CORE */ |
| @@ -331,7 +331,7 @@ | |||
| 331 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | 331 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 |
| 332 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | 332 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) |
| 333 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 | 333 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 |
| 334 | #define OMAP3430_AUTO_MAD2D (1 << 3) | 334 | #define OMAP3430_AUTO_MAD2D_MASK (1 << 3) |
| 335 | 335 | ||
| 336 | /* CM_CLKSEL_CORE */ | 336 | /* CM_CLKSEL_CORE */ |
| 337 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | 337 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 |
| @@ -366,9 +366,9 @@ | |||
| 366 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | 366 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) |
| 367 | 367 | ||
| 368 | /* CM_FCLKEN_GFX */ | 368 | /* CM_FCLKEN_GFX */ |
| 369 | #define OMAP3430ES1_EN_3D (1 << 2) | 369 | #define OMAP3430ES1_EN_3D_MASK (1 << 2) |
| 370 | #define OMAP3430ES1_EN_3D_SHIFT 2 | 370 | #define OMAP3430ES1_EN_3D_SHIFT 2 |
| 371 | #define OMAP3430ES1_EN_2D (1 << 1) | 371 | #define OMAP3430ES1_EN_2D_MASK (1 << 1) |
| 372 | #define OMAP3430ES1_EN_2D_SHIFT 1 | 372 | #define OMAP3430ES1_EN_2D_SHIFT 1 |
| 373 | 373 | ||
| 374 | /* CM_ICLKEN_GFX specific bits */ | 374 | /* CM_ICLKEN_GFX specific bits */ |
| @@ -416,9 +416,9 @@ | |||
| 416 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) | 416 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) |
| 417 | 417 | ||
| 418 | /* CM_ICLKEN_WKUP specific bits */ | 418 | /* CM_ICLKEN_WKUP specific bits */ |
| 419 | #define OMAP3430_EN_WDT1 (1 << 4) | 419 | #define OMAP3430_EN_WDT1_MASK (1 << 4) |
| 420 | #define OMAP3430_EN_WDT1_SHIFT 4 | 420 | #define OMAP3430_EN_WDT1_SHIFT 4 |
| 421 | #define OMAP3430_EN_32KSYNC (1 << 2) | 421 | #define OMAP3430_EN_32KSYNC_MASK (1 << 2) |
| 422 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | 422 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
| 423 | 423 | ||
| 424 | /* CM_IDLEST_WKUP specific bits */ | 424 | /* CM_IDLEST_WKUP specific bits */ |
| @@ -432,19 +432,19 @@ | |||
| 432 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | 432 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) |
| 433 | 433 | ||
| 434 | /* CM_AUTOIDLE_WKUP */ | 434 | /* CM_AUTOIDLE_WKUP */ |
| 435 | #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) | 435 | #define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) |
| 436 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | 436 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 |
| 437 | #define OMAP3430_AUTO_WDT2 (1 << 5) | 437 | #define OMAP3430_AUTO_WDT2_MASK (1 << 5) |
| 438 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | 438 | #define OMAP3430_AUTO_WDT2_SHIFT 5 |
| 439 | #define OMAP3430_AUTO_WDT1 (1 << 4) | 439 | #define OMAP3430_AUTO_WDT1_MASK (1 << 4) |
| 440 | #define OMAP3430_AUTO_WDT1_SHIFT 4 | 440 | #define OMAP3430_AUTO_WDT1_SHIFT 4 |
| 441 | #define OMAP3430_AUTO_GPIO1 (1 << 3) | 441 | #define OMAP3430_AUTO_GPIO1_MASK (1 << 3) |
| 442 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 | 442 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 |
| 443 | #define OMAP3430_AUTO_32KSYNC (1 << 2) | 443 | #define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) |
| 444 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 | 444 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 |
| 445 | #define OMAP3430_AUTO_GPT12 (1 << 1) | 445 | #define OMAP3430_AUTO_GPT12_MASK (1 << 1) |
| 446 | #define OMAP3430_AUTO_GPT12_SHIFT 1 | 446 | #define OMAP3430_AUTO_GPT12_SHIFT 1 |
| 447 | #define OMAP3430_AUTO_GPT1 (1 << 0) | 447 | #define OMAP3430_AUTO_GPT1_MASK (1 << 0) |
| 448 | #define OMAP3430_AUTO_GPT1_SHIFT 0 | 448 | #define OMAP3430_AUTO_GPT1_SHIFT 0 |
| 449 | 449 | ||
| 450 | /* CM_CLKSEL_WKUP */ | 450 | /* CM_CLKSEL_WKUP */ |
| @@ -479,7 +479,7 @@ | |||
| 479 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | 479 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) |
| 480 | 480 | ||
| 481 | /* CM_CLKEN2_PLL */ | 481 | /* CM_CLKEN2_PLL */ |
| 482 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 | 482 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 |
| 483 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) | 483 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) |
| 484 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | 484 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 |
| 485 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | 485 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) |
| @@ -488,10 +488,10 @@ | |||
| 488 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | 488 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) |
| 489 | 489 | ||
| 490 | /* CM_IDLEST_CKGEN */ | 490 | /* CM_IDLEST_CKGEN */ |
| 491 | #define OMAP3430_ST_54M_CLK (1 << 5) | 491 | #define OMAP3430_ST_54M_CLK_MASK (1 << 5) |
| 492 | #define OMAP3430_ST_12M_CLK (1 << 4) | 492 | #define OMAP3430_ST_12M_CLK_MASK (1 << 4) |
| 493 | #define OMAP3430_ST_48M_CLK (1 << 3) | 493 | #define OMAP3430_ST_48M_CLK_MASK (1 << 3) |
| 494 | #define OMAP3430_ST_96M_CLK (1 << 2) | 494 | #define OMAP3430_ST_96M_CLK_MASK (1 << 2) |
| 495 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 | 495 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 |
| 496 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) | 496 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) |
| 497 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | 497 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 |
| @@ -558,22 +558,22 @@ | |||
| 558 | 558 | ||
| 559 | /* CM_CLKOUT_CTRL */ | 559 | /* CM_CLKOUT_CTRL */ |
| 560 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | 560 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 |
| 561 | #define OMAP3430_CLKOUT2_EN (1 << 7) | 561 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) |
| 562 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 | 562 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 |
| 563 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | 563 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) |
| 564 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | 564 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 |
| 565 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | 565 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) |
| 566 | 566 | ||
| 567 | /* CM_FCLKEN_DSS */ | 567 | /* CM_FCLKEN_DSS */ |
| 568 | #define OMAP3430_EN_TV (1 << 2) | 568 | #define OMAP3430_EN_TV_MASK (1 << 2) |
| 569 | #define OMAP3430_EN_TV_SHIFT 2 | 569 | #define OMAP3430_EN_TV_SHIFT 2 |
| 570 | #define OMAP3430_EN_DSS2 (1 << 1) | 570 | #define OMAP3430_EN_DSS2_MASK (1 << 1) |
| 571 | #define OMAP3430_EN_DSS2_SHIFT 1 | 571 | #define OMAP3430_EN_DSS2_SHIFT 1 |
| 572 | #define OMAP3430_EN_DSS1 (1 << 0) | 572 | #define OMAP3430_EN_DSS1_MASK (1 << 0) |
| 573 | #define OMAP3430_EN_DSS1_SHIFT 0 | 573 | #define OMAP3430_EN_DSS1_SHIFT 0 |
| 574 | 574 | ||
| 575 | /* CM_ICLKEN_DSS */ | 575 | /* CM_ICLKEN_DSS */ |
| 576 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) | 576 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) |
| 577 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | 577 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
| 578 | 578 | ||
| 579 | /* CM_IDLEST_DSS */ | 579 | /* CM_IDLEST_DSS */ |
| @@ -585,7 +585,7 @@ | |||
| 585 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | 585 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) |
| 586 | 586 | ||
| 587 | /* CM_AUTOIDLE_DSS */ | 587 | /* CM_AUTOIDLE_DSS */ |
| 588 | #define OMAP3430_AUTO_DSS (1 << 0) | 588 | #define OMAP3430_AUTO_DSS_MASK (1 << 0) |
| 589 | #define OMAP3430_AUTO_DSS_SHIFT 0 | 589 | #define OMAP3430_AUTO_DSS_SHIFT 0 |
| 590 | 590 | ||
| 591 | /* CM_CLKSEL_DSS */ | 591 | /* CM_CLKSEL_DSS */ |
| @@ -607,16 +607,16 @@ | |||
| 607 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | 607 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) |
| 608 | 608 | ||
| 609 | /* CM_FCLKEN_CAM specific bits */ | 609 | /* CM_FCLKEN_CAM specific bits */ |
| 610 | #define OMAP3430_EN_CSI2 (1 << 1) | 610 | #define OMAP3430_EN_CSI2_MASK (1 << 1) |
| 611 | #define OMAP3430_EN_CSI2_SHIFT 1 | 611 | #define OMAP3430_EN_CSI2_SHIFT 1 |
| 612 | 612 | ||
| 613 | /* CM_ICLKEN_CAM specific bits */ | 613 | /* CM_ICLKEN_CAM specific bits */ |
| 614 | 614 | ||
| 615 | /* CM_IDLEST_CAM */ | 615 | /* CM_IDLEST_CAM */ |
| 616 | #define OMAP3430_ST_CAM (1 << 0) | 616 | #define OMAP3430_ST_CAM_MASK (1 << 0) |
| 617 | 617 | ||
| 618 | /* CM_AUTOIDLE_CAM */ | 618 | /* CM_AUTOIDLE_CAM */ |
| 619 | #define OMAP3430_AUTO_CAM (1 << 0) | 619 | #define OMAP3430_AUTO_CAM_MASK (1 << 0) |
| 620 | #define OMAP3430_AUTO_CAM_SHIFT 0 | 620 | #define OMAP3430_AUTO_CAM_SHIFT 0 |
| 621 | 621 | ||
| 622 | /* CM_CLKSEL_CAM */ | 622 | /* CM_CLKSEL_CAM */ |
| @@ -649,41 +649,41 @@ | |||
| 649 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | 649 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) |
| 650 | 650 | ||
| 651 | /* CM_AUTOIDLE_PER */ | 651 | /* CM_AUTOIDLE_PER */ |
| 652 | #define OMAP3430_AUTO_GPIO6 (1 << 17) | 652 | #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) |
| 653 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 | 653 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 |
| 654 | #define OMAP3430_AUTO_GPIO5 (1 << 16) | 654 | #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) |
| 655 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 | 655 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 |
| 656 | #define OMAP3430_AUTO_GPIO4 (1 << 15) | 656 | #define OMAP3430_AUTO_GPIO4_MASK (1 << 15) |
| 657 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 | 657 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 |
| 658 | #define OMAP3430_AUTO_GPIO3 (1 << 14) | 658 | #define OMAP3430_AUTO_GPIO3_MASK (1 << 14) |
| 659 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 | 659 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 |
| 660 | #define OMAP3430_AUTO_GPIO2 (1 << 13) | 660 | #define OMAP3430_AUTO_GPIO2_MASK (1 << 13) |
| 661 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 | 661 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 |
| 662 | #define OMAP3430_AUTO_WDT3 (1 << 12) | 662 | #define OMAP3430_AUTO_WDT3_MASK (1 << 12) |
| 663 | #define OMAP3430_AUTO_WDT3_SHIFT 12 | 663 | #define OMAP3430_AUTO_WDT3_SHIFT 12 |
| 664 | #define OMAP3430_AUTO_UART3 (1 << 11) | 664 | #define OMAP3430_AUTO_UART3_MASK (1 << 11) |
| 665 | #define OMAP3430_AUTO_UART3_SHIFT 11 | 665 | #define OMAP3430_AUTO_UART3_SHIFT 11 |
| 666 | #define OMAP3430_AUTO_GPT9 (1 << 10) | 666 | #define OMAP3430_AUTO_GPT9_MASK (1 << 10) |
| 667 | #define OMAP3430_AUTO_GPT9_SHIFT 10 | 667 | #define OMAP3430_AUTO_GPT9_SHIFT 10 |
| 668 | #define OMAP3430_AUTO_GPT8 (1 << 9) | 668 | #define OMAP3430_AUTO_GPT8_MASK (1 << 9) |
| 669 | #define OMAP3430_AUTO_GPT8_SHIFT 9 | 669 | #define OMAP3430_AUTO_GPT8_SHIFT 9 |
| 670 | #define OMAP3430_AUTO_GPT7 (1 << 8) | 670 | #define OMAP3430_AUTO_GPT7_MASK (1 << 8) |
| 671 | #define OMAP3430_AUTO_GPT7_SHIFT 8 | 671 | #define OMAP3430_AUTO_GPT7_SHIFT 8 |
| 672 | #define OMAP3430_AUTO_GPT6 (1 << 7) | 672 | #define OMAP3430_AUTO_GPT6_MASK (1 << 7) |
| 673 | #define OMAP3430_AUTO_GPT6_SHIFT 7 | 673 | #define OMAP3430_AUTO_GPT6_SHIFT 7 |
| 674 | #define OMAP3430_AUTO_GPT5 (1 << 6) | 674 | #define OMAP3430_AUTO_GPT5_MASK (1 << 6) |
| 675 | #define OMAP3430_AUTO_GPT5_SHIFT 6 | 675 | #define OMAP3430_AUTO_GPT5_SHIFT 6 |
| 676 | #define OMAP3430_AUTO_GPT4 (1 << 5) | 676 | #define OMAP3430_AUTO_GPT4_MASK (1 << 5) |
| 677 | #define OMAP3430_AUTO_GPT4_SHIFT 5 | 677 | #define OMAP3430_AUTO_GPT4_SHIFT 5 |
| 678 | #define OMAP3430_AUTO_GPT3 (1 << 4) | 678 | #define OMAP3430_AUTO_GPT3_MASK (1 << 4) |
| 679 | #define OMAP3430_AUTO_GPT3_SHIFT 4 | 679 | #define OMAP3430_AUTO_GPT3_SHIFT 4 |
| 680 | #define OMAP3430_AUTO_GPT2 (1 << 3) | 680 | #define OMAP3430_AUTO_GPT2_MASK (1 << 3) |
| 681 | #define OMAP3430_AUTO_GPT2_SHIFT 3 | 681 | #define OMAP3430_AUTO_GPT2_SHIFT 3 |
| 682 | #define OMAP3430_AUTO_MCBSP4 (1 << 2) | 682 | #define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) |
| 683 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 | 683 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 |
| 684 | #define OMAP3430_AUTO_MCBSP3 (1 << 1) | 684 | #define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) |
| 685 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 | 685 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 |
| 686 | #define OMAP3430_AUTO_MCBSP2 (1 << 0) | 686 | #define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) |
| 687 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 | 687 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 |
| 688 | 688 | ||
| 689 | /* CM_CLKSEL_PER */ | 689 | /* CM_CLKSEL_PER */ |
| @@ -705,7 +705,7 @@ | |||
| 705 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | 705 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 |
| 706 | 706 | ||
| 707 | /* CM_SLEEPDEP_PER specific bits */ | 707 | /* CM_SLEEPDEP_PER specific bits */ |
| 708 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) | 708 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) |
| 709 | 709 | ||
| 710 | /* CM_CLKSTCTRL_PER */ | 710 | /* CM_CLKSTCTRL_PER */ |
| 711 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | 711 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 |
| @@ -755,10 +755,10 @@ | |||
| 755 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | 755 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) |
| 756 | 756 | ||
| 757 | /* CM_POLCTRL */ | 757 | /* CM_POLCTRL */ |
| 758 | #define OMAP3430_CLKOUT2_POL (1 << 0) | 758 | #define OMAP3430_CLKOUT2_POL_MASK (1 << 0) |
| 759 | 759 | ||
| 760 | /* CM_IDLEST_NEON */ | 760 | /* CM_IDLEST_NEON */ |
| 761 | #define OMAP3430_ST_NEON (1 << 0) | 761 | #define OMAP3430_ST_NEON_MASK (1 << 0) |
| 762 | 762 | ||
| 763 | /* CM_CLKSTCTRL_NEON */ | 763 | /* CM_CLKSTCTRL_NEON */ |
| 764 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | 764 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 |