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Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c215
1 files changed, 172 insertions, 43 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 25473a1db3e7..2af0e3f00ce1 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -2808,19 +2808,39 @@ static struct clk trace_clk_div_ck = {
2808 2808
2809/* SCRM aux clk nodes */ 2809/* SCRM aux clk nodes */
2810 2810
2811static const struct clksel auxclk_sel[] = { 2811static const struct clksel auxclk_src_sel[] = {
2812 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 2812 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2813 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, 2813 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2814 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, 2814 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2815 { .parent = NULL }, 2815 { .parent = NULL },
2816}; 2816};
2817 2817
2818static struct clk auxclk0_ck = { 2818static const struct clksel_rate div16_1to16_rates[] = {
2819 .name = "auxclk0_ck", 2819 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2820 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2821 { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2822 { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2823 { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2824 { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2825 { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2826 { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2827 { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2828 { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2829 { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2830 { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2831 { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2832 { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2833 { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2834 { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2835 { .div = 0 },
2836};
2837
2838static struct clk auxclk0_src_ck = {
2839 .name = "auxclk0_src_ck",
2820 .parent = &sys_clkin_ck, 2840 .parent = &sys_clkin_ck,
2821 .init = &omap2_init_clksel_parent, 2841 .init = &omap2_init_clksel_parent,
2822 .ops = &clkops_omap2_dflt, 2842 .ops = &clkops_omap2_dflt,
2823 .clksel = auxclk_sel, 2843 .clksel = auxclk_src_sel,
2824 .clksel_reg = OMAP4_SCRM_AUXCLK0, 2844 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2825 .clksel_mask = OMAP4_SRCSELECT_MASK, 2845 .clksel_mask = OMAP4_SRCSELECT_MASK,
2826 .recalc = &omap2_clksel_recalc, 2846 .recalc = &omap2_clksel_recalc,
@@ -2828,12 +2848,29 @@ static struct clk auxclk0_ck = {
2828 .enable_bit = OMAP4_ENABLE_SHIFT, 2848 .enable_bit = OMAP4_ENABLE_SHIFT,
2829}; 2849};
2830 2850
2831static struct clk auxclk1_ck = { 2851static const struct clksel auxclk0_sel[] = {
2832 .name = "auxclk1_ck", 2852 { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2853 { .parent = NULL },
2854};
2855
2856static struct clk auxclk0_ck = {
2857 .name = "auxclk0_ck",
2858 .parent = &auxclk0_src_ck,
2859 .clksel = auxclk0_sel,
2860 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2861 .clksel_mask = OMAP4_CLKDIV_MASK,
2862 .ops = &clkops_null,
2863 .recalc = &omap2_clksel_recalc,
2864 .round_rate = &omap2_clksel_round_rate,
2865 .set_rate = &omap2_clksel_set_rate,
2866};
2867
2868static struct clk auxclk1_src_ck = {
2869 .name = "auxclk1_src_ck",
2833 .parent = &sys_clkin_ck, 2870 .parent = &sys_clkin_ck,
2834 .init = &omap2_init_clksel_parent, 2871 .init = &omap2_init_clksel_parent,
2835 .ops = &clkops_omap2_dflt, 2872 .ops = &clkops_omap2_dflt,
2836 .clksel = auxclk_sel, 2873 .clksel = auxclk_src_sel,
2837 .clksel_reg = OMAP4_SCRM_AUXCLK1, 2874 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2838 .clksel_mask = OMAP4_SRCSELECT_MASK, 2875 .clksel_mask = OMAP4_SRCSELECT_MASK,
2839 .recalc = &omap2_clksel_recalc, 2876 .recalc = &omap2_clksel_recalc,
@@ -2841,12 +2878,29 @@ static struct clk auxclk1_ck = {
2841 .enable_bit = OMAP4_ENABLE_SHIFT, 2878 .enable_bit = OMAP4_ENABLE_SHIFT,
2842}; 2879};
2843 2880
2844static struct clk auxclk2_ck = { 2881static const struct clksel auxclk1_sel[] = {
2845 .name = "auxclk2_ck", 2882 { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2883 { .parent = NULL },
2884};
2885
2886static struct clk auxclk1_ck = {
2887 .name = "auxclk1_ck",
2888 .parent = &auxclk1_src_ck,
2889 .clksel = auxclk1_sel,
2890 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2891 .clksel_mask = OMAP4_CLKDIV_MASK,
2892 .ops = &clkops_null,
2893 .recalc = &omap2_clksel_recalc,
2894 .round_rate = &omap2_clksel_round_rate,
2895 .set_rate = &omap2_clksel_set_rate,
2896};
2897
2898static struct clk auxclk2_src_ck = {
2899 .name = "auxclk2_src_ck",
2846 .parent = &sys_clkin_ck, 2900 .parent = &sys_clkin_ck,
2847 .init = &omap2_init_clksel_parent, 2901 .init = &omap2_init_clksel_parent,
2848 .ops = &clkops_omap2_dflt, 2902 .ops = &clkops_omap2_dflt,
2849 .clksel = auxclk_sel, 2903 .clksel = auxclk_src_sel,
2850 .clksel_reg = OMAP4_SCRM_AUXCLK2, 2904 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2851 .clksel_mask = OMAP4_SRCSELECT_MASK, 2905 .clksel_mask = OMAP4_SRCSELECT_MASK,
2852 .recalc = &omap2_clksel_recalc, 2906 .recalc = &omap2_clksel_recalc,
@@ -2854,12 +2908,29 @@ static struct clk auxclk2_ck = {
2854 .enable_bit = OMAP4_ENABLE_SHIFT, 2908 .enable_bit = OMAP4_ENABLE_SHIFT,
2855}; 2909};
2856 2910
2857static struct clk auxclk3_ck = { 2911static const struct clksel auxclk2_sel[] = {
2858 .name = "auxclk3_ck", 2912 { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2913 { .parent = NULL },
2914};
2915
2916static struct clk auxclk2_ck = {
2917 .name = "auxclk2_ck",
2918 .parent = &auxclk2_src_ck,
2919 .clksel = auxclk2_sel,
2920 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2921 .clksel_mask = OMAP4_CLKDIV_MASK,
2922 .ops = &clkops_null,
2923 .recalc = &omap2_clksel_recalc,
2924 .round_rate = &omap2_clksel_round_rate,
2925 .set_rate = &omap2_clksel_set_rate,
2926};
2927
2928static struct clk auxclk3_src_ck = {
2929 .name = "auxclk3_src_ck",
2859 .parent = &sys_clkin_ck, 2930 .parent = &sys_clkin_ck,
2860 .init = &omap2_init_clksel_parent, 2931 .init = &omap2_init_clksel_parent,
2861 .ops = &clkops_omap2_dflt, 2932 .ops = &clkops_omap2_dflt,
2862 .clksel = auxclk_sel, 2933 .clksel = auxclk_src_sel,
2863 .clksel_reg = OMAP4_SCRM_AUXCLK3, 2934 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2864 .clksel_mask = OMAP4_SRCSELECT_MASK, 2935 .clksel_mask = OMAP4_SRCSELECT_MASK,
2865 .recalc = &omap2_clksel_recalc, 2936 .recalc = &omap2_clksel_recalc,
@@ -2867,12 +2938,29 @@ static struct clk auxclk3_ck = {
2867 .enable_bit = OMAP4_ENABLE_SHIFT, 2938 .enable_bit = OMAP4_ENABLE_SHIFT,
2868}; 2939};
2869 2940
2870static struct clk auxclk4_ck = { 2941static const struct clksel auxclk3_sel[] = {
2871 .name = "auxclk4_ck", 2942 { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2943 { .parent = NULL },
2944};
2945
2946static struct clk auxclk3_ck = {
2947 .name = "auxclk3_ck",
2948 .parent = &auxclk3_src_ck,
2949 .clksel = auxclk3_sel,
2950 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2951 .clksel_mask = OMAP4_CLKDIV_MASK,
2952 .ops = &clkops_null,
2953 .recalc = &omap2_clksel_recalc,
2954 .round_rate = &omap2_clksel_round_rate,
2955 .set_rate = &omap2_clksel_set_rate,
2956};
2957
2958static struct clk auxclk4_src_ck = {
2959 .name = "auxclk4_src_ck",
2872 .parent = &sys_clkin_ck, 2960 .parent = &sys_clkin_ck,
2873 .init = &omap2_init_clksel_parent, 2961 .init = &omap2_init_clksel_parent,
2874 .ops = &clkops_omap2_dflt, 2962 .ops = &clkops_omap2_dflt,
2875 .clksel = auxclk_sel, 2963 .clksel = auxclk_src_sel,
2876 .clksel_reg = OMAP4_SCRM_AUXCLK4, 2964 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2877 .clksel_mask = OMAP4_SRCSELECT_MASK, 2965 .clksel_mask = OMAP4_SRCSELECT_MASK,
2878 .recalc = &omap2_clksel_recalc, 2966 .recalc = &omap2_clksel_recalc,
@@ -2880,12 +2968,29 @@ static struct clk auxclk4_ck = {
2880 .enable_bit = OMAP4_ENABLE_SHIFT, 2968 .enable_bit = OMAP4_ENABLE_SHIFT,
2881}; 2969};
2882 2970
2883static struct clk auxclk5_ck = { 2971static const struct clksel auxclk4_sel[] = {
2884 .name = "auxclk5_ck", 2972 { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2973 { .parent = NULL },
2974};
2975
2976static struct clk auxclk4_ck = {
2977 .name = "auxclk4_ck",
2978 .parent = &auxclk4_src_ck,
2979 .clksel = auxclk4_sel,
2980 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2981 .clksel_mask = OMAP4_CLKDIV_MASK,
2982 .ops = &clkops_null,
2983 .recalc = &omap2_clksel_recalc,
2984 .round_rate = &omap2_clksel_round_rate,
2985 .set_rate = &omap2_clksel_set_rate,
2986};
2987
2988static struct clk auxclk5_src_ck = {
2989 .name = "auxclk5_src_ck",
2885 .parent = &sys_clkin_ck, 2990 .parent = &sys_clkin_ck,
2886 .init = &omap2_init_clksel_parent, 2991 .init = &omap2_init_clksel_parent,
2887 .ops = &clkops_omap2_dflt, 2992 .ops = &clkops_omap2_dflt,
2888 .clksel = auxclk_sel, 2993 .clksel = auxclk_src_sel,
2889 .clksel_reg = OMAP4_SCRM_AUXCLK5, 2994 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2890 .clksel_mask = OMAP4_SRCSELECT_MASK, 2995 .clksel_mask = OMAP4_SRCSELECT_MASK,
2891 .recalc = &omap2_clksel_recalc, 2996 .recalc = &omap2_clksel_recalc,
@@ -2893,6 +2998,23 @@ static struct clk auxclk5_ck = {
2893 .enable_bit = OMAP4_ENABLE_SHIFT, 2998 .enable_bit = OMAP4_ENABLE_SHIFT,
2894}; 2999};
2895 3000
3001static const struct clksel auxclk5_sel[] = {
3002 { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3003 { .parent = NULL },
3004};
3005
3006static struct clk auxclk5_ck = {
3007 .name = "auxclk5_ck",
3008 .parent = &auxclk5_src_ck,
3009 .clksel = auxclk5_sel,
3010 .clksel_reg = OMAP4_SCRM_AUXCLK5,
3011 .clksel_mask = OMAP4_CLKDIV_MASK,
3012 .ops = &clkops_null,
3013 .recalc = &omap2_clksel_recalc,
3014 .round_rate = &omap2_clksel_round_rate,
3015 .set_rate = &omap2_clksel_set_rate,
3016};
3017
2896static const struct clksel auxclkreq_sel[] = { 3018static const struct clksel auxclkreq_sel[] = {
2897 { .parent = &auxclk0_ck, .rates = div_1_0_rates }, 3019 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2898 { .parent = &auxclk1_ck, .rates = div_1_1_rates }, 3020 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
@@ -3093,12 +3215,12 @@ static struct omap_clk omap44xx_clks[] = {
3093 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 3215 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
3094 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 3216 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
3095 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), 3217 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
3096 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), 3218 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
3097 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 3219 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
3098 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), 3220 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
3099 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), 3221 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
3100 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), 3222 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
3101 CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), 3223 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
3102 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), 3224 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3103 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 3225 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
3104 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 3226 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
@@ -3109,23 +3231,23 @@ static struct omap_clk omap44xx_clks[] = {
3109 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 3231 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
3110 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 3232 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
3111 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 3233 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
3112 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), 3234 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
3113 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 3235 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
3114 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), 3236 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
3115 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 3237 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
3116 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), 3238 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
3117 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 3239 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
3118 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), 3240 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
3119 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), 3241 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
3120 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), 3242 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
3121 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 3243 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
3122 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 3244 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
3123 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), 3245 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
3124 CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), 3246 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
3125 CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), 3247 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
3126 CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), 3248 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
3127 CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), 3249 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
3128 CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), 3250 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
3129 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), 3251 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3130 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), 3252 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3131 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), 3253 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
@@ -3182,21 +3304,27 @@ static struct omap_clk omap44xx_clks[] = {
3182 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 3304 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3183 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 3305 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3184 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3306 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3185 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), 3307 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
3186 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), 3308 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3187 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 3309 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3188 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 3310 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3311 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
3189 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), 3312 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3190 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3191 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3192 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3193 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3194 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3195 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), 3313 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3314 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
3315 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3196 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), 3316 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3317 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
3318 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3197 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), 3319 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3320 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
3321 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3198 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), 3322 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3323 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
3324 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3199 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), 3325 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3326 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
3327 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3200 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), 3328 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3201 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3329 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3202 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 3330 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
@@ -3251,6 +3379,7 @@ int __init omap4xxx_clk_init(void)
3251 } 3379 }
3252 3380
3253 clk_init(&omap2_clk_functions); 3381 clk_init(&omap2_clk_functions);
3382 omap2_clk_disable_clkdm_control();
3254 3383
3255 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); 3384 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3256 c++) 3385 c++)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 20:25:12 -0500