1 files changed, 287 insertions, 203 deletions

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c965671b4d4..2af0e3f00ce1 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
 static struct clk pad_clks_ck = {
         .name           = "pad_clks_ck",
         .rate           = 12000000,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
 };
 
 static struct clk pad_slimbus_core_clks_ck = {
@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
 static struct clk slimbus_clk = {
         .name           = "slimbus_clk",
         .rate           = 12000000,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
 };
 
 static struct clk sys_32k_ck = {
@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
 static struct clk dpll_abe_x2_ck = {
         .name           = "dpll_abe_x2_ck",
         .parent         = &dpll_abe_ck,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
         .flags          = CLOCK_CLKOUTX2,
         .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap3_clkoutx2_recalc,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 };
 
 static const struct clksel_rate div31_1to31_rates[] = {
@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
-        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 };
 
 static struct clk dpll_core_m7x2_ck = {
@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
 static struct clk dpll_per_x2_ck = {
         .name           = "dpll_per_x2_ck",
         .parent         = &dpll_per_ck,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
         .flags          = CLOCK_CLKOUTX2,
         .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap3_clkoutx2_recalc,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 };
 
 static const struct clksel dpll_per_m2x2_div[] = {
@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
-        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 };
 
 static struct clk dpll_per_m4x2_ck = {
@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-/* DPLL_UNIPRO */
-static struct dpll_data dpll_unipro_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
-        .min_divider    = 1,
-};
-
-
-static struct clk dpll_unipro_ck = {
-        .name           = "dpll_unipro_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_unipro_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_unipro_x2_ck = {
-        .name           = "dpll_unipro_x2_ck",
-        .parent         = &dpll_unipro_ck,
-        .flags          = CLOCK_CLKOUTX2,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel dpll_unipro_m2x2_div[] = {
-        { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-static struct clk dpll_unipro_m2x2_ck = {
-        .name           = "dpll_unipro_m2x2_ck",
-        .parent         = &dpll_unipro_x2_ck,
-        .clksel         = dpll_unipro_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
 static struct clk usb_hs_clk_div_ck = {
         .name           = "usb_hs_clk_div_ck",
         .parent         = &dpll_abe_m3x2_ck,
@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
+        .max_multiplier = 4095,
+        .max_divider    = 256,
         .min_divider    = 1,
 };
 
@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
 static struct clk dpll_usb_clkdcoldo_ck = {
         .name           = "dpll_usb_clkdcoldo_ck",
         .parent         = &dpll_usb_ck,
-        .ops            = &clkops_omap4_dpllmx_ops,
         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &followparent_recalc,
 };
 
@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel hsmmc6_fclk_sel[] = {
-        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
-        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk hsmmc6_fclk = {
-        .name           = "hsmmc6_fclk",
-        .parent         = &func_64m_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
 static const struct clksel_rate div2_1to8_rates[] = {
         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+static struct clk ocp_abe_iclk = {
+        .name           = "ocp_abe_iclk",
+        .parent         = &aess_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_abe_24m_fclk = {
+        .name           = "per_abe_24m_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
 static const struct clksel per_abe_nc_fclk_div[] = {
         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
         { .parent = NULL },
@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel mcasp2_fclk_sel[] = {
-        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
-        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk mcasp2_fclk = {
-        .name           = "mcasp2_fclk",
-        .parent         = &func_96m_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcasp3_fclk = {
-        .name           = "mcasp3_fclk",
-        .parent         = &func_96m_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ocp_abe_iclk = {
-        .name           = "ocp_abe_iclk",
-        .parent         = &aess_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk per_abe_24m_fclk = {
-        .name           = "per_abe_24m_fclk",
-        .parent         = &dpll_abe_m2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 4,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-
 static const struct clksel pmd_stm_clock_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@@ -1486,6 +1397,40 @@ static struct clk dss_dss_clk = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate div3_8to32_rates[] = {
+        { .div = 8, .val = 0, .flags = RATE_IN_44XX },
+        { .div = 16, .val = 1, .flags = RATE_IN_44XX },
+        { .div = 32, .val = 2, .flags = RATE_IN_44XX },
+        { .div = 0 },
+};
+
+static const struct clksel div_ts_div[] = {
+        { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
+        { .parent = NULL },
+};
+
+static struct clk div_ts_ck = {
+        .name           = "div_ts_ck",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .clksel         = div_ts_div,
+        .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk bandgap_ts_fclk = {
+        .name           = "bandgap_ts_fclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &div_ts_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_48mhz_clk = {
         .name           = "dss_48mhz_clk",
         .ops            = &clkops_omap2_dflt,
@@ -1694,6 +1639,7 @@ static struct clk gpmc_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "l3_2_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
@@ -1846,8 +1792,8 @@ static struct clk l3_instr_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
         .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -1857,8 +1803,8 @@ static struct clk l3_main_3_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
         .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -1995,10 +1941,16 @@ static struct clk mcbsp3_fck = {
         .clkdm_name     = "abe_clkdm",
 };
 
+static const struct clksel mcbsp4_sync_mux_sel[] = {
+        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
+        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
 static struct clk mcbsp4_sync_mux_ck = {
         .name           = "mcbsp4_sync_mux_ck",
         .parent         = &func_96m_fclk,
-        .clksel         = mcasp2_fclk_sel,
+        .clksel         = mcbsp4_sync_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@@ -2077,11 +2029,17 @@ static struct clk mcspi4_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel hsmmc1_fclk_sel[] = {
+        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
 /* Merged hsmmc1_fclk into mmc1 */
 static struct clk mmc1_fck = {
         .name           = "mmc1_fck",
         .parent         = &func_64m_fclk,
-        .clksel         = hsmmc6_fclk_sel,
+        .clksel         = hsmmc1_fclk_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_MASK,
@@ -2096,7 +2054,7 @@ static struct clk mmc1_fck = {
 static struct clk mmc2_fck = {
         .name           = "mmc2_fck",
         .parent         = &func_64m_fclk,
-        .clksel         = hsmmc6_fclk_sel,
+        .clksel         = hsmmc1_fclk_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_MASK,
@@ -2162,8 +2120,8 @@ static struct clk ocp_wp_noc_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
         .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -2850,19 +2808,39 @@ static struct clk trace_clk_div_ck = {
 
 /* SCRM aux clk nodes */
 
-static const struct clksel auxclk_sel[] = {
+static const struct clksel auxclk_src_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
         { .parent = NULL },
 };
 
-static struct clk auxclk0_ck = {
-        .name           = "auxclk0_ck",
+static const struct clksel_rate div16_1to16_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static struct clk auxclk0_src_ck = {
+        .name           = "auxclk0_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2870,12 +2848,29 @@ static struct clk auxclk0_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk1_ck = {
-        .name           = "auxclk1_ck",
+static const struct clksel auxclk0_sel[] = {
+        { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk0_ck = {
+        .name           = "auxclk0_ck",
+        .parent         = &auxclk0_src_ck,
+        .clksel         = auxclk0_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk1_src_ck = {
+        .name           = "auxclk1_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2883,24 +2878,59 @@ static struct clk auxclk1_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk2_ck = {
-        .name           = "auxclk2_ck",
+static const struct clksel auxclk1_sel[] = {
+        { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk1_ck = {
+        .name           = "auxclk1_ck",
+        .parent         = &auxclk1_src_ck,
+        .clksel         = auxclk1_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk2_src_ck = {
+        .name           = "auxclk2_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
         .enable_reg     = OMAP4_SCRM_AUXCLK2,
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
-static struct clk auxclk3_ck = {
-        .name           = "auxclk3_ck",
+
+static const struct clksel auxclk2_sel[] = {
+        { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk2_ck = {
+        .name           = "auxclk2_ck",
+        .parent         = &auxclk2_src_ck,
+        .clksel         = auxclk2_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk3_src_ck = {
+        .name           = "auxclk3_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2908,12 +2938,29 @@ static struct clk auxclk3_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk4_ck = {
-        .name           = "auxclk4_ck",
+static const struct clksel auxclk3_sel[] = {
+        { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk3_ck = {
+        .name           = "auxclk3_ck",
+        .parent         = &auxclk3_src_ck,
+        .clksel         = auxclk3_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk4_src_ck = {
+        .name           = "auxclk4_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2921,12 +2968,29 @@ static struct clk auxclk4_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk5_ck = {
-        .name           = "auxclk5_ck",
+static const struct clksel auxclk4_sel[] = {
+        { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk4_ck = {
+        .name           = "auxclk4_ck",
+        .parent         = &auxclk4_src_ck,
+        .clksel         = auxclk4_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk5_src_ck = {
+        .name           = "auxclk5_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2934,6 +2998,23 @@ static struct clk auxclk5_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
+static const struct clksel auxclk5_sel[] = {
+        { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk5_ck = {
+        .name           = "auxclk5_ck",
+        .parent         = &auxclk5_src_ck,
+        .clksel         = auxclk5_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
 static const struct clksel auxclkreq_sel[] = {
         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
@@ -3077,9 +3158,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
-        CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
-        CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
@@ -3092,17 +3170,14 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
-        CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
-        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
-        CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
-        CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
@@ -3110,14 +3185,16 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
+        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
+        CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
-        CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
-        CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
-        CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
-        CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@ -3138,12 +3215,12 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
-        CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
+        CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
-        CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
-        CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
-        CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
+        CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
+        CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
+        CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
+        CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
@@ -3154,23 +3231,23 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
+        CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
+        CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
+        CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
-        CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
-        CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
-        CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
-        CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
-        CLK("omap_hsmmc.0",     "fck",                          &mmc1_fck,      CK_443X),
-        CLK("omap_hsmmc.1",     "fck",                          &mmc2_fck,      CK_443X),
-        CLK("omap_hsmmc.2",     "fck",                          &mmc3_fck,      CK_443X),
-        CLK("omap_hsmmc.3",     "fck",                          &mmc4_fck,      CK_443X),
-        CLK("omap_hsmmc.4",     "fck",                          &mmc5_fck,      CK_443X),
+        CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
+        CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
+        CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
+        CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
+        CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
+        CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
+        CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
+        CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
+        CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
@@ -3204,7 +3281,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
         CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
@@ -3216,9 +3292,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
-        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
         CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
-        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
@@ -3226,17 +3300,32 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
         CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
-        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
+        CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
+        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
+        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
+        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
+        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
+        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
+        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
@@ -3253,6 +3342,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
         CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
@@ -3270,19 +3360,9 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
+        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
+        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
-        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
-        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
-        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
-        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
-        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
-        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
-        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
-        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
-        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
-        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
@@ -3293,9 +3373,13 @@ int __init omap4xxx_clk_init(void)
         if (cpu_is_omap44xx()) {
                 cpu_mask = RATE_IN_4430;
                 cpu_clkflg = CK_443X;
+        } else if (cpu_is_omap446x()) {
+                cpu_mask = RATE_IN_4460;
+                cpu_clkflg = CK_446X;
         }
 
         clk_init(&omap2_clk_functions);
+        omap2_clk_disable_clkdm_control();
 
         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
                                                                           c++)