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Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c412
1 files changed, 162 insertions, 250 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 9cba5560519b..833be485c89e 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -110,32 +110,32 @@ static struct clk virt_38_4m_ck = {
110}; 110};
111 111
112static const struct clksel_rate osc_sys_12m_rates[] = { 112static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
114 { .div = 0 } 114 { .div = 0 }
115}; 115};
116 116
117static const struct clksel_rate osc_sys_13m_rates[] = { 117static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
119 { .div = 0 } 119 { .div = 0 }
120}; 120};
121 121
122static const struct clksel_rate osc_sys_16_8m_rates[] = { 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
124 { .div = 0 } 124 { .div = 0 }
125}; 125};
126 126
127static const struct clksel_rate osc_sys_19_2m_rates[] = { 127static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
129 { .div = 0 } 129 { .div = 0 }
130}; 130};
131 131
132static const struct clksel_rate osc_sys_26m_rates[] = { 132static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
134 { .div = 0 } 134 { .div = 0 }
135}; 135};
136 136
137static const struct clksel_rate osc_sys_38_4m_rates[] = { 137static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, 138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
139 { .div = 0 } 139 { .div = 0 }
140}; 140};
141 141
@@ -163,8 +163,8 @@ static struct clk osc_sys_ck = {
163}; 163};
164 164
165static const struct clksel_rate div2_rates[] = { 165static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
168 { .div = 0 } 168 { .div = 0 }
169}; 169};
170 170
@@ -213,42 +213,42 @@ static struct clk sys_clkout1 = {
213/* CM CLOCKS */ 213/* CM CLOCKS */
214 214
215static const struct clksel_rate div16_dpll_rates[] = { 215static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_343X }, 220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_343X }, 222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_343X }, 224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_343X }, 225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_343X }, 226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_343X }, 227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_343X }, 228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_343X }, 229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_343X }, 230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_343X }, 231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
232 { .div = 0 } 232 { .div = 0 }
233}; 233};
234 234
235static const struct clksel_rate div32_dpll4_rates_3630[] = { 235static const struct clksel_rate dpll4_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE }, 236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
237 { .div = 2, .val = 2, .flags = RATE_IN_36XX }, 237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
238 { .div = 3, .val = 3, .flags = RATE_IN_36XX }, 238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
239 { .div = 4, .val = 4, .flags = RATE_IN_36XX }, 239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
240 { .div = 5, .val = 5, .flags = RATE_IN_36XX }, 240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
241 { .div = 6, .val = 6, .flags = RATE_IN_36XX }, 241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
242 { .div = 7, .val = 7, .flags = RATE_IN_36XX }, 242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
243 { .div = 8, .val = 8, .flags = RATE_IN_36XX }, 243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
244 { .div = 9, .val = 9, .flags = RATE_IN_36XX }, 244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
245 { .div = 10, .val = 10, .flags = RATE_IN_36XX }, 245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
246 { .div = 11, .val = 11, .flags = RATE_IN_36XX }, 246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
247 { .div = 12, .val = 12, .flags = RATE_IN_36XX }, 247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
248 { .div = 13, .val = 13, .flags = RATE_IN_36XX }, 248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
249 { .div = 14, .val = 14, .flags = RATE_IN_36XX }, 249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
250 { .div = 15, .val = 15, .flags = RATE_IN_36XX }, 250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
251 { .div = 16, .val = 16, .flags = RATE_IN_36XX }, 251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
252 { .div = 17, .val = 17, .flags = RATE_IN_36XX }, 252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX }, 253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX }, 254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
@@ -450,37 +450,37 @@ static struct clk dpll3_x2_ck = {
450}; 450};
451 451
452static const struct clksel_rate div31_dpll3_rates[] = { 452static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, 455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, 456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, 457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, 458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, 459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, 460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, 461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, 462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, 463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, 464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, 465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, 466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, 467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, 468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, 469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, 470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, 471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, 472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, 473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, 474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, 475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, 476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, 477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, 478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, 479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, 480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, 481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, 482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, 483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
484 { .div = 0 }, 484 { .div = 0 },
485}; 485};
486 486
@@ -562,6 +562,7 @@ static struct clk emu_core_alwon_ck = {
562/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ 562/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
563/* Type: DPLL */ 563/* Type: DPLL */
564static struct dpll_data dpll4_dd; 564static struct dpll_data dpll4_dd;
565
565static struct dpll_data dpll4_dd_34xx __initdata = { 566static struct dpll_data dpll4_dd_34xx __initdata = {
566 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 567 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
567 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, 568 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
@@ -632,39 +633,20 @@ static struct clk dpll4_x2_ck = {
632 .recalc = &omap3_clkoutx2_recalc, 633 .recalc = &omap3_clkoutx2_recalc,
633}; 634};
634 635
635static const struct clksel div16_dpll4_clksel[] = { 636static const struct clksel dpll4_clksel[] = {
636 { .parent = &dpll4_ck, .rates = div16_dpll_rates }, 637 { .parent = &dpll4_ck, .rates = dpll4_rates },
637 { .parent = NULL }
638};
639
640static const struct clksel div32_dpll4_clksel[] = {
641 { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
642 { .parent = NULL } 638 { .parent = NULL }
643}; 639};
644 640
645/* This virtual clock is the source for dpll4_m2x2_ck */ 641/* This virtual clock is the source for dpll4_m2x2_ck */
646static struct clk dpll4_m2_ck; 642static struct clk dpll4_m2_ck = {
647
648static struct clk dpll4_m2_ck_34xx __initdata = {
649 .name = "dpll4_m2_ck",
650 .ops = &clkops_null,
651 .parent = &dpll4_ck,
652 .init = &omap2_init_clksel_parent,
653 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
654 .clksel_mask = OMAP3430_DIV_96M_MASK,
655 .clksel = div16_dpll4_clksel,
656 .clkdm_name = "dpll4_clkdm",
657 .recalc = &omap2_clksel_recalc,
658};
659
660static struct clk dpll4_m2_ck_3630 __initdata = {
661 .name = "dpll4_m2_ck", 643 .name = "dpll4_m2_ck",
662 .ops = &clkops_null, 644 .ops = &clkops_null,
663 .parent = &dpll4_ck, 645 .parent = &dpll4_ck,
664 .init = &omap2_init_clksel_parent, 646 .init = &omap2_init_clksel_parent,
665 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 647 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
666 .clksel_mask = OMAP3630_DIV_96M_MASK, 648 .clksel_mask = OMAP3630_DIV_96M_MASK,
667 .clksel = div32_dpll4_clksel, 649 .clksel = dpll4_clksel,
668 .clkdm_name = "dpll4_clkdm", 650 .clkdm_name = "dpll4_clkdm",
669 .recalc = &omap2_clksel_recalc, 651 .recalc = &omap2_clksel_recalc,
670}; 652};
@@ -698,7 +680,7 @@ static struct clk omap_192m_alwon_fck = {
698 680
699static const struct clksel_rate omap_96m_alwon_fck_rates[] = { 681static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
700 { .div = 1, .val = 1, .flags = RATE_IN_36XX }, 682 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
701 { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE }, 683 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
702 { .div = 0 } 684 { .div = 0 }
703}; 685};
704 686
@@ -708,12 +690,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
708}; 690};
709 691
710static const struct clksel_rate omap_96m_dpll_rates[] = { 692static const struct clksel_rate omap_96m_dpll_rates[] = {
711 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 693 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
712 { .div = 0 } 694 { .div = 0 }
713}; 695};
714 696
715static const struct clksel_rate omap_96m_sys_rates[] = { 697static const struct clksel_rate omap_96m_sys_rates[] = {
716 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 698 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
717 { .div = 0 } 699 { .div = 0 }
718}; 700};
719 701
@@ -760,28 +742,14 @@ static struct clk omap_96m_fck = {
760}; 742};
761 743
762/* This virtual clock is the source for dpll4_m3x2_ck */ 744/* This virtual clock is the source for dpll4_m3x2_ck */
763static struct clk dpll4_m3_ck; 745static struct clk dpll4_m3_ck = {
764
765static struct clk dpll4_m3_ck_34xx __initdata = {
766 .name = "dpll4_m3_ck", 746 .name = "dpll4_m3_ck",
767 .ops = &clkops_null, 747 .ops = &clkops_null,
768 .parent = &dpll4_ck, 748 .parent = &dpll4_ck,
769 .init = &omap2_init_clksel_parent, 749 .init = &omap2_init_clksel_parent,
770 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 750 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
771 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 751 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
772 .clksel = div16_dpll4_clksel, 752 .clksel = dpll4_clksel,
773 .clkdm_name = "dpll4_clkdm",
774 .recalc = &omap2_clksel_recalc,
775};
776
777static struct clk dpll4_m3_ck_3630 __initdata = {
778 .name = "dpll4_m3_ck",
779 .ops = &clkops_null,
780 .parent = &dpll4_ck,
781 .init = &omap2_init_clksel_parent,
782 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
783 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
784 .clksel = div32_dpll4_clksel,
785 .clkdm_name = "dpll4_clkdm", 753 .clkdm_name = "dpll4_clkdm",
786 .recalc = &omap2_clksel_recalc, 754 .recalc = &omap2_clksel_recalc,
787}; 755};
@@ -799,12 +767,12 @@ static struct clk dpll4_m3x2_ck = {
799}; 767};
800 768
801static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 769static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
802 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 770 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
803 { .div = 0 } 771 { .div = 0 }
804}; 772};
805 773
806static const struct clksel_rate omap_54m_alt_rates[] = { 774static const struct clksel_rate omap_54m_alt_rates[] = {
807 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 775 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
808 { .div = 0 } 776 { .div = 0 }
809}; 777};
810 778
@@ -825,12 +793,12 @@ static struct clk omap_54m_fck = {
825}; 793};
826 794
827static const struct clksel_rate omap_48m_cm96m_rates[] = { 795static const struct clksel_rate omap_48m_cm96m_rates[] = {
828 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 796 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
829 { .div = 0 } 797 { .div = 0 }
830}; 798};
831 799
832static const struct clksel_rate omap_48m_alt_rates[] = { 800static const struct clksel_rate omap_48m_alt_rates[] = {
833 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 801 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
834 { .div = 0 } 802 { .div = 0 }
835}; 803};
836 804
@@ -858,31 +826,15 @@ static struct clk omap_12m_fck = {
858 .recalc = &omap_fixed_divisor_recalc, 826 .recalc = &omap_fixed_divisor_recalc,
859}; 827};
860 828
861/* This virstual clock is the source for dpll4_m4x2_ck */ 829/* This virtual clock is the source for dpll4_m4x2_ck */
862static struct clk dpll4_m4_ck; 830static struct clk dpll4_m4_ck = {
863
864static struct clk dpll4_m4_ck_34xx __initdata = {
865 .name = "dpll4_m4_ck", 831 .name = "dpll4_m4_ck",
866 .ops = &clkops_null, 832 .ops = &clkops_null,
867 .parent = &dpll4_ck, 833 .parent = &dpll4_ck,
868 .init = &omap2_init_clksel_parent, 834 .init = &omap2_init_clksel_parent,
869 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 835 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
870 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 836 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
871 .clksel = div16_dpll4_clksel, 837 .clksel = dpll4_clksel,
872 .clkdm_name = "dpll4_clkdm",
873 .recalc = &omap2_clksel_recalc,
874 .set_rate = &omap2_clksel_set_rate,
875 .round_rate = &omap2_clksel_round_rate,
876};
877
878static struct clk dpll4_m4_ck_3630 __initdata = {
879 .name = "dpll4_m4_ck",
880 .ops = &clkops_null,
881 .parent = &dpll4_ck,
882 .init = &omap2_init_clksel_parent,
883 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
884 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
885 .clksel = div32_dpll4_clksel,
886 .clkdm_name = "dpll4_clkdm", 838 .clkdm_name = "dpll4_clkdm",
887 .recalc = &omap2_clksel_recalc, 839 .recalc = &omap2_clksel_recalc,
888 .set_rate = &omap2_clksel_set_rate, 840 .set_rate = &omap2_clksel_set_rate,
@@ -902,30 +854,14 @@ static struct clk dpll4_m4x2_ck = {
902}; 854};
903 855
904/* This virtual clock is the source for dpll4_m5x2_ck */ 856/* This virtual clock is the source for dpll4_m5x2_ck */
905static struct clk dpll4_m5_ck; 857static struct clk dpll4_m5_ck = {
906
907static struct clk dpll4_m5_ck_34xx __initdata = {
908 .name = "dpll4_m5_ck", 858 .name = "dpll4_m5_ck",
909 .ops = &clkops_null, 859 .ops = &clkops_null,
910 .parent = &dpll4_ck, 860 .parent = &dpll4_ck,
911 .init = &omap2_init_clksel_parent, 861 .init = &omap2_init_clksel_parent,
912 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 862 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
913 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 863 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
914 .clksel = div16_dpll4_clksel, 864 .clksel = dpll4_clksel,
915 .clkdm_name = "dpll4_clkdm",
916 .set_rate = &omap2_clksel_set_rate,
917 .round_rate = &omap2_clksel_round_rate,
918 .recalc = &omap2_clksel_recalc,
919};
920
921static struct clk dpll4_m5_ck_3630 __initdata = {
922 .name = "dpll4_m5_ck",
923 .ops = &clkops_null,
924 .parent = &dpll4_ck,
925 .init = &omap2_init_clksel_parent,
926 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
927 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
928 .clksel = div32_dpll4_clksel,
929 .clkdm_name = "dpll4_clkdm", 865 .clkdm_name = "dpll4_clkdm",
930 .set_rate = &omap2_clksel_set_rate, 866 .set_rate = &omap2_clksel_set_rate,
931 .round_rate = &omap2_clksel_round_rate, 867 .round_rate = &omap2_clksel_round_rate,
@@ -945,28 +881,14 @@ static struct clk dpll4_m5x2_ck = {
945}; 881};
946 882
947/* This virtual clock is the source for dpll4_m6x2_ck */ 883/* This virtual clock is the source for dpll4_m6x2_ck */
948static struct clk dpll4_m6_ck; 884static struct clk dpll4_m6_ck = {
949
950static struct clk dpll4_m6_ck_34xx __initdata = {
951 .name = "dpll4_m6_ck", 885 .name = "dpll4_m6_ck",
952 .ops = &clkops_null, 886 .ops = &clkops_null,
953 .parent = &dpll4_ck, 887 .parent = &dpll4_ck,
954 .init = &omap2_init_clksel_parent, 888 .init = &omap2_init_clksel_parent,
955 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 889 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
956 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 890 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
957 .clksel = div16_dpll4_clksel, 891 .clksel = dpll4_clksel,
958 .clkdm_name = "dpll4_clkdm",
959 .recalc = &omap2_clksel_recalc,
960};
961
962static struct clk dpll4_m6_ck_3630 __initdata = {
963 .name = "dpll4_m6_ck",
964 .ops = &clkops_null,
965 .parent = &dpll4_ck,
966 .init = &omap2_init_clksel_parent,
967 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
968 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
969 .clksel = div32_dpll4_clksel,
970 .clkdm_name = "dpll4_clkdm", 892 .clkdm_name = "dpll4_clkdm",
971 .recalc = &omap2_clksel_recalc, 893 .recalc = &omap2_clksel_recalc,
972}; 894};
@@ -1049,22 +971,22 @@ static struct clk dpll5_m2_ck = {
1049/* CM EXTERNAL CLOCK OUTPUTS */ 971/* CM EXTERNAL CLOCK OUTPUTS */
1050 972
1051static const struct clksel_rate clkout2_src_core_rates[] = { 973static const struct clksel_rate clkout2_src_core_rates[] = {
1052 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 974 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1053 { .div = 0 } 975 { .div = 0 }
1054}; 976};
1055 977
1056static const struct clksel_rate clkout2_src_sys_rates[] = { 978static const struct clksel_rate clkout2_src_sys_rates[] = {
1057 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 979 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1058 { .div = 0 } 980 { .div = 0 }
1059}; 981};
1060 982
1061static const struct clksel_rate clkout2_src_96m_rates[] = { 983static const struct clksel_rate clkout2_src_96m_rates[] = {
1062 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 984 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1063 { .div = 0 } 985 { .div = 0 }
1064}; 986};
1065 987
1066static const struct clksel_rate clkout2_src_54m_rates[] = { 988static const struct clksel_rate clkout2_src_54m_rates[] = {
1067 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 989 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1068 { .div = 0 } 990 { .div = 0 }
1069}; 991};
1070 992
@@ -1090,11 +1012,11 @@ static struct clk clkout2_src_ck = {
1090}; 1012};
1091 1013
1092static const struct clksel_rate sys_clkout2_rates[] = { 1014static const struct clksel_rate sys_clkout2_rates[] = {
1093 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1015 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1094 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1016 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1095 { .div = 4, .val = 2, .flags = RATE_IN_343X }, 1017 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1096 { .div = 8, .val = 3, .flags = RATE_IN_343X }, 1018 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1097 { .div = 16, .val = 4, .flags = RATE_IN_343X }, 1019 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1098 { .div = 0 }, 1020 { .div = 0 },
1099}; 1021};
1100 1022
@@ -1111,6 +1033,8 @@ static struct clk sys_clkout2 = {
1111 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 1033 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1112 .clksel = sys_clkout2_clksel, 1034 .clksel = sys_clkout2_clksel,
1113 .recalc = &omap2_clksel_recalc, 1035 .recalc = &omap2_clksel_recalc,
1036 .round_rate = &omap2_clksel_round_rate,
1037 .set_rate = &omap2_clksel_set_rate
1114}; 1038};
1115 1039
1116/* CM OUTPUT CLOCKS */ 1040/* CM OUTPUT CLOCKS */
@@ -1125,9 +1049,9 @@ static struct clk corex2_fck = {
1125/* DPLL power domain clock controls */ 1049/* DPLL power domain clock controls */
1126 1050
1127static const struct clksel_rate div4_rates[] = { 1051static const struct clksel_rate div4_rates[] = {
1128 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1052 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1129 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1053 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1130 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1054 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1131 { .div = 0 } 1055 { .div = 0 }
1132}; 1056};
1133 1057
@@ -1161,8 +1085,8 @@ static struct clk mpu_ck = {
1161 1085
1162/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1086/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1163static const struct clksel_rate arm_fck_rates[] = { 1087static const struct clksel_rate arm_fck_rates[] = {
1164 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1088 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1165 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1089 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1166 { .div = 0 }, 1090 { .div = 0 },
1167}; 1091};
1168 1092
@@ -1333,25 +1257,25 @@ static struct clk gfx_cg2_ck = {
1333 1257
1334static const struct clksel_rate sgx_core_rates[] = { 1258static const struct clksel_rate sgx_core_rates[] = {
1335 { .div = 2, .val = 5, .flags = RATE_IN_36XX }, 1259 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1336 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1260 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1337 { .div = 4, .val = 1, .flags = RATE_IN_343X }, 1261 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1338 { .div = 6, .val = 2, .flags = RATE_IN_343X }, 1262 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1339 { .div = 0 }, 1263 { .div = 0 },
1340}; 1264};
1341 1265
1342static const struct clksel_rate sgx_192m_rates[] = { 1266static const struct clksel_rate sgx_192m_rates[] = {
1343 { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE }, 1267 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1344 { .div = 0 }, 1268 { .div = 0 },
1345}; 1269};
1346 1270
1347static const struct clksel_rate sgx_corex2_rates[] = { 1271static const struct clksel_rate sgx_corex2_rates[] = {
1348 { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE }, 1272 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1349 { .div = 5, .val = 7, .flags = RATE_IN_36XX }, 1273 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1350 { .div = 0 }, 1274 { .div = 0 },
1351}; 1275};
1352 1276
1353static const struct clksel_rate sgx_96m_rates[] = { 1277static const struct clksel_rate sgx_96m_rates[] = {
1354 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 1278 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1355 { .div = 0 }, 1279 { .div = 0 },
1356}; 1280};
1357 1281
@@ -1576,12 +1500,12 @@ static struct clk i2c1_fck = {
1576 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. 1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1577 */ 1501 */
1578static const struct clksel_rate common_mcbsp_96m_rates[] = { 1502static const struct clksel_rate common_mcbsp_96m_rates[] = {
1579 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1580 { .div = 0 } 1504 { .div = 0 }
1581}; 1505};
1582 1506
1583static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { 1507static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1584 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1585 { .div = 0 } 1509 { .div = 0 }
1586}; 1510};
1587 1511
@@ -1714,12 +1638,12 @@ static struct clk hdq_fck = {
1714/* DPLL3-derived clock */ 1638/* DPLL3-derived clock */
1715 1639
1716static const struct clksel_rate ssi_ssr_corex2_rates[] = { 1640static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1717 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1641 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1718 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1642 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1719 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 1643 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1720 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1644 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1721 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 1645 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1722 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 1646 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1723 { .div = 0 } 1647 { .div = 0 }
1724}; 1648};
1725 1649
@@ -2353,18 +2277,18 @@ static struct clk usbhost_ick = {
2353/* WKUP */ 2277/* WKUP */
2354 2278
2355static const struct clksel_rate usim_96m_rates[] = { 2279static const struct clksel_rate usim_96m_rates[] = {
2356 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2280 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2357 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2281 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2358 { .div = 8, .val = 5, .flags = RATE_IN_343X }, 2282 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2359 { .div = 10, .val = 6, .flags = RATE_IN_343X }, 2283 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2360 { .div = 0 }, 2284 { .div = 0 },
2361}; 2285};
2362 2286
2363static const struct clksel_rate usim_120m_rates[] = { 2287static const struct clksel_rate usim_120m_rates[] = {
2364 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, 2288 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2365 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 2289 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2366 { .div = 16, .val = 9, .flags = RATE_IN_343X }, 2290 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2367 { .div = 20, .val = 10, .flags = RATE_IN_343X }, 2291 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2368 { .div = 0 }, 2292 { .div = 0 },
2369}; 2293};
2370 2294
@@ -2951,22 +2875,22 @@ static struct clk mcbsp4_fck = {
2951/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ 2875/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2952 2876
2953static const struct clksel_rate emu_src_sys_rates[] = { 2877static const struct clksel_rate emu_src_sys_rates[] = {
2954 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 2878 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2955 { .div = 0 }, 2879 { .div = 0 },
2956}; 2880};
2957 2881
2958static const struct clksel_rate emu_src_core_rates[] = { 2882static const struct clksel_rate emu_src_core_rates[] = {
2959 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2883 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2960 { .div = 0 }, 2884 { .div = 0 },
2961}; 2885};
2962 2886
2963static const struct clksel_rate emu_src_per_rates[] = { 2887static const struct clksel_rate emu_src_per_rates[] = {
2964 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2888 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2965 { .div = 0 }, 2889 { .div = 0 },
2966}; 2890};
2967 2891
2968static const struct clksel_rate emu_src_mpu_rates[] = { 2892static const struct clksel_rate emu_src_mpu_rates[] = {
2969 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2893 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2970 { .div = 0 }, 2894 { .div = 0 },
2971}; 2895};
2972 2896
@@ -2995,10 +2919,10 @@ static struct clk emu_src_ck = {
2995}; 2919};
2996 2920
2997static const struct clksel_rate pclk_emu_rates[] = { 2921static const struct clksel_rate pclk_emu_rates[] = {
2998 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2922 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2999 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2923 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
3000 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2924 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3001 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 2925 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
3002 { .div = 0 }, 2926 { .div = 0 },
3003}; 2927};
3004 2928
@@ -3019,9 +2943,9 @@ static struct clk pclk_fck = {
3019}; 2943};
3020 2944
3021static const struct clksel_rate pclkx2_emu_rates[] = { 2945static const struct clksel_rate pclkx2_emu_rates[] = {
3022 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2946 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3023 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 2947 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3024 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2948 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
3025 { .div = 0 }, 2949 { .div = 0 },
3026}; 2950};
3027 2951
@@ -3069,9 +2993,9 @@ static struct clk traceclk_src_fck = {
3069}; 2993};
3070 2994
3071static const struct clksel_rate traceclk_rates[] = { 2995static const struct clksel_rate traceclk_rates[] = {
3072 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2996 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3073 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 2997 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3074 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2998 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3075 { .div = 0 }, 2999 { .div = 0 },
3076}; 3000};
3077 3001
@@ -3472,8 +3396,8 @@ static struct omap_clk omap3xxx_clks[] = {
3472 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), 3396 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3473 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), 3397 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3474 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), 3398 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3475 CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX), 3399 CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
3476 CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX), 3400 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
3477 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), 3401 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3478 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), 3402 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3479 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), 3403 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
@@ -3488,14 +3412,8 @@ int __init omap3xxx_clk_init(void)
3488 struct omap_clk *c; 3412 struct omap_clk *c;
3489 u32 cpu_clkflg = CK_3XXX; 3413 u32 cpu_clkflg = CK_3XXX;
3490 3414
3491 if (cpu_is_omap3517()) { 3415 if (cpu_is_omap34xx()) {
3492 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; 3416 cpu_mask = RATE_IN_3XXX;
3493 cpu_clkflg |= CK_3517;
3494 } else if (cpu_is_omap3505()) {
3495 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3496 cpu_clkflg |= CK_3505;
3497 } else if (cpu_is_omap34xx()) {
3498 cpu_mask = RATE_IN_343X;
3499 cpu_clkflg |= CK_343X; 3417 cpu_clkflg |= CK_343X;
3500 3418
3501 /* 3419 /*
@@ -3506,10 +3424,17 @@ int __init omap3xxx_clk_init(void)
3506 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 3424 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3507 cpu_clkflg |= CK_3430ES1; 3425 cpu_clkflg |= CK_3430ES1;
3508 } else { 3426 } else {
3509 cpu_mask |= RATE_IN_3430ES2; 3427 cpu_mask |= RATE_IN_3430ES2PLUS;
3510 cpu_clkflg |= CK_3430ES2; 3428 cpu_clkflg |= CK_3430ES2;
3511 } 3429 }
3430 } else if (cpu_is_omap3517()) {
3431 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3432 cpu_clkflg |= CK_3517;
3433 } else if (cpu_is_omap3505()) {
3434 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3435 cpu_clkflg |= CK_3505;
3512 } 3436 }
3437
3513 if (omap3_has_192mhz_clk()) 3438 if (omap3_has_192mhz_clk())
3514 omap_96m_alwon_fck = omap_96m_alwon_fck_3630; 3439 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3515 3440
@@ -3520,14 +3445,7 @@ int __init omap3xxx_clk_init(void)
3520 /* 3445 /*
3521 * XXX This type of dynamic rewriting of the clock tree is 3446 * XXX This type of dynamic rewriting of the clock tree is
3522 * deprecated and should be revised soon. 3447 * deprecated and should be revised soon.
3523 */ 3448 *
3524 dpll4_m2_ck = dpll4_m2_ck_3630;
3525 dpll4_m3_ck = dpll4_m3_ck_3630;
3526 dpll4_m4_ck = dpll4_m4_ck_3630;
3527 dpll4_m5_ck = dpll4_m5_ck_3630;
3528 dpll4_m6_ck = dpll4_m6_ck_3630;
3529
3530 /*
3531 * For 3630: override clkops_omap2_dflt_wait for the 3449 * For 3630: override clkops_omap2_dflt_wait for the
3532 * clocks affected from PWRDN reset Limitation 3450 * clocks affected from PWRDN reset Limitation
3533 */ 3451 */
@@ -3543,18 +3461,12 @@ int __init omap3xxx_clk_init(void)
3543 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; 3461 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3544 dpll4_m6x2_ck.ops = 3462 dpll4_m6x2_ck.ops =
3545 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; 3463 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3546 } else {
3547 /*
3548 * XXX This type of dynamic rewriting of the clock tree is
3549 * deprecated and should be revised soon.
3550 */
3551 dpll4_m2_ck = dpll4_m2_ck_34xx;
3552 dpll4_m3_ck = dpll4_m3_ck_34xx;
3553 dpll4_m4_ck = dpll4_m4_ck_34xx;
3554 dpll4_m5_ck = dpll4_m5_ck_34xx;
3555 dpll4_m6_ck = dpll4_m6_ck_34xx;
3556 } 3464 }
3557 3465
3466 /*
3467 * XXX This type of dynamic rewriting of the clock tree is
3468 * deprecated and should be revised soon.
3469 */
3558 if (cpu_is_omap3630()) 3470 if (cpu_is_omap3630())
3559 dpll4_dd = dpll4_dd_3630; 3471 dpll4_dd = dpll4_dd_3630;
3560 else 3472 else
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 13:33:20 -0400