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Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c100
1 files changed, 30 insertions, 70 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 1efdec236ae8..83bed9ad3017 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -93,18 +93,6 @@ static struct clk virt_16_8m_ck = {
93 .rate = 16800000, 93 .rate = 16800000,
94}; 94};
95 95
96static struct clk virt_19_2m_ck = {
97 .name = "virt_19_2m_ck",
98 .ops = &clkops_null,
99 .rate = 19200000,
100};
101
102static struct clk virt_26m_ck = {
103 .name = "virt_26m_ck",
104 .ops = &clkops_null,
105 .rate = 26000000,
106};
107
108static struct clk virt_38_4m_ck = { 96static struct clk virt_38_4m_ck = {
109 .name = "virt_38_4m_ck", 97 .name = "virt_38_4m_ck",
110 .ops = &clkops_null, 98 .ops = &clkops_null,
@@ -145,8 +133,8 @@ static const struct clksel osc_sys_clksel[] = {
145 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, 133 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
146 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, 134 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
147 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, 135 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
148 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, 136 { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
149 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, 137 { .parent = &virt_26000000_ck, .rates = osc_sys_26m_rates },
150 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, 138 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
151 { .parent = NULL }, 139 { .parent = NULL },
152}; 140};
@@ -2490,13 +2478,13 @@ static struct clk uart4_fck = {
2490}; 2478};
2491 2479
2492static struct clk uart4_fck_am35xx = { 2480static struct clk uart4_fck_am35xx = {
2493 .name = "uart4_fck", 2481 .name = "uart4_fck",
2494 .ops = &clkops_omap2_dflt_wait, 2482 .ops = &clkops_omap2_dflt_wait,
2495 .parent = &per_48m_fck, 2483 .parent = &core_48m_fck,
2496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2497 .enable_bit = OMAP3430_EN_UART4_SHIFT, 2485 .enable_bit = AM35XX_EN_UART4_SHIFT,
2498 .clkdm_name = "core_l4_clkdm", 2486 .clkdm_name = "core_l4_clkdm",
2499 .recalc = &followparent_recalc, 2487 .recalc = &followparent_recalc,
2500}; 2488};
2501 2489
2502static struct clk gpt2_fck = { 2490static struct clk gpt2_fck = {
@@ -3201,8 +3189,12 @@ static struct clk vpfe_fck = {
3201}; 3189};
3202 3190
3203/* 3191/*
3204 * The UART1/2 functional clock acts as the functional 3192 * The UART1/2 functional clock acts as the functional clock for
3205 * clock for UART4. No separate fclk control available. 3193 * UART4. No separate fclk control available. XXX Well now we have a
3194 * uart4_fck that is apparently used as the UART4 functional clock,
3195 * but it also seems that uart1_fck or uart2_fck are still needed, at
3196 * least for UART4 softresets to complete. This really needs
3197 * clarification.
3206 */ 3198 */
3207static struct clk uart4_ick_am35xx = { 3199static struct clk uart4_ick_am35xx = {
3208 .name = "uart4_ick", 3200 .name = "uart4_ick",
@@ -3230,17 +3222,12 @@ static struct omap_clk omap3xxx_clks[] = {
3230 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3222 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3231 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3223 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3232 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3224 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3233 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), 3225 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3234 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), 3226 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
3235 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), 3227 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3236 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3228 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3237 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3229 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3238 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), 3230 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3239 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3240 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3241 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3242 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3243 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3244 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), 3231 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3245 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), 3232 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3246 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3233 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
@@ -3307,8 +3294,6 @@ static struct omap_clk omap3xxx_clks[] = {
3307 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3294 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3308 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3295 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3309 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3296 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3310 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3311 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3312 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3297 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3313 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3298 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3314 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), 3299 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
@@ -3391,15 +3376,15 @@ static struct omap_clk omap3xxx_clks[] = {
3391 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3376 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3392 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3377 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3393 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3378 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3394 CLK("usbhs_omap", "utmi_p1_gfclk", &dummy_ck, CK_3XXX), 3379 CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3395 CLK("usbhs_omap", "utmi_p2_gfclk", &dummy_ck, CK_3XXX), 3380 CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3396 CLK("usbhs_omap", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), 3381 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3397 CLK("usbhs_omap", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), 3382 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3398 CLK("usbhs_omap", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), 3383 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3399 CLK("usbhs_omap", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), 3384 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3400 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), 3385 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3401 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), 3386 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3402 CLK("usbhs_omap", "init_60m_fclk", &dummy_ck, CK_3XXX), 3387 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3403 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), 3388 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3404 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), 3389 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3405 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), 3390 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
@@ -3413,9 +3398,6 @@ static struct omap_clk omap3xxx_clks[] = {
3413 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), 3398 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3414 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), 3399 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3415 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), 3400 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3416 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3417 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3418 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3419 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), 3401 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3420 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3402 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3421 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3403 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
@@ -3474,38 +3456,16 @@ static struct omap_clk omap3xxx_clks[] = {
3474 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), 3456 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3475 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), 3457 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3476 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), 3458 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3477 CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX), 3459 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3478 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), 3460 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3479 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), 3461 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3480 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), 3462 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3481 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), 3463 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3482 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), 3464 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3483 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), 3465 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3484 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), 3466 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3485 CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), 3467 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3486 CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX), 3468 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3487 CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
3488 CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX),
3489 CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX),
3490 CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX),
3491 CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX),
3492 CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX),
3493 CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX),
3494 CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX),
3495 CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX),
3496 CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX),
3497 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX),
3498 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX),
3499 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX),
3500 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX),
3501 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX),
3502 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX),
3503 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX),
3504 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX),
3505 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX),
3506 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX),
3507 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX),
3508 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX),
3509}; 3469};
3510 3470
3511 3471
@@ -3523,7 +3483,7 @@ int __init omap3xxx_clk_init(void)
3523 } else if (cpu_is_ti816x()) { 3483 } else if (cpu_is_ti816x()) {
3524 cpu_mask = RATE_IN_TI816X; 3484 cpu_mask = RATE_IN_TI816X;
3525 cpu_clkflg = CK_TI816X; 3485 cpu_clkflg = CK_TI816X;
3526 } else if (cpu_is_am33xx()) { 3486 } else if (soc_is_am33xx()) {
3527 cpu_mask = RATE_IN_AM33XX; 3487 cpu_mask = RATE_IN_AM33XX;
3528 } else if (cpu_is_ti814x()) { 3488 } else if (cpu_is_ti814x()) {
3529 cpu_mask = RATE_IN_TI814X; 3489 cpu_mask = RATE_IN_TI814X;