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Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c182
1 files changed, 94 insertions, 88 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 403a4a1d3f9c..d905ecc7989a 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP3 clock data 2 * OMAP3 clock data
3 * 3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander 8 * With many device clock fixes by Kevin Hilman and Jouni Högander
@@ -291,12 +291,11 @@ static struct dpll_data dpll1_dd = {
291 .max_multiplier = OMAP3_MAX_DPLL_MULT, 291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1, 292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV, 293 .max_divider = OMAP3_MAX_DPLL_DIV,
294 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
295}; 294};
296 295
297static struct clk dpll1_ck = { 296static struct clk dpll1_ck = {
298 .name = "dpll1_ck", 297 .name = "dpll1_ck",
299 .ops = &clkops_null, 298 .ops = &clkops_omap3_noncore_dpll_ops,
300 .parent = &sys_ck, 299 .parent = &sys_ck,
301 .dpll_data = &dpll1_dd, 300 .dpll_data = &dpll1_dd,
302 .round_rate = &omap2_dpll_round_rate, 301 .round_rate = &omap2_dpll_round_rate,
@@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
364 .max_multiplier = OMAP3_MAX_DPLL_MULT, 363 .max_multiplier = OMAP3_MAX_DPLL_MULT,
365 .min_divider = 1, 364 .min_divider = 1,
366 .max_divider = OMAP3_MAX_DPLL_DIV, 365 .max_divider = OMAP3_MAX_DPLL_DIV,
367 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
368}; 366};
369 367
370static struct clk dpll2_ck = { 368static struct clk dpll2_ck = {
@@ -424,12 +422,11 @@ static struct dpll_data dpll3_dd = {
424 .max_multiplier = OMAP3_MAX_DPLL_MULT, 422 .max_multiplier = OMAP3_MAX_DPLL_MULT,
425 .min_divider = 1, 423 .min_divider = 1,
426 .max_divider = OMAP3_MAX_DPLL_DIV, 424 .max_divider = OMAP3_MAX_DPLL_DIV,
427 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
428}; 425};
429 426
430static struct clk dpll3_ck = { 427static struct clk dpll3_ck = {
431 .name = "dpll3_ck", 428 .name = "dpll3_ck",
432 .ops = &clkops_null, 429 .ops = &clkops_omap3_core_dpll_ops,
433 .parent = &sys_ck, 430 .parent = &sys_ck,
434 .dpll_data = &dpll3_dd, 431 .dpll_data = &dpll3_dd,
435 .round_rate = &omap2_dpll_round_rate, 432 .round_rate = &omap2_dpll_round_rate,
@@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
583 .max_multiplier = OMAP3_MAX_DPLL_MULT, 580 .max_multiplier = OMAP3_MAX_DPLL_MULT,
584 .min_divider = 1, 581 .min_divider = 1,
585 .max_divider = OMAP3_MAX_DPLL_DIV, 582 .max_divider = OMAP3_MAX_DPLL_DIV,
586 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
587}; 583};
588 584
589static struct dpll_data dpll4_dd_3630 __initdata = { 585static struct dpll_data dpll4_dd_3630 __initdata = {
@@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
607 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, 603 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
608 .min_divider = 1, 604 .min_divider = 1,
609 .max_divider = OMAP3_MAX_DPLL_DIV, 605 .max_divider = OMAP3_MAX_DPLL_DIV,
610 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
611 .flags = DPLL_J_TYPE 606 .flags = DPLL_J_TYPE
612}; 607};
613 608
@@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = {
939 .max_multiplier = OMAP3_MAX_DPLL_MULT, 934 .max_multiplier = OMAP3_MAX_DPLL_MULT,
940 .min_divider = 1, 935 .min_divider = 1,
941 .max_divider = OMAP3_MAX_DPLL_DIV, 936 .max_divider = OMAP3_MAX_DPLL_DIV,
942 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
943}; 937};
944 938
945static struct clk dpll5_ck = { 939static struct clk dpll5_ck = {
@@ -1205,7 +1199,10 @@ static const struct clksel gfx_l3_clksel[] = {
1205 { .parent = NULL } 1199 { .parent = NULL }
1206}; 1200};
1207 1201
1208/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ 1202/*
1203 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1204 * This interface clock does not have a CM_AUTOIDLE bit
1205 */
1209static struct clk gfx_l3_ck = { 1206static struct clk gfx_l3_ck = {
1210 .name = "gfx_l3_ck", 1207 .name = "gfx_l3_ck",
1211 .ops = &clkops_omap2_dflt_wait, 1208 .ops = &clkops_omap2_dflt_wait,
@@ -1304,6 +1301,7 @@ static struct clk sgx_fck = {
1304 .round_rate = &omap2_clksel_round_rate 1301 .round_rate = &omap2_clksel_round_rate
1305}; 1302};
1306 1303
1304/* This interface clock does not have a CM_AUTOIDLE bit */
1307static struct clk sgx_ick = { 1305static struct clk sgx_ick = {
1308 .name = "sgx_ick", 1306 .name = "sgx_ick",
1309 .ops = &clkops_omap2_dflt_wait, 1307 .ops = &clkops_omap2_dflt_wait,
@@ -1328,7 +1326,7 @@ static struct clk d2d_26m_fck = {
1328 1326
1329static struct clk modem_fck = { 1327static struct clk modem_fck = {
1330 .name = "modem_fck", 1328 .name = "modem_fck",
1331 .ops = &clkops_omap2_dflt_wait, 1329 .ops = &clkops_omap2_mdmclk_dflt_wait,
1332 .parent = &sys_ck, 1330 .parent = &sys_ck,
1333 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1334 .enable_bit = OMAP3430_EN_MODEM_SHIFT, 1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
@@ -1338,7 +1336,7 @@ static struct clk modem_fck = {
1338 1336
1339static struct clk sad2d_ick = { 1337static struct clk sad2d_ick = {
1340 .name = "sad2d_ick", 1338 .name = "sad2d_ick",
1341 .ops = &clkops_omap2_dflt_wait, 1339 .ops = &clkops_omap2_iclk_dflt_wait,
1342 .parent = &l3_ick, 1340 .parent = &l3_ick,
1343 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1344 .enable_bit = OMAP3430_EN_SAD2D_SHIFT, 1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
@@ -1348,7 +1346,7 @@ static struct clk sad2d_ick = {
1348 1346
1349static struct clk mad2d_ick = { 1347static struct clk mad2d_ick = {
1350 .name = "mad2d_ick", 1348 .name = "mad2d_ick",
1351 .ops = &clkops_omap2_dflt_wait, 1349 .ops = &clkops_omap2_iclk_dflt_wait,
1352 .parent = &l3_ick, 1350 .parent = &l3_ick,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1354 .enable_bit = OMAP3430_EN_MAD2D_SHIFT, 1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
@@ -1718,7 +1716,7 @@ static struct clk core_l3_ick = {
1718 1716
1719static struct clk hsotgusb_ick_3430es1 = { 1717static struct clk hsotgusb_ick_3430es1 = {
1720 .name = "hsotgusb_ick", 1718 .name = "hsotgusb_ick",
1721 .ops = &clkops_omap2_dflt, 1719 .ops = &clkops_omap2_iclk_dflt,
1722 .parent = &core_l3_ick, 1720 .parent = &core_l3_ick,
1723 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1724 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1722 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1728,7 +1726,7 @@ static struct clk hsotgusb_ick_3430es1 = {
1728 1726
1729static struct clk hsotgusb_ick_3430es2 = { 1727static struct clk hsotgusb_ick_3430es2 = {
1730 .name = "hsotgusb_ick", 1728 .name = "hsotgusb_ick",
1731 .ops = &clkops_omap3430es2_hsotgusb_wait, 1729 .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
1732 .parent = &core_l3_ick, 1730 .parent = &core_l3_ick,
1733 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1734 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1732 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1736,6 +1734,7 @@ static struct clk hsotgusb_ick_3430es2 = {
1736 .recalc = &followparent_recalc, 1734 .recalc = &followparent_recalc,
1737}; 1735};
1738 1736
1737/* This interface clock does not have a CM_AUTOIDLE bit */
1739static struct clk sdrc_ick = { 1738static struct clk sdrc_ick = {
1740 .name = "sdrc_ick", 1739 .name = "sdrc_ick",
1741 .ops = &clkops_omap2_dflt_wait, 1740 .ops = &clkops_omap2_dflt_wait,
@@ -1767,7 +1766,7 @@ static struct clk security_l3_ick = {
1767 1766
1768static struct clk pka_ick = { 1767static struct clk pka_ick = {
1769 .name = "pka_ick", 1768 .name = "pka_ick",
1770 .ops = &clkops_omap2_dflt_wait, 1769 .ops = &clkops_omap2_iclk_dflt_wait,
1771 .parent = &security_l3_ick, 1770 .parent = &security_l3_ick,
1772 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1773 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1772 .enable_bit = OMAP3430_EN_PKA_SHIFT,
@@ -1786,7 +1785,7 @@ static struct clk core_l4_ick = {
1786 1785
1787static struct clk usbtll_ick = { 1786static struct clk usbtll_ick = {
1788 .name = "usbtll_ick", 1787 .name = "usbtll_ick",
1789 .ops = &clkops_omap2_dflt_wait, 1788 .ops = &clkops_omap2_iclk_dflt_wait,
1790 .parent = &core_l4_ick, 1789 .parent = &core_l4_ick,
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1792 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1791 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1796,7 +1795,7 @@ static struct clk usbtll_ick = {
1796 1795
1797static struct clk mmchs3_ick = { 1796static struct clk mmchs3_ick = {
1798 .name = "mmchs3_ick", 1797 .name = "mmchs3_ick",
1799 .ops = &clkops_omap2_dflt_wait, 1798 .ops = &clkops_omap2_iclk_dflt_wait,
1800 .parent = &core_l4_ick, 1799 .parent = &core_l4_ick,
1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1801 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1807,7 +1806,7 @@ static struct clk mmchs3_ick = {
1807/* Intersystem Communication Registers - chassis mode only */ 1806/* Intersystem Communication Registers - chassis mode only */
1808static struct clk icr_ick = { 1807static struct clk icr_ick = {
1809 .name = "icr_ick", 1808 .name = "icr_ick",
1810 .ops = &clkops_omap2_dflt_wait, 1809 .ops = &clkops_omap2_iclk_dflt_wait,
1811 .parent = &core_l4_ick, 1810 .parent = &core_l4_ick,
1812 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1812 .enable_bit = OMAP3430_EN_ICR_SHIFT,
@@ -1817,7 +1816,7 @@ static struct clk icr_ick = {
1817 1816
1818static struct clk aes2_ick = { 1817static struct clk aes2_ick = {
1819 .name = "aes2_ick", 1818 .name = "aes2_ick",
1820 .ops = &clkops_omap2_dflt_wait, 1819 .ops = &clkops_omap2_iclk_dflt_wait,
1821 .parent = &core_l4_ick, 1820 .parent = &core_l4_ick,
1822 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1823 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1822 .enable_bit = OMAP3430_EN_AES2_SHIFT,
@@ -1827,7 +1826,7 @@ static struct clk aes2_ick = {
1827 1826
1828static struct clk sha12_ick = { 1827static struct clk sha12_ick = {
1829 .name = "sha12_ick", 1828 .name = "sha12_ick",
1830 .ops = &clkops_omap2_dflt_wait, 1829 .ops = &clkops_omap2_iclk_dflt_wait,
1831 .parent = &core_l4_ick, 1830 .parent = &core_l4_ick,
1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1832 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
@@ -1837,7 +1836,7 @@ static struct clk sha12_ick = {
1837 1836
1838static struct clk des2_ick = { 1837static struct clk des2_ick = {
1839 .name = "des2_ick", 1838 .name = "des2_ick",
1840 .ops = &clkops_omap2_dflt_wait, 1839 .ops = &clkops_omap2_iclk_dflt_wait,
1841 .parent = &core_l4_ick, 1840 .parent = &core_l4_ick,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1842 .enable_bit = OMAP3430_EN_DES2_SHIFT,
@@ -1847,7 +1846,7 @@ static struct clk des2_ick = {
1847 1846
1848static struct clk mmchs2_ick = { 1847static struct clk mmchs2_ick = {
1849 .name = "mmchs2_ick", 1848 .name = "mmchs2_ick",
1850 .ops = &clkops_omap2_dflt_wait, 1849 .ops = &clkops_omap2_iclk_dflt_wait,
1851 .parent = &core_l4_ick, 1850 .parent = &core_l4_ick,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1852 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1857,7 +1856,7 @@ static struct clk mmchs2_ick = {
1857 1856
1858static struct clk mmchs1_ick = { 1857static struct clk mmchs1_ick = {
1859 .name = "mmchs1_ick", 1858 .name = "mmchs1_ick",
1860 .ops = &clkops_omap2_dflt_wait, 1859 .ops = &clkops_omap2_iclk_dflt_wait,
1861 .parent = &core_l4_ick, 1860 .parent = &core_l4_ick,
1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1862 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -1867,7 +1866,7 @@ static struct clk mmchs1_ick = {
1867 1866
1868static struct clk mspro_ick = { 1867static struct clk mspro_ick = {
1869 .name = "mspro_ick", 1868 .name = "mspro_ick",
1870 .ops = &clkops_omap2_dflt_wait, 1869 .ops = &clkops_omap2_iclk_dflt_wait,
1871 .parent = &core_l4_ick, 1870 .parent = &core_l4_ick,
1872 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1873 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1872 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
@@ -1877,7 +1876,7 @@ static struct clk mspro_ick = {
1877 1876
1878static struct clk hdq_ick = { 1877static struct clk hdq_ick = {
1879 .name = "hdq_ick", 1878 .name = "hdq_ick",
1880 .ops = &clkops_omap2_dflt_wait, 1879 .ops = &clkops_omap2_iclk_dflt_wait,
1881 .parent = &core_l4_ick, 1880 .parent = &core_l4_ick,
1882 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1882 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
@@ -1887,7 +1886,7 @@ static struct clk hdq_ick = {
1887 1886
1888static struct clk mcspi4_ick = { 1887static struct clk mcspi4_ick = {
1889 .name = "mcspi4_ick", 1888 .name = "mcspi4_ick",
1890 .ops = &clkops_omap2_dflt_wait, 1889 .ops = &clkops_omap2_iclk_dflt_wait,
1891 .parent = &core_l4_ick, 1890 .parent = &core_l4_ick,
1892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1893 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1892 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1897,7 +1896,7 @@ static struct clk mcspi4_ick = {
1897 1896
1898static struct clk mcspi3_ick = { 1897static struct clk mcspi3_ick = {
1899 .name = "mcspi3_ick", 1898 .name = "mcspi3_ick",
1900 .ops = &clkops_omap2_dflt_wait, 1899 .ops = &clkops_omap2_iclk_dflt_wait,
1901 .parent = &core_l4_ick, 1900 .parent = &core_l4_ick,
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1902 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1907,7 +1906,7 @@ static struct clk mcspi3_ick = {
1907 1906
1908static struct clk mcspi2_ick = { 1907static struct clk mcspi2_ick = {
1909 .name = "mcspi2_ick", 1908 .name = "mcspi2_ick",
1910 .ops = &clkops_omap2_dflt_wait, 1909 .ops = &clkops_omap2_iclk_dflt_wait,
1911 .parent = &core_l4_ick, 1910 .parent = &core_l4_ick,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1912 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1917,7 +1916,7 @@ static struct clk mcspi2_ick = {
1917 1916
1918static struct clk mcspi1_ick = { 1917static struct clk mcspi1_ick = {
1919 .name = "mcspi1_ick", 1918 .name = "mcspi1_ick",
1920 .ops = &clkops_omap2_dflt_wait, 1919 .ops = &clkops_omap2_iclk_dflt_wait,
1921 .parent = &core_l4_ick, 1920 .parent = &core_l4_ick,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1922 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1927,7 +1926,7 @@ static struct clk mcspi1_ick = {
1927 1926
1928static struct clk i2c3_ick = { 1927static struct clk i2c3_ick = {
1929 .name = "i2c3_ick", 1928 .name = "i2c3_ick",
1930 .ops = &clkops_omap2_dflt_wait, 1929 .ops = &clkops_omap2_iclk_dflt_wait,
1931 .parent = &core_l4_ick, 1930 .parent = &core_l4_ick,
1932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1932 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -1937,7 +1936,7 @@ static struct clk i2c3_ick = {
1937 1936
1938static struct clk i2c2_ick = { 1937static struct clk i2c2_ick = {
1939 .name = "i2c2_ick", 1938 .name = "i2c2_ick",
1940 .ops = &clkops_omap2_dflt_wait, 1939 .ops = &clkops_omap2_iclk_dflt_wait,
1941 .parent = &core_l4_ick, 1940 .parent = &core_l4_ick,
1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1941 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1942 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -1947,7 +1946,7 @@ static struct clk i2c2_ick = {
1947 1946
1948static struct clk i2c1_ick = { 1947static struct clk i2c1_ick = {
1949 .name = "i2c1_ick", 1948 .name = "i2c1_ick",
1950 .ops = &clkops_omap2_dflt_wait, 1949 .ops = &clkops_omap2_iclk_dflt_wait,
1951 .parent = &core_l4_ick, 1950 .parent = &core_l4_ick,
1952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1951 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1952 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -1957,7 +1956,7 @@ static struct clk i2c1_ick = {
1957 1956
1958static struct clk uart2_ick = { 1957static struct clk uart2_ick = {
1959 .name = "uart2_ick", 1958 .name = "uart2_ick",
1960 .ops = &clkops_omap2_dflt_wait, 1959 .ops = &clkops_omap2_iclk_dflt_wait,
1961 .parent = &core_l4_ick, 1960 .parent = &core_l4_ick,
1962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1963 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1962 .enable_bit = OMAP3430_EN_UART2_SHIFT,
@@ -1967,7 +1966,7 @@ static struct clk uart2_ick = {
1967 1966
1968static struct clk uart1_ick = { 1967static struct clk uart1_ick = {
1969 .name = "uart1_ick", 1968 .name = "uart1_ick",
1970 .ops = &clkops_omap2_dflt_wait, 1969 .ops = &clkops_omap2_iclk_dflt_wait,
1971 .parent = &core_l4_ick, 1970 .parent = &core_l4_ick,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1971 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1972 .enable_bit = OMAP3430_EN_UART1_SHIFT,
@@ -1977,7 +1976,7 @@ static struct clk uart1_ick = {
1977 1976
1978static struct clk gpt11_ick = { 1977static struct clk gpt11_ick = {
1979 .name = "gpt11_ick", 1978 .name = "gpt11_ick",
1980 .ops = &clkops_omap2_dflt_wait, 1979 .ops = &clkops_omap2_iclk_dflt_wait,
1981 .parent = &core_l4_ick, 1980 .parent = &core_l4_ick,
1982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1982 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
@@ -1987,7 +1986,7 @@ static struct clk gpt11_ick = {
1987 1986
1988static struct clk gpt10_ick = { 1987static struct clk gpt10_ick = {
1989 .name = "gpt10_ick", 1988 .name = "gpt10_ick",
1990 .ops = &clkops_omap2_dflt_wait, 1989 .ops = &clkops_omap2_iclk_dflt_wait,
1991 .parent = &core_l4_ick, 1990 .parent = &core_l4_ick,
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1992 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
@@ -1997,7 +1996,7 @@ static struct clk gpt10_ick = {
1997 1996
1998static struct clk mcbsp5_ick = { 1997static struct clk mcbsp5_ick = {
1999 .name = "mcbsp5_ick", 1998 .name = "mcbsp5_ick",
2000 .ops = &clkops_omap2_dflt_wait, 1999 .ops = &clkops_omap2_iclk_dflt_wait,
2001 .parent = &core_l4_ick, 2000 .parent = &core_l4_ick,
2002 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 2002 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -2007,7 +2006,7 @@ static struct clk mcbsp5_ick = {
2007 2006
2008static struct clk mcbsp1_ick = { 2007static struct clk mcbsp1_ick = {
2009 .name = "mcbsp1_ick", 2008 .name = "mcbsp1_ick",
2010 .ops = &clkops_omap2_dflt_wait, 2009 .ops = &clkops_omap2_iclk_dflt_wait,
2011 .parent = &core_l4_ick, 2010 .parent = &core_l4_ick,
2012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 2012 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2017,7 +2016,7 @@ static struct clk mcbsp1_ick = {
2017 2016
2018static struct clk fac_ick = { 2017static struct clk fac_ick = {
2019 .name = "fac_ick", 2018 .name = "fac_ick",
2020 .ops = &clkops_omap2_dflt_wait, 2019 .ops = &clkops_omap2_iclk_dflt_wait,
2021 .parent = &core_l4_ick, 2020 .parent = &core_l4_ick,
2022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2021 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2023 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 2022 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
@@ -2027,7 +2026,7 @@ static struct clk fac_ick = {
2027 2026
2028static struct clk mailboxes_ick = { 2027static struct clk mailboxes_ick = {
2029 .name = "mailboxes_ick", 2028 .name = "mailboxes_ick",
2030 .ops = &clkops_omap2_dflt_wait, 2029 .ops = &clkops_omap2_iclk_dflt_wait,
2031 .parent = &core_l4_ick, 2030 .parent = &core_l4_ick,
2032 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2031 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2033 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 2032 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
@@ -2037,7 +2036,7 @@ static struct clk mailboxes_ick = {
2037 2036
2038static struct clk omapctrl_ick = { 2037static struct clk omapctrl_ick = {
2039 .name = "omapctrl_ick", 2038 .name = "omapctrl_ick",
2040 .ops = &clkops_omap2_dflt_wait, 2039 .ops = &clkops_omap2_iclk_dflt_wait,
2041 .parent = &core_l4_ick, 2040 .parent = &core_l4_ick,
2042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2041 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2043 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 2042 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
@@ -2057,7 +2056,7 @@ static struct clk ssi_l4_ick = {
2057 2056
2058static struct clk ssi_ick_3430es1 = { 2057static struct clk ssi_ick_3430es1 = {
2059 .name = "ssi_ick", 2058 .name = "ssi_ick",
2060 .ops = &clkops_omap2_dflt, 2059 .ops = &clkops_omap2_iclk_dflt,
2061 .parent = &ssi_l4_ick, 2060 .parent = &ssi_l4_ick,
2062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2063 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2062 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2067,7 +2066,7 @@ static struct clk ssi_ick_3430es1 = {
2067 2066
2068static struct clk ssi_ick_3430es2 = { 2067static struct clk ssi_ick_3430es2 = {
2069 .name = "ssi_ick", 2068 .name = "ssi_ick",
2070 .ops = &clkops_omap3430es2_ssi_wait, 2069 .ops = &clkops_omap3430es2_iclk_ssi_wait,
2071 .parent = &ssi_l4_ick, 2070 .parent = &ssi_l4_ick,
2072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2071 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2073 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2072 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2085,7 +2084,7 @@ static const struct clksel usb_l4_clksel[] = {
2085 2084
2086static struct clk usb_l4_ick = { 2085static struct clk usb_l4_ick = {
2087 .name = "usb_l4_ick", 2086 .name = "usb_l4_ick",
2088 .ops = &clkops_omap2_dflt_wait, 2087 .ops = &clkops_omap2_iclk_dflt_wait,
2089 .parent = &l4_ick, 2088 .parent = &l4_ick,
2090 .init = &omap2_init_clksel_parent, 2089 .init = &omap2_init_clksel_parent,
2091 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2107,7 +2106,7 @@ static struct clk security_l4_ick2 = {
2107 2106
2108static struct clk aes1_ick = { 2107static struct clk aes1_ick = {
2109 .name = "aes1_ick", 2108 .name = "aes1_ick",
2110 .ops = &clkops_omap2_dflt_wait, 2109 .ops = &clkops_omap2_iclk_dflt_wait,
2111 .parent = &security_l4_ick2, 2110 .parent = &security_l4_ick2,
2112 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2113 .enable_bit = OMAP3430_EN_AES1_SHIFT, 2112 .enable_bit = OMAP3430_EN_AES1_SHIFT,
@@ -2116,7 +2115,7 @@ static struct clk aes1_ick = {
2116 2115
2117static struct clk rng_ick = { 2116static struct clk rng_ick = {
2118 .name = "rng_ick", 2117 .name = "rng_ick",
2119 .ops = &clkops_omap2_dflt_wait, 2118 .ops = &clkops_omap2_iclk_dflt_wait,
2120 .parent = &security_l4_ick2, 2119 .parent = &security_l4_ick2,
2121 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2122 .enable_bit = OMAP3430_EN_RNG_SHIFT, 2121 .enable_bit = OMAP3430_EN_RNG_SHIFT,
@@ -2125,7 +2124,7 @@ static struct clk rng_ick = {
2125 2124
2126static struct clk sha11_ick = { 2125static struct clk sha11_ick = {
2127 .name = "sha11_ick", 2126 .name = "sha11_ick",
2128 .ops = &clkops_omap2_dflt_wait, 2127 .ops = &clkops_omap2_iclk_dflt_wait,
2129 .parent = &security_l4_ick2, 2128 .parent = &security_l4_ick2,
2130 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2131 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 2130 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
@@ -2134,7 +2133,7 @@ static struct clk sha11_ick = {
2134 2133
2135static struct clk des1_ick = { 2134static struct clk des1_ick = {
2136 .name = "des1_ick", 2135 .name = "des1_ick",
2137 .ops = &clkops_omap2_dflt_wait, 2136 .ops = &clkops_omap2_iclk_dflt_wait,
2138 .parent = &security_l4_ick2, 2137 .parent = &security_l4_ick2,
2139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2140 .enable_bit = OMAP3430_EN_DES1_SHIFT, 2139 .enable_bit = OMAP3430_EN_DES1_SHIFT,
@@ -2195,7 +2194,7 @@ static struct clk dss2_alwon_fck = {
2195static struct clk dss_ick_3430es1 = { 2194static struct clk dss_ick_3430es1 = {
2196 /* Handles both L3 and L4 clocks */ 2195 /* Handles both L3 and L4 clocks */
2197 .name = "dss_ick", 2196 .name = "dss_ick",
2198 .ops = &clkops_omap2_dflt, 2197 .ops = &clkops_omap2_iclk_dflt,
2199 .parent = &l4_ick, 2198 .parent = &l4_ick,
2200 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2199 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2201 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2200 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2206,7 +2205,7 @@ static struct clk dss_ick_3430es1 = {
2206static struct clk dss_ick_3430es2 = { 2205static struct clk dss_ick_3430es2 = {
2207 /* Handles both L3 and L4 clocks */ 2206 /* Handles both L3 and L4 clocks */
2208 .name = "dss_ick", 2207 .name = "dss_ick",
2209 .ops = &clkops_omap3430es2_dss_usbhost_wait, 2208 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2210 .parent = &l4_ick, 2209 .parent = &l4_ick,
2211 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2210 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2212 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2211 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2229,7 +2228,7 @@ static struct clk cam_mclk = {
2229static struct clk cam_ick = { 2228static struct clk cam_ick = {
2230 /* Handles both L3 and L4 clocks */ 2229 /* Handles both L3 and L4 clocks */
2231 .name = "cam_ick", 2230 .name = "cam_ick",
2232 .ops = &clkops_omap2_dflt, 2231 .ops = &clkops_omap2_iclk_dflt,
2233 .parent = &l4_ick, 2232 .parent = &l4_ick,
2234 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2233 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2235 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2234 .enable_bit = OMAP3430_EN_CAM_SHIFT,
@@ -2272,7 +2271,7 @@ static struct clk usbhost_48m_fck = {
2272static struct clk usbhost_ick = { 2271static struct clk usbhost_ick = {
2273 /* Handles both L3 and L4 clocks */ 2272 /* Handles both L3 and L4 clocks */
2274 .name = "usbhost_ick", 2273 .name = "usbhost_ick",
2275 .ops = &clkops_omap3430es2_dss_usbhost_wait, 2274 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2276 .parent = &l4_ick, 2275 .parent = &l4_ick,
2277 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2276 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2278 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2277 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
@@ -2372,7 +2371,7 @@ static struct clk wkup_l4_ick = {
2372/* Never specifically named in the TRM, so we have to infer a likely name */ 2371/* Never specifically named in the TRM, so we have to infer a likely name */
2373static struct clk usim_ick = { 2372static struct clk usim_ick = {
2374 .name = "usim_ick", 2373 .name = "usim_ick",
2375 .ops = &clkops_omap2_dflt_wait, 2374 .ops = &clkops_omap2_iclk_dflt_wait,
2376 .parent = &wkup_l4_ick, 2375 .parent = &wkup_l4_ick,
2377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2378 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2377 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2382,7 +2381,7 @@ static struct clk usim_ick = {
2382 2381
2383static struct clk wdt2_ick = { 2382static struct clk wdt2_ick = {
2384 .name = "wdt2_ick", 2383 .name = "wdt2_ick",
2385 .ops = &clkops_omap2_dflt_wait, 2384 .ops = &clkops_omap2_iclk_dflt_wait,
2386 .parent = &wkup_l4_ick, 2385 .parent = &wkup_l4_ick,
2387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2388 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2387 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
@@ -2392,7 +2391,7 @@ static struct clk wdt2_ick = {
2392 2391
2393static struct clk wdt1_ick = { 2392static struct clk wdt1_ick = {
2394 .name = "wdt1_ick", 2393 .name = "wdt1_ick",
2395 .ops = &clkops_omap2_dflt_wait, 2394 .ops = &clkops_omap2_iclk_dflt_wait,
2396 .parent = &wkup_l4_ick, 2395 .parent = &wkup_l4_ick,
2397 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2398 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2397 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
@@ -2402,7 +2401,7 @@ static struct clk wdt1_ick = {
2402 2401
2403static struct clk gpio1_ick = { 2402static struct clk gpio1_ick = {
2404 .name = "gpio1_ick", 2403 .name = "gpio1_ick",
2405 .ops = &clkops_omap2_dflt_wait, 2404 .ops = &clkops_omap2_iclk_dflt_wait,
2406 .parent = &wkup_l4_ick, 2405 .parent = &wkup_l4_ick,
2407 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2406 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2408 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2407 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2412,7 +2411,7 @@ static struct clk gpio1_ick = {
2412 2411
2413static struct clk omap_32ksync_ick = { 2412static struct clk omap_32ksync_ick = {
2414 .name = "omap_32ksync_ick", 2413 .name = "omap_32ksync_ick",
2415 .ops = &clkops_omap2_dflt_wait, 2414 .ops = &clkops_omap2_iclk_dflt_wait,
2416 .parent = &wkup_l4_ick, 2415 .parent = &wkup_l4_ick,
2417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2416 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2418 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2417 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
@@ -2423,7 +2422,7 @@ static struct clk omap_32ksync_ick = {
2423/* XXX This clock no longer exists in 3430 TRM rev F */ 2422/* XXX This clock no longer exists in 3430 TRM rev F */
2424static struct clk gpt12_ick = { 2423static struct clk gpt12_ick = {
2425 .name = "gpt12_ick", 2424 .name = "gpt12_ick",
2426 .ops = &clkops_omap2_dflt_wait, 2425 .ops = &clkops_omap2_iclk_dflt_wait,
2427 .parent = &wkup_l4_ick, 2426 .parent = &wkup_l4_ick,
2428 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2429 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2428 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
@@ -2433,7 +2432,7 @@ static struct clk gpt12_ick = {
2433 2432
2434static struct clk gpt1_ick = { 2433static struct clk gpt1_ick = {
2435 .name = "gpt1_ick", 2434 .name = "gpt1_ick",
2436 .ops = &clkops_omap2_dflt_wait, 2435 .ops = &clkops_omap2_iclk_dflt_wait,
2437 .parent = &wkup_l4_ick, 2436 .parent = &wkup_l4_ick,
2438 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2437 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2439 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2438 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
@@ -2663,7 +2662,7 @@ static struct clk per_l4_ick = {
2663 2662
2664static struct clk gpio6_ick = { 2663static struct clk gpio6_ick = {
2665 .name = "gpio6_ick", 2664 .name = "gpio6_ick",
2666 .ops = &clkops_omap2_dflt_wait, 2665 .ops = &clkops_omap2_iclk_dflt_wait,
2667 .parent = &per_l4_ick, 2666 .parent = &per_l4_ick,
2668 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2667 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2669 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2668 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2673,7 +2672,7 @@ static struct clk gpio6_ick = {
2673 2672
2674static struct clk gpio5_ick = { 2673static struct clk gpio5_ick = {
2675 .name = "gpio5_ick", 2674 .name = "gpio5_ick",
2676 .ops = &clkops_omap2_dflt_wait, 2675 .ops = &clkops_omap2_iclk_dflt_wait,
2677 .parent = &per_l4_ick, 2676 .parent = &per_l4_ick,
2678 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2677 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2678 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2683,7 +2682,7 @@ static struct clk gpio5_ick = {
2683 2682
2684static struct clk gpio4_ick = { 2683static struct clk gpio4_ick = {
2685 .name = "gpio4_ick", 2684 .name = "gpio4_ick",
2686 .ops = &clkops_omap2_dflt_wait, 2685 .ops = &clkops_omap2_iclk_dflt_wait,
2687 .parent = &per_l4_ick, 2686 .parent = &per_l4_ick,
2688 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2687 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2688 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2693,7 +2692,7 @@ static struct clk gpio4_ick = {
2693 2692
2694static struct clk gpio3_ick = { 2693static struct clk gpio3_ick = {
2695 .name = "gpio3_ick", 2694 .name = "gpio3_ick",
2696 .ops = &clkops_omap2_dflt_wait, 2695 .ops = &clkops_omap2_iclk_dflt_wait,
2697 .parent = &per_l4_ick, 2696 .parent = &per_l4_ick,
2698 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2697 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2698 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2703,7 +2702,7 @@ static struct clk gpio3_ick = {
2703 2702
2704static struct clk gpio2_ick = { 2703static struct clk gpio2_ick = {
2705 .name = "gpio2_ick", 2704 .name = "gpio2_ick",
2706 .ops = &clkops_omap2_dflt_wait, 2705 .ops = &clkops_omap2_iclk_dflt_wait,
2707 .parent = &per_l4_ick, 2706 .parent = &per_l4_ick,
2708 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2707 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2708 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -2713,7 +2712,7 @@ static struct clk gpio2_ick = {
2713 2712
2714static struct clk wdt3_ick = { 2713static struct clk wdt3_ick = {
2715 .name = "wdt3_ick", 2714 .name = "wdt3_ick",
2716 .ops = &clkops_omap2_dflt_wait, 2715 .ops = &clkops_omap2_iclk_dflt_wait,
2717 .parent = &per_l4_ick, 2716 .parent = &per_l4_ick,
2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2717 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2718 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
@@ -2723,7 +2722,7 @@ static struct clk wdt3_ick = {
2723 2722
2724static struct clk uart3_ick = { 2723static struct clk uart3_ick = {
2725 .name = "uart3_ick", 2724 .name = "uart3_ick",
2726 .ops = &clkops_omap2_dflt_wait, 2725 .ops = &clkops_omap2_iclk_dflt_wait,
2727 .parent = &per_l4_ick, 2726 .parent = &per_l4_ick,
2728 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2727 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2728 .enable_bit = OMAP3430_EN_UART3_SHIFT,
@@ -2733,7 +2732,7 @@ static struct clk uart3_ick = {
2733 2732
2734static struct clk uart4_ick = { 2733static struct clk uart4_ick = {
2735 .name = "uart4_ick", 2734 .name = "uart4_ick",
2736 .ops = &clkops_omap2_dflt_wait, 2735 .ops = &clkops_omap2_iclk_dflt_wait,
2737 .parent = &per_l4_ick, 2736 .parent = &per_l4_ick,
2738 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2737 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739 .enable_bit = OMAP3630_EN_UART4_SHIFT, 2738 .enable_bit = OMAP3630_EN_UART4_SHIFT,
@@ -2743,7 +2742,7 @@ static struct clk uart4_ick = {
2743 2742
2744static struct clk gpt9_ick = { 2743static struct clk gpt9_ick = {
2745 .name = "gpt9_ick", 2744 .name = "gpt9_ick",
2746 .ops = &clkops_omap2_dflt_wait, 2745 .ops = &clkops_omap2_iclk_dflt_wait,
2747 .parent = &per_l4_ick, 2746 .parent = &per_l4_ick,
2748 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2747 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2748 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
@@ -2753,7 +2752,7 @@ static struct clk gpt9_ick = {
2753 2752
2754static struct clk gpt8_ick = { 2753static struct clk gpt8_ick = {
2755 .name = "gpt8_ick", 2754 .name = "gpt8_ick",
2756 .ops = &clkops_omap2_dflt_wait, 2755 .ops = &clkops_omap2_iclk_dflt_wait,
2757 .parent = &per_l4_ick, 2756 .parent = &per_l4_ick,
2758 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2757 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2758 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
@@ -2763,7 +2762,7 @@ static struct clk gpt8_ick = {
2763 2762
2764static struct clk gpt7_ick = { 2763static struct clk gpt7_ick = {
2765 .name = "gpt7_ick", 2764 .name = "gpt7_ick",
2766 .ops = &clkops_omap2_dflt_wait, 2765 .ops = &clkops_omap2_iclk_dflt_wait,
2767 .parent = &per_l4_ick, 2766 .parent = &per_l4_ick,
2768 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2767 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2768 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
@@ -2773,7 +2772,7 @@ static struct clk gpt7_ick = {
2773 2772
2774static struct clk gpt6_ick = { 2773static struct clk gpt6_ick = {
2775 .name = "gpt6_ick", 2774 .name = "gpt6_ick",
2776 .ops = &clkops_omap2_dflt_wait, 2775 .ops = &clkops_omap2_iclk_dflt_wait,
2777 .parent = &per_l4_ick, 2776 .parent = &per_l4_ick,
2778 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2777 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2778 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
@@ -2783,7 +2782,7 @@ static struct clk gpt6_ick = {
2783 2782
2784static struct clk gpt5_ick = { 2783static struct clk gpt5_ick = {
2785 .name = "gpt5_ick", 2784 .name = "gpt5_ick",
2786 .ops = &clkops_omap2_dflt_wait, 2785 .ops = &clkops_omap2_iclk_dflt_wait,
2787 .parent = &per_l4_ick, 2786 .parent = &per_l4_ick,
2788 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2787 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2788 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
@@ -2793,7 +2792,7 @@ static struct clk gpt5_ick = {
2793 2792
2794static struct clk gpt4_ick = { 2793static struct clk gpt4_ick = {
2795 .name = "gpt4_ick", 2794 .name = "gpt4_ick",
2796 .ops = &clkops_omap2_dflt_wait, 2795 .ops = &clkops_omap2_iclk_dflt_wait,
2797 .parent = &per_l4_ick, 2796 .parent = &per_l4_ick,
2798 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2797 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2799 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2798 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
@@ -2803,7 +2802,7 @@ static struct clk gpt4_ick = {
2803 2802
2804static struct clk gpt3_ick = { 2803static struct clk gpt3_ick = {
2805 .name = "gpt3_ick", 2804 .name = "gpt3_ick",
2806 .ops = &clkops_omap2_dflt_wait, 2805 .ops = &clkops_omap2_iclk_dflt_wait,
2807 .parent = &per_l4_ick, 2806 .parent = &per_l4_ick,
2808 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2809 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2808 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
@@ -2813,7 +2812,7 @@ static struct clk gpt3_ick = {
2813 2812
2814static struct clk gpt2_ick = { 2813static struct clk gpt2_ick = {
2815 .name = "gpt2_ick", 2814 .name = "gpt2_ick",
2816 .ops = &clkops_omap2_dflt_wait, 2815 .ops = &clkops_omap2_iclk_dflt_wait,
2817 .parent = &per_l4_ick, 2816 .parent = &per_l4_ick,
2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2817 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2818 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
@@ -2823,7 +2822,7 @@ static struct clk gpt2_ick = {
2823 2822
2824static struct clk mcbsp2_ick = { 2823static struct clk mcbsp2_ick = {
2825 .name = "mcbsp2_ick", 2824 .name = "mcbsp2_ick",
2826 .ops = &clkops_omap2_dflt_wait, 2825 .ops = &clkops_omap2_iclk_dflt_wait,
2827 .parent = &per_l4_ick, 2826 .parent = &per_l4_ick,
2828 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2827 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2829 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2828 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2833,7 +2832,7 @@ static struct clk mcbsp2_ick = {
2833 2832
2834static struct clk mcbsp3_ick = { 2833static struct clk mcbsp3_ick = {
2835 .name = "mcbsp3_ick", 2834 .name = "mcbsp3_ick",
2836 .ops = &clkops_omap2_dflt_wait, 2835 .ops = &clkops_omap2_iclk_dflt_wait,
2837 .parent = &per_l4_ick, 2836 .parent = &per_l4_ick,
2838 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2837 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2839 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2838 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2843,7 +2842,7 @@ static struct clk mcbsp3_ick = {
2843 2842
2844static struct clk mcbsp4_ick = { 2843static struct clk mcbsp4_ick = {
2845 .name = "mcbsp4_ick", 2844 .name = "mcbsp4_ick",
2846 .ops = &clkops_omap2_dflt_wait, 2845 .ops = &clkops_omap2_iclk_dflt_wait,
2847 .parent = &per_l4_ick, 2846 .parent = &per_l4_ick,
2848 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2847 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2849 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2848 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -3186,7 +3185,7 @@ static struct clk vpfe_fck = {
3186 */ 3185 */
3187static struct clk uart4_ick_am35xx = { 3186static struct clk uart4_ick_am35xx = {
3188 .name = "uart4_ick", 3187 .name = "uart4_ick",
3189 .ops = &clkops_omap2_dflt_wait, 3188 .ops = &clkops_omap2_iclk_dflt_wait,
3190 .parent = &core_l4_ick, 3189 .parent = &core_l4_ick,
3191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 3190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3192 .enable_bit = AM35XX_EN_UART4_SHIFT, 3191 .enable_bit = AM35XX_EN_UART4_SHIFT,
@@ -3290,10 +3289,10 @@ static struct omap_clk omap3xxx_clks[] = {
3290 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), 3289 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3291 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), 3290 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3292 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3291 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3293 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3292 CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3294 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), 3293 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
3295 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), 3294 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3296 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), 3295 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
3297 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), 3296 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
3298 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), 3297 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
3299 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), 3298 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
@@ -3323,13 +3322,13 @@ static struct omap_clk omap3xxx_clks[] = {
3323 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3322 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3324 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3323 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3325 CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3324 CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3326 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3325 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3327 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), 3326 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3328 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), 3327 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3329 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), 3328 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3330 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), 3329 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3331 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), 3330 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3332 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), 3331 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3333 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), 3332 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3334 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3333 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3335 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3334 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
@@ -3471,6 +3470,9 @@ int __init omap3xxx_clk_init(void)
3471 } else if (cpu_is_omap3630()) { 3470 } else if (cpu_is_omap3630()) {
3472 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); 3471 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3473 cpu_clkflg = CK_36XX; 3472 cpu_clkflg = CK_36XX;
3473 } else if (cpu_is_ti816x()) {
3474 cpu_mask = RATE_IN_TI816X;
3475 cpu_clkflg = CK_TI816X;
3474 } else if (cpu_is_omap34xx()) { 3476 } else if (cpu_is_omap34xx()) {
3475 if (omap_rev() == OMAP3430_REV_ES1_0) { 3477 if (omap_rev() == OMAP3430_REV_ES1_0) {
3476 cpu_mask = RATE_IN_3430ES1; 3478 cpu_mask = RATE_IN_3430ES1;
@@ -3535,6 +3537,9 @@ int __init omap3xxx_clk_init(void)
3535 omap2_init_clk_clkdm(c->lk.clk); 3537 omap2_init_clk_clkdm(c->lk.clk);
3536 } 3538 }
3537 3539
3540 /* Disable autoidle on all clocks; let the PM code enable it later */
3541 omap_clk_disable_autoidle_all();
3542
3538 recalculate_root_clocks(); 3543 recalculate_root_clocks();
3539 3544
3540 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 3545 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
@@ -3548,9 +3553,10 @@ int __init omap3xxx_clk_init(void)
3548 clk_enable_init_clocks(); 3553 clk_enable_init_clocks();
3549 3554
3550 /* 3555 /*
3551 * Lock DPLL5 and put it in autoidle. 3556 * Lock DPLL5 -- here only until other device init code can
3557 * handle this
3552 */ 3558 */
3553 if (omap_rev() >= OMAP3430_REV_ES2_0) 3559 if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
3554 omap3_clk_lock_dpll5(); 3560 omap3_clk_lock_dpll5();
3555 3561
3556 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ 3562 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-01 00:51:22 -0400