1 files changed, 9 insertions, 8 deletions

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index cd7819cc0c9e..fafcd32e6907 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -27,6 +27,7 @@
 #include <linux/limits.h>
 #include <linux/bitops.h>
 
+#include <mach/cpu.h>
 #include <mach/clock.h>
 #include <mach/sram.h>
 #include <asm/div64.h>
@@ -1067,17 +1068,17 @@ static int __init omap2_clk_arch_init(void)
                 return -EINVAL;
 
         /* REVISIT: not yet ready for 343x */
-#if 0
-        if (clk_set_rate(&virt_prcm_set, mpurate))
-                printk(KERN_ERR "Could not find matching MPU rate\n");
-#endif
+        if (clk_set_rate(&dpll1_ck, mpurate))
+                printk(KERN_ERR "*** Unable to set MPU rate\n");
 
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
                "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
-               (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
+               (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
+               (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
+
+        calibrate_delay();
 
         return 0;
 }
@@ -1136,7 +1137,7 @@ int __init omap2_clk_init(void)
 
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
+        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
                "%ld.%01ld/%ld/%ld MHz\n",
                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));