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-rw-r--r--arch/arm/mach-omap2/clock24xx.h535
1 files changed, 194 insertions, 341 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index ad6d98d177c5..88c5acb40fcf 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,17 +24,13 @@
24#include "cm-regbits-24xx.h" 24#include "cm-regbits-24xx.h"
25#include "sdrc.h" 25#include "sdrc.h"
26 26
27static void omap2_table_mpu_recalc(struct clk *clk); 27static unsigned long omap2_table_mpu_recalc(struct clk *clk);
28static int omap2_select_table_rate(struct clk *clk, unsigned long rate); 28static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); 29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk); 30static unsigned long omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk); 31static unsigned long omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk); 32static unsigned long omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpllcore_recalc(struct clk *clk); 33static unsigned long omap2_dpllcore_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 34static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39 35
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 36/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -623,41 +619,43 @@ static struct prcm_config rate_table[] = {
623/* Base external input clocks */ 619/* Base external input clocks */
624static struct clk func_32k_ck = { 620static struct clk func_32k_ck = {
625 .name = "func_32k_ck", 621 .name = "func_32k_ck",
622 .ops = &clkops_null,
626 .rate = 32000, 623 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 624 .flags = RATE_FIXED,
628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 625 .clkdm_name = "wkup_clkdm",
626};
627
628static struct clk secure_32k_ck = {
629 .name = "secure_32k_ck",
630 .ops = &clkops_null,
631 .rate = 32768,
632 .flags = RATE_FIXED,
629 .clkdm_name = "wkup_clkdm", 633 .clkdm_name = "wkup_clkdm",
630 .recalc = &propagate_rate,
631}; 634};
632 635
633/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ 636/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 637static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
635 .name = "osc_ck", 638 .name = "osc_ck",
636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 639 .ops = &clkops_oscck,
637 RATE_PROPAGATES,
638 .clkdm_name = "wkup_clkdm", 640 .clkdm_name = "wkup_clkdm",
639 .enable = &omap2_enable_osc_ck,
640 .disable = &omap2_disable_osc_ck,
641 .recalc = &omap2_osc_clk_recalc, 641 .recalc = &omap2_osc_clk_recalc,
642}; 642};
643 643
644/* Without modem likely 12MHz, with modem likely 13MHz */ 644/* Without modem likely 12MHz, with modem likely 13MHz */
645static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 645static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
646 .name = "sys_ck", /* ~ ref_clk also */ 646 .name = "sys_ck", /* ~ ref_clk also */
647 .ops = &clkops_null,
647 .parent = &osc_ck, 648 .parent = &osc_ck,
648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
649 ALWAYS_ENABLED | RATE_PROPAGATES,
650 .clkdm_name = "wkup_clkdm", 649 .clkdm_name = "wkup_clkdm",
651 .recalc = &omap2_sys_clk_recalc, 650 .recalc = &omap2_sys_clk_recalc,
652}; 651};
653 652
654static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ 653static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
655 .name = "alt_ck", 654 .name = "alt_ck",
655 .ops = &clkops_null,
656 .rate = 54000000, 656 .rate = 54000000,
657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 657 .flags = RATE_FIXED,
658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
659 .clkdm_name = "wkup_clkdm", 658 .clkdm_name = "wkup_clkdm",
660 .recalc = &propagate_rate,
661}; 659};
662 660
663/* 661/*
@@ -673,7 +671,12 @@ static struct dpll_data dpll_dd = {
673 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 671 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
674 .mult_mask = OMAP24XX_DPLL_MULT_MASK, 672 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
675 .div1_mask = OMAP24XX_DPLL_DIV_MASK, 673 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
674 .clk_bypass = &sys_ck,
675 .clk_ref = &sys_ck,
676 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
677 .enable_mask = OMAP24XX_EN_DPLL_MASK,
676 .max_multiplier = 1024, 678 .max_multiplier = 1024,
679 .min_divider = 1,
677 .max_divider = 16, 680 .max_divider = 16,
678 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 681 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
679}; 682};
@@ -684,10 +687,9 @@ static struct dpll_data dpll_dd = {
684 */ 687 */
685static struct clk dpll_ck = { 688static struct clk dpll_ck = {
686 .name = "dpll_ck", 689 .name = "dpll_ck",
690 .ops = &clkops_null,
687 .parent = &sys_ck, /* Can be func_32k also */ 691 .parent = &sys_ck, /* Can be func_32k also */
688 .dpll_data = &dpll_dd, 692 .dpll_data = &dpll_dd,
689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
690 RATE_PROPAGATES | ALWAYS_ENABLED,
691 .clkdm_name = "wkup_clkdm", 693 .clkdm_name = "wkup_clkdm",
692 .recalc = &omap2_dpllcore_recalc, 694 .recalc = &omap2_dpllcore_recalc,
693 .set_rate = &omap2_reprogram_dpllcore, 695 .set_rate = &omap2_reprogram_dpllcore,
@@ -695,30 +697,24 @@ static struct clk dpll_ck = {
695 697
696static struct clk apll96_ck = { 698static struct clk apll96_ck = {
697 .name = "apll96_ck", 699 .name = "apll96_ck",
700 .ops = &clkops_fixed,
698 .parent = &sys_ck, 701 .parent = &sys_ck,
699 .rate = 96000000, 702 .rate = 96000000,
700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 703 .flags = RATE_FIXED | ENABLE_ON_INIT,
701 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
702 .clkdm_name = "wkup_clkdm", 704 .clkdm_name = "wkup_clkdm",
703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 705 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 706 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
705 .enable = &omap2_clk_fixed_enable,
706 .disable = &omap2_clk_fixed_disable,
707 .recalc = &propagate_rate,
708}; 707};
709 708
710static struct clk apll54_ck = { 709static struct clk apll54_ck = {
711 .name = "apll54_ck", 710 .name = "apll54_ck",
711 .ops = &clkops_fixed,
712 .parent = &sys_ck, 712 .parent = &sys_ck,
713 .rate = 54000000, 713 .rate = 54000000,
714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 714 .flags = RATE_FIXED | ENABLE_ON_INIT,
715 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
716 .clkdm_name = "wkup_clkdm", 715 .clkdm_name = "wkup_clkdm",
717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 716 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 717 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
719 .enable = &omap2_clk_fixed_enable,
720 .disable = &omap2_clk_fixed_disable,
721 .recalc = &propagate_rate,
722}; 718};
723 719
724/* 720/*
@@ -745,9 +741,8 @@ static const struct clksel func_54m_clksel[] = {
745 741
746static struct clk func_54m_ck = { 742static struct clk func_54m_ck = {
747 .name = "func_54m_ck", 743 .name = "func_54m_ck",
744 .ops = &clkops_null,
748 .parent = &apll54_ck, /* can also be alt_clk */ 745 .parent = &apll54_ck, /* can also be alt_clk */
749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
750 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
751 .clkdm_name = "wkup_clkdm", 746 .clkdm_name = "wkup_clkdm",
752 .init = &omap2_init_clksel_parent, 747 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 748 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -758,9 +753,8 @@ static struct clk func_54m_ck = {
758 753
759static struct clk core_ck = { 754static struct clk core_ck = {
760 .name = "core_ck", 755 .name = "core_ck",
756 .ops = &clkops_null,
761 .parent = &dpll_ck, /* can also be 32k */ 757 .parent = &dpll_ck, /* can also be 32k */
762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
763 ALWAYS_ENABLED | RATE_PROPAGATES,
764 .clkdm_name = "wkup_clkdm", 758 .clkdm_name = "wkup_clkdm",
765 .recalc = &followparent_recalc, 759 .recalc = &followparent_recalc,
766}; 760};
@@ -785,9 +779,8 @@ static const struct clksel func_96m_clksel[] = {
785/* The parent of this clock is not selectable on 2420. */ 779/* The parent of this clock is not selectable on 2420. */
786static struct clk func_96m_ck = { 780static struct clk func_96m_ck = {
787 .name = "func_96m_ck", 781 .name = "func_96m_ck",
782 .ops = &clkops_null,
788 .parent = &apll96_ck, 783 .parent = &apll96_ck,
789 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
790 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
791 .clkdm_name = "wkup_clkdm", 784 .clkdm_name = "wkup_clkdm",
792 .init = &omap2_init_clksel_parent, 785 .init = &omap2_init_clksel_parent,
793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 786 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -818,9 +811,8 @@ static const struct clksel func_48m_clksel[] = {
818 811
819static struct clk func_48m_ck = { 812static struct clk func_48m_ck = {
820 .name = "func_48m_ck", 813 .name = "func_48m_ck",
814 .ops = &clkops_null,
821 .parent = &apll96_ck, /* 96M or Alt */ 815 .parent = &apll96_ck, /* 96M or Alt */
822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
823 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
824 .clkdm_name = "wkup_clkdm", 816 .clkdm_name = "wkup_clkdm",
825 .init = &omap2_init_clksel_parent, 817 .init = &omap2_init_clksel_parent,
826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 818 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -833,10 +825,9 @@ static struct clk func_48m_ck = {
833 825
834static struct clk func_12m_ck = { 826static struct clk func_12m_ck = {
835 .name = "func_12m_ck", 827 .name = "func_12m_ck",
828 .ops = &clkops_null,
836 .parent = &func_48m_ck, 829 .parent = &func_48m_ck,
837 .fixed_div = 4, 830 .fixed_div = 4,
838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
839 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
840 .clkdm_name = "wkup_clkdm", 831 .clkdm_name = "wkup_clkdm",
841 .recalc = &omap2_fixed_divisor_recalc, 832 .recalc = &omap2_fixed_divisor_recalc,
842}; 833};
@@ -844,8 +835,8 @@ static struct clk func_12m_ck = {
844/* Secure timer, only available in secure mode */ 835/* Secure timer, only available in secure mode */
845static struct clk wdt1_osc_ck = { 836static struct clk wdt1_osc_ck = {
846 .name = "ck_wdt1_osc", 837 .name = "ck_wdt1_osc",
838 .ops = &clkops_null, /* RMK: missing? */
847 .parent = &osc_ck, 839 .parent = &osc_ck,
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
849 .recalc = &followparent_recalc, 840 .recalc = &followparent_recalc,
850}; 841};
851 842
@@ -887,9 +878,8 @@ static const struct clksel common_clkout_src_clksel[] = {
887 878
888static struct clk sys_clkout_src = { 879static struct clk sys_clkout_src = {
889 .name = "sys_clkout_src", 880 .name = "sys_clkout_src",
881 .ops = &clkops_omap2_dflt,
890 .parent = &func_54m_ck, 882 .parent = &func_54m_ck,
891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
892 RATE_PROPAGATES,
893 .clkdm_name = "wkup_clkdm", 883 .clkdm_name = "wkup_clkdm",
894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 884 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, 885 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
@@ -918,9 +908,8 @@ static const struct clksel sys_clkout_clksel[] = {
918 908
919static struct clk sys_clkout = { 909static struct clk sys_clkout = {
920 .name = "sys_clkout", 910 .name = "sys_clkout",
911 .ops = &clkops_null,
921 .parent = &sys_clkout_src, 912 .parent = &sys_clkout_src,
922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
923 PARENT_CONTROLS_CLOCK,
924 .clkdm_name = "wkup_clkdm", 913 .clkdm_name = "wkup_clkdm",
925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 914 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, 915 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
@@ -933,8 +922,8 @@ static struct clk sys_clkout = {
933/* In 2430, new in 2420 ES2 */ 922/* In 2430, new in 2420 ES2 */
934static struct clk sys_clkout2_src = { 923static struct clk sys_clkout2_src = {
935 .name = "sys_clkout2_src", 924 .name = "sys_clkout2_src",
925 .ops = &clkops_omap2_dflt,
936 .parent = &func_54m_ck, 926 .parent = &func_54m_ck,
937 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
938 .clkdm_name = "wkup_clkdm", 927 .clkdm_name = "wkup_clkdm",
939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 928 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, 929 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
@@ -955,8 +944,8 @@ static const struct clksel sys_clkout2_clksel[] = {
955/* In 2430, new in 2420 ES2 */ 944/* In 2430, new in 2420 ES2 */
956static struct clk sys_clkout2 = { 945static struct clk sys_clkout2 = {
957 .name = "sys_clkout2", 946 .name = "sys_clkout2",
947 .ops = &clkops_null,
958 .parent = &sys_clkout2_src, 948 .parent = &sys_clkout2_src,
959 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
960 .clkdm_name = "wkup_clkdm", 949 .clkdm_name = "wkup_clkdm",
961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 950 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, 951 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
@@ -968,8 +957,8 @@ static struct clk sys_clkout2 = {
968 957
969static struct clk emul_ck = { 958static struct clk emul_ck = {
970 .name = "emul_ck", 959 .name = "emul_ck",
960 .ops = &clkops_omap2_dflt,
971 .parent = &func_54m_ck, 961 .parent = &func_54m_ck,
972 .flags = CLOCK_IN_OMAP242X,
973 .clkdm_name = "wkup_clkdm", 962 .clkdm_name = "wkup_clkdm",
974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, 963 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, 964 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
@@ -1003,10 +992,9 @@ static const struct clksel mpu_clksel[] = {
1003 992
1004static struct clk mpu_ck = { /* Control cpu */ 993static struct clk mpu_ck = { /* Control cpu */
1005 .name = "mpu_ck", 994 .name = "mpu_ck",
995 .ops = &clkops_null,
1006 .parent = &core_ck, 996 .parent = &core_ck,
1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 997 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1008 ALWAYS_ENABLED | DELAYED_APP |
1009 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1010 .clkdm_name = "mpu_clkdm", 998 .clkdm_name = "mpu_clkdm",
1011 .init = &omap2_init_clksel_parent, 999 .init = &omap2_init_clksel_parent,
1012 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 1000 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -1046,9 +1034,9 @@ static const struct clksel dsp_fck_clksel[] = {
1046 1034
1047static struct clk dsp_fck = { 1035static struct clk dsp_fck = {
1048 .name = "dsp_fck", 1036 .name = "dsp_fck",
1037 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &core_ck, 1038 .parent = &core_ck,
1050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1039 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1051 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1052 .clkdm_name = "dsp_clkdm", 1040 .clkdm_name = "dsp_clkdm",
1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1041 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1042 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -1076,9 +1064,9 @@ static const struct clksel dsp_irate_ick_clksel[] = {
1076/* This clock does not exist as such in the TRM. */ 1064/* This clock does not exist as such in the TRM. */
1077static struct clk dsp_irate_ick = { 1065static struct clk dsp_irate_ick = {
1078 .name = "dsp_irate_ick", 1066 .name = "dsp_irate_ick",
1067 .ops = &clkops_null,
1079 .parent = &dsp_fck, 1068 .parent = &dsp_fck,
1080 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1069 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1081 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1082 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1070 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1083 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 1071 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1084 .clksel = dsp_irate_ick_clksel, 1072 .clksel = dsp_irate_ick_clksel,
@@ -1090,8 +1078,9 @@ static struct clk dsp_irate_ick = {
1090/* 2420 only */ 1078/* 2420 only */
1091static struct clk dsp_ick = { 1079static struct clk dsp_ick = {
1092 .name = "dsp_ick", /* apparently ipi and isp */ 1080 .name = "dsp_ick", /* apparently ipi and isp */
1081 .ops = &clkops_omap2_dflt_wait,
1093 .parent = &dsp_irate_ick, 1082 .parent = &dsp_irate_ick,
1094 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, 1083 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1095 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), 1084 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1096 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ 1085 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1097}; 1086};
@@ -1099,8 +1088,9 @@ static struct clk dsp_ick = {
1099/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ 1088/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1100static struct clk iva2_1_ick = { 1089static struct clk iva2_1_ick = {
1101 .name = "iva2_1_ick", 1090 .name = "iva2_1_ick",
1091 .ops = &clkops_omap2_dflt_wait,
1102 .parent = &dsp_irate_ick, 1092 .parent = &dsp_irate_ick,
1103 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1093 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1104 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1094 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1105 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1095 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1106}; 1096};
@@ -1112,9 +1102,9 @@ static struct clk iva2_1_ick = {
1112 */ 1102 */
1113static struct clk iva1_ifck = { 1103static struct clk iva1_ifck = {
1114 .name = "iva1_ifck", 1104 .name = "iva1_ifck",
1105 .ops = &clkops_omap2_dflt_wait,
1115 .parent = &core_ck, 1106 .parent = &core_ck,
1116 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1107 .flags = CONFIG_PARTICIPANT | DELAYED_APP,
1117 RATE_PROPAGATES | DELAYED_APP,
1118 .clkdm_name = "iva1_clkdm", 1108 .clkdm_name = "iva1_clkdm",
1119 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1109 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1120 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 1110 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
@@ -1129,8 +1119,8 @@ static struct clk iva1_ifck = {
1129/* IVA1 mpu/int/i/f clocks are /2 of parent */ 1119/* IVA1 mpu/int/i/f clocks are /2 of parent */
1130static struct clk iva1_mpu_int_ifck = { 1120static struct clk iva1_mpu_int_ifck = {
1131 .name = "iva1_mpu_int_ifck", 1121 .name = "iva1_mpu_int_ifck",
1122 .ops = &clkops_omap2_dflt_wait,
1132 .parent = &iva1_ifck, 1123 .parent = &iva1_ifck,
1133 .flags = CLOCK_IN_OMAP242X,
1134 .clkdm_name = "iva1_clkdm", 1124 .clkdm_name = "iva1_clkdm",
1135 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1125 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1136 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, 1126 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
@@ -1175,10 +1165,9 @@ static const struct clksel core_l3_clksel[] = {
1175 1165
1176static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ 1166static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1177 .name = "core_l3_ck", 1167 .name = "core_l3_ck",
1168 .ops = &clkops_null,
1178 .parent = &core_ck, 1169 .parent = &core_ck,
1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1170 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1180 ALWAYS_ENABLED | DELAYED_APP |
1181 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1182 .clkdm_name = "core_l3_clkdm", 1171 .clkdm_name = "core_l3_clkdm",
1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1172 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 1173 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
@@ -1204,9 +1193,9 @@ static const struct clksel usb_l4_ick_clksel[] = {
1204/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 1193/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1205static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1194static struct clk usb_l4_ick = { /* FS-USB interface clock */
1206 .name = "usb_l4_ick", 1195 .name = "usb_l4_ick",
1196 .ops = &clkops_omap2_dflt_wait,
1207 .parent = &core_l3_ck, 1197 .parent = &core_l3_ck,
1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1198 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1209 DELAYED_APP | CONFIG_PARTICIPANT,
1210 .clkdm_name = "core_l4_clkdm", 1199 .clkdm_name = "core_l4_clkdm",
1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1212 .enable_bit = OMAP24XX_EN_USB_SHIFT, 1201 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -1238,9 +1227,9 @@ static const struct clksel l4_clksel[] = {
1238 1227
1239static struct clk l4_ck = { /* used both as an ick and fck */ 1228static struct clk l4_ck = { /* used both as an ick and fck */
1240 .name = "l4_ck", 1229 .name = "l4_ck",
1230 .ops = &clkops_null,
1241 .parent = &core_l3_ck, 1231 .parent = &core_l3_ck,
1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1232 .flags = DELAYED_APP,
1243 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1244 .clkdm_name = "core_l4_clkdm", 1233 .clkdm_name = "core_l4_clkdm",
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1234 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 1235 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
@@ -1276,9 +1265,9 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1276 1265
1277static struct clk ssi_ssr_sst_fck = { 1266static struct clk ssi_ssr_sst_fck = {
1278 .name = "ssi_fck", 1267 .name = "ssi_fck",
1268 .ops = &clkops_omap2_dflt_wait,
1279 .parent = &core_ck, 1269 .parent = &core_ck,
1280 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1270 .flags = DELAYED_APP,
1281 DELAYED_APP,
1282 .clkdm_name = "core_l3_clkdm", 1271 .clkdm_name = "core_l3_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 1273 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -1290,6 +1279,20 @@ static struct clk ssi_ssr_sst_fck = {
1290 .set_rate = &omap2_clksel_set_rate 1279 .set_rate = &omap2_clksel_set_rate
1291}; 1280};
1292 1281
1282/*
1283 * Presumably this is the same as SSI_ICLK.
1284 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1285 */
1286static struct clk ssi_l4_ick = {
1287 .name = "ssi_l4_ick",
1288 .ops = &clkops_omap2_dflt_wait,
1289 .parent = &l4_ck,
1290 .clkdm_name = "core_l4_clkdm",
1291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1292 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1293 .recalc = &followparent_recalc,
1294};
1295
1293 1296
1294/* 1297/*
1295 * GFX clock domain 1298 * GFX clock domain
@@ -1312,8 +1315,8 @@ static const struct clksel gfx_fck_clksel[] = {
1312 1315
1313static struct clk gfx_3d_fck = { 1316static struct clk gfx_3d_fck = {
1314 .name = "gfx_3d_fck", 1317 .name = "gfx_3d_fck",
1318 .ops = &clkops_omap2_dflt_wait,
1315 .parent = &core_l3_ck, 1319 .parent = &core_l3_ck,
1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1317 .clkdm_name = "gfx_clkdm", 1320 .clkdm_name = "gfx_clkdm",
1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1321 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1319 .enable_bit = OMAP24XX_EN_3D_SHIFT, 1322 .enable_bit = OMAP24XX_EN_3D_SHIFT,
@@ -1327,8 +1330,8 @@ static struct clk gfx_3d_fck = {
1327 1330
1328static struct clk gfx_2d_fck = { 1331static struct clk gfx_2d_fck = {
1329 .name = "gfx_2d_fck", 1332 .name = "gfx_2d_fck",
1333 .ops = &clkops_omap2_dflt_wait,
1330 .parent = &core_l3_ck, 1334 .parent = &core_l3_ck,
1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332 .clkdm_name = "gfx_clkdm", 1335 .clkdm_name = "gfx_clkdm",
1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1336 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334 .enable_bit = OMAP24XX_EN_2D_SHIFT, 1337 .enable_bit = OMAP24XX_EN_2D_SHIFT,
@@ -1342,8 +1345,8 @@ static struct clk gfx_2d_fck = {
1342 1345
1343static struct clk gfx_ick = { 1346static struct clk gfx_ick = {
1344 .name = "gfx_ick", /* From l3 */ 1347 .name = "gfx_ick", /* From l3 */
1348 .ops = &clkops_omap2_dflt_wait,
1345 .parent = &core_l3_ck, 1349 .parent = &core_l3_ck,
1346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1347 .clkdm_name = "gfx_clkdm", 1350 .clkdm_name = "gfx_clkdm",
1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1351 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1349 .enable_bit = OMAP_EN_GFX_SHIFT, 1352 .enable_bit = OMAP_EN_GFX_SHIFT,
@@ -1372,8 +1375,9 @@ static const struct clksel mdm_ick_clksel[] = {
1372 1375
1373static struct clk mdm_ick = { /* used both as a ick and fck */ 1376static struct clk mdm_ick = { /* used both as a ick and fck */
1374 .name = "mdm_ick", 1377 .name = "mdm_ick",
1378 .ops = &clkops_omap2_dflt_wait,
1375 .parent = &core_ck, 1379 .parent = &core_ck,
1376 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1380 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1377 .clkdm_name = "mdm_clkdm", 1381 .clkdm_name = "mdm_clkdm",
1378 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 1382 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1379 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 1383 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -1387,8 +1391,8 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
1387 1391
1388static struct clk mdm_osc_ck = { 1392static struct clk mdm_osc_ck = {
1389 .name = "mdm_osc_ck", 1393 .name = "mdm_osc_ck",
1394 .ops = &clkops_omap2_dflt_wait,
1390 .parent = &osc_ck, 1395 .parent = &osc_ck,
1391 .flags = CLOCK_IN_OMAP243X,
1392 .clkdm_name = "mdm_clkdm", 1396 .clkdm_name = "mdm_clkdm",
1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 1397 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1394 .enable_bit = OMAP2430_EN_OSC_SHIFT, 1398 .enable_bit = OMAP2430_EN_OSC_SHIFT,
@@ -1432,8 +1436,8 @@ static const struct clksel dss1_fck_clksel[] = {
1432 1436
1433static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 1437static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1434 .name = "dss_ick", 1438 .name = "dss_ick",
1439 .ops = &clkops_omap2_dflt,
1435 .parent = &l4_ck, /* really both l3 and l4 */ 1440 .parent = &l4_ck, /* really both l3 and l4 */
1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437 .clkdm_name = "dss_clkdm", 1441 .clkdm_name = "dss_clkdm",
1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1439 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1443 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1442,9 +1446,9 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1442 1446
1443static struct clk dss1_fck = { 1447static struct clk dss1_fck = {
1444 .name = "dss1_fck", 1448 .name = "dss1_fck",
1449 .ops = &clkops_omap2_dflt,
1445 .parent = &core_ck, /* Core or sys */ 1450 .parent = &core_ck, /* Core or sys */
1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1451 .flags = DELAYED_APP,
1447 DELAYED_APP,
1448 .clkdm_name = "dss_clkdm", 1452 .clkdm_name = "dss_clkdm",
1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1454 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1475,9 +1479,9 @@ static const struct clksel dss2_fck_clksel[] = {
1475 1479
1476static struct clk dss2_fck = { /* Alt clk used in power management */ 1480static struct clk dss2_fck = { /* Alt clk used in power management */
1477 .name = "dss2_fck", 1481 .name = "dss2_fck",
1482 .ops = &clkops_omap2_dflt,
1478 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1483 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1484 .flags = DELAYED_APP,
1480 DELAYED_APP,
1481 .clkdm_name = "dss_clkdm", 1485 .clkdm_name = "dss_clkdm",
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1486 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 1487 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
@@ -1490,8 +1494,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1490 1494
1491static struct clk dss_54m_fck = { /* Alt clk used in power management */ 1495static struct clk dss_54m_fck = { /* Alt clk used in power management */
1492 .name = "dss_54m_fck", /* 54m tv clk */ 1496 .name = "dss_54m_fck", /* 54m tv clk */
1497 .ops = &clkops_omap2_dflt_wait,
1493 .parent = &func_54m_ck, 1498 .parent = &func_54m_ck,
1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495 .clkdm_name = "dss_clkdm", 1499 .clkdm_name = "dss_clkdm",
1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1500 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497 .enable_bit = OMAP24XX_EN_TV_SHIFT, 1501 .enable_bit = OMAP24XX_EN_TV_SHIFT,
@@ -1518,8 +1522,8 @@ static const struct clksel omap24xx_gpt_clksel[] = {
1518 1522
1519static struct clk gpt1_ick = { 1523static struct clk gpt1_ick = {
1520 .name = "gpt1_ick", 1524 .name = "gpt1_ick",
1525 .ops = &clkops_omap2_dflt_wait,
1521 .parent = &l4_ck, 1526 .parent = &l4_ck,
1522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523 .clkdm_name = "core_l4_clkdm", 1527 .clkdm_name = "core_l4_clkdm",
1524 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1528 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1525 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1529 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1528,8 +1532,8 @@ static struct clk gpt1_ick = {
1528 1532
1529static struct clk gpt1_fck = { 1533static struct clk gpt1_fck = {
1530 .name = "gpt1_fck", 1534 .name = "gpt1_fck",
1535 .ops = &clkops_omap2_dflt_wait,
1531 .parent = &func_32k_ck, 1536 .parent = &func_32k_ck,
1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .clkdm_name = "core_l4_clkdm", 1537 .clkdm_name = "core_l4_clkdm",
1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 1538 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1535 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1539 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1544,8 +1548,8 @@ static struct clk gpt1_fck = {
1544 1548
1545static struct clk gpt2_ick = { 1549static struct clk gpt2_ick = {
1546 .name = "gpt2_ick", 1550 .name = "gpt2_ick",
1551 .ops = &clkops_omap2_dflt_wait,
1547 .parent = &l4_ck, 1552 .parent = &l4_ck,
1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549 .clkdm_name = "core_l4_clkdm", 1553 .clkdm_name = "core_l4_clkdm",
1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1551 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1555 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1554,8 +1558,8 @@ static struct clk gpt2_ick = {
1554 1558
1555static struct clk gpt2_fck = { 1559static struct clk gpt2_fck = {
1556 .name = "gpt2_fck", 1560 .name = "gpt2_fck",
1561 .ops = &clkops_omap2_dflt_wait,
1557 .parent = &func_32k_ck, 1562 .parent = &func_32k_ck,
1558 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559 .clkdm_name = "core_l4_clkdm", 1563 .clkdm_name = "core_l4_clkdm",
1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1565 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1568,8 +1572,8 @@ static struct clk gpt2_fck = {
1568 1572
1569static struct clk gpt3_ick = { 1573static struct clk gpt3_ick = {
1570 .name = "gpt3_ick", 1574 .name = "gpt3_ick",
1575 .ops = &clkops_omap2_dflt_wait,
1571 .parent = &l4_ck, 1576 .parent = &l4_ck,
1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573 .clkdm_name = "core_l4_clkdm", 1577 .clkdm_name = "core_l4_clkdm",
1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1575 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1579 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1578,8 +1582,8 @@ static struct clk gpt3_ick = {
1578 1582
1579static struct clk gpt3_fck = { 1583static struct clk gpt3_fck = {
1580 .name = "gpt3_fck", 1584 .name = "gpt3_fck",
1585 .ops = &clkops_omap2_dflt_wait,
1581 .parent = &func_32k_ck, 1586 .parent = &func_32k_ck,
1582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1583 .clkdm_name = "core_l4_clkdm", 1587 .clkdm_name = "core_l4_clkdm",
1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1585 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1589 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1592,8 +1596,8 @@ static struct clk gpt3_fck = {
1592 1596
1593static struct clk gpt4_ick = { 1597static struct clk gpt4_ick = {
1594 .name = "gpt4_ick", 1598 .name = "gpt4_ick",
1599 .ops = &clkops_omap2_dflt_wait,
1595 .parent = &l4_ck, 1600 .parent = &l4_ck,
1596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597 .clkdm_name = "core_l4_clkdm", 1601 .clkdm_name = "core_l4_clkdm",
1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1599 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1603 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1602,8 +1606,8 @@ static struct clk gpt4_ick = {
1602 1606
1603static struct clk gpt4_fck = { 1607static struct clk gpt4_fck = {
1604 .name = "gpt4_fck", 1608 .name = "gpt4_fck",
1609 .ops = &clkops_omap2_dflt_wait,
1605 .parent = &func_32k_ck, 1610 .parent = &func_32k_ck,
1606 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607 .clkdm_name = "core_l4_clkdm", 1611 .clkdm_name = "core_l4_clkdm",
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1613 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1616,8 +1620,8 @@ static struct clk gpt4_fck = {
1616 1620
1617static struct clk gpt5_ick = { 1621static struct clk gpt5_ick = {
1618 .name = "gpt5_ick", 1622 .name = "gpt5_ick",
1623 .ops = &clkops_omap2_dflt_wait,
1619 .parent = &l4_ck, 1624 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .clkdm_name = "core_l4_clkdm", 1625 .clkdm_name = "core_l4_clkdm",
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1626 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1627 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1626,8 +1630,8 @@ static struct clk gpt5_ick = {
1626 1630
1627static struct clk gpt5_fck = { 1631static struct clk gpt5_fck = {
1628 .name = "gpt5_fck", 1632 .name = "gpt5_fck",
1633 .ops = &clkops_omap2_dflt_wait,
1629 .parent = &func_32k_ck, 1634 .parent = &func_32k_ck,
1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631 .clkdm_name = "core_l4_clkdm", 1635 .clkdm_name = "core_l4_clkdm",
1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1636 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1637 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1640,8 +1644,8 @@ static struct clk gpt5_fck = {
1640 1644
1641static struct clk gpt6_ick = { 1645static struct clk gpt6_ick = {
1642 .name = "gpt6_ick", 1646 .name = "gpt6_ick",
1647 .ops = &clkops_omap2_dflt_wait,
1643 .parent = &l4_ck, 1648 .parent = &l4_ck,
1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645 .clkdm_name = "core_l4_clkdm", 1649 .clkdm_name = "core_l4_clkdm",
1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1647 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1651 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1650,8 +1654,8 @@ static struct clk gpt6_ick = {
1650 1654
1651static struct clk gpt6_fck = { 1655static struct clk gpt6_fck = {
1652 .name = "gpt6_fck", 1656 .name = "gpt6_fck",
1657 .ops = &clkops_omap2_dflt_wait,
1653 .parent = &func_32k_ck, 1658 .parent = &func_32k_ck,
1654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655 .clkdm_name = "core_l4_clkdm", 1659 .clkdm_name = "core_l4_clkdm",
1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1661 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1664,8 +1668,8 @@ static struct clk gpt6_fck = {
1664 1668
1665static struct clk gpt7_ick = { 1669static struct clk gpt7_ick = {
1666 .name = "gpt7_ick", 1670 .name = "gpt7_ick",
1671 .ops = &clkops_omap2_dflt_wait,
1667 .parent = &l4_ck, 1672 .parent = &l4_ck,
1668 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1673 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1674 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1671 .recalc = &followparent_recalc, 1675 .recalc = &followparent_recalc,
@@ -1673,8 +1677,8 @@ static struct clk gpt7_ick = {
1673 1677
1674static struct clk gpt7_fck = { 1678static struct clk gpt7_fck = {
1675 .name = "gpt7_fck", 1679 .name = "gpt7_fck",
1680 .ops = &clkops_omap2_dflt_wait,
1676 .parent = &func_32k_ck, 1681 .parent = &func_32k_ck,
1677 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678 .clkdm_name = "core_l4_clkdm", 1682 .clkdm_name = "core_l4_clkdm",
1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1683 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1684 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
@@ -1687,8 +1691,8 @@ static struct clk gpt7_fck = {
1687 1691
1688static struct clk gpt8_ick = { 1692static struct clk gpt8_ick = {
1689 .name = "gpt8_ick", 1693 .name = "gpt8_ick",
1694 .ops = &clkops_omap2_dflt_wait,
1690 .parent = &l4_ck, 1695 .parent = &l4_ck,
1691 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692 .clkdm_name = "core_l4_clkdm", 1696 .clkdm_name = "core_l4_clkdm",
1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1694 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1698 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1697,8 +1701,8 @@ static struct clk gpt8_ick = {
1697 1701
1698static struct clk gpt8_fck = { 1702static struct clk gpt8_fck = {
1699 .name = "gpt8_fck", 1703 .name = "gpt8_fck",
1704 .ops = &clkops_omap2_dflt_wait,
1700 .parent = &func_32k_ck, 1705 .parent = &func_32k_ck,
1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .clkdm_name = "core_l4_clkdm", 1706 .clkdm_name = "core_l4_clkdm",
1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1707 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1708 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1711,8 +1715,8 @@ static struct clk gpt8_fck = {
1711 1715
1712static struct clk gpt9_ick = { 1716static struct clk gpt9_ick = {
1713 .name = "gpt9_ick", 1717 .name = "gpt9_ick",
1718 .ops = &clkops_omap2_dflt_wait,
1714 .parent = &l4_ck, 1719 .parent = &l4_ck,
1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716 .clkdm_name = "core_l4_clkdm", 1720 .clkdm_name = "core_l4_clkdm",
1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1722 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1721,8 +1725,8 @@ static struct clk gpt9_ick = {
1721 1725
1722static struct clk gpt9_fck = { 1726static struct clk gpt9_fck = {
1723 .name = "gpt9_fck", 1727 .name = "gpt9_fck",
1728 .ops = &clkops_omap2_dflt_wait,
1724 .parent = &func_32k_ck, 1729 .parent = &func_32k_ck,
1725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1726 .clkdm_name = "core_l4_clkdm", 1730 .clkdm_name = "core_l4_clkdm",
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1732 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1735,8 +1739,8 @@ static struct clk gpt9_fck = {
1735 1739
1736static struct clk gpt10_ick = { 1740static struct clk gpt10_ick = {
1737 .name = "gpt10_ick", 1741 .name = "gpt10_ick",
1742 .ops = &clkops_omap2_dflt_wait,
1738 .parent = &l4_ck, 1743 .parent = &l4_ck,
1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740 .clkdm_name = "core_l4_clkdm", 1744 .clkdm_name = "core_l4_clkdm",
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1745 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1746 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1745,8 +1749,8 @@ static struct clk gpt10_ick = {
1745 1749
1746static struct clk gpt10_fck = { 1750static struct clk gpt10_fck = {
1747 .name = "gpt10_fck", 1751 .name = "gpt10_fck",
1752 .ops = &clkops_omap2_dflt_wait,
1748 .parent = &func_32k_ck, 1753 .parent = &func_32k_ck,
1749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750 .clkdm_name = "core_l4_clkdm", 1754 .clkdm_name = "core_l4_clkdm",
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1752 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1756 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1759,8 +1763,8 @@ static struct clk gpt10_fck = {
1759 1763
1760static struct clk gpt11_ick = { 1764static struct clk gpt11_ick = {
1761 .name = "gpt11_ick", 1765 .name = "gpt11_ick",
1766 .ops = &clkops_omap2_dflt_wait,
1762 .parent = &l4_ck, 1767 .parent = &l4_ck,
1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764 .clkdm_name = "core_l4_clkdm", 1768 .clkdm_name = "core_l4_clkdm",
1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1770 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1769,8 +1773,8 @@ static struct clk gpt11_ick = {
1769 1773
1770static struct clk gpt11_fck = { 1774static struct clk gpt11_fck = {
1771 .name = "gpt11_fck", 1775 .name = "gpt11_fck",
1776 .ops = &clkops_omap2_dflt_wait,
1772 .parent = &func_32k_ck, 1777 .parent = &func_32k_ck,
1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774 .clkdm_name = "core_l4_clkdm", 1778 .clkdm_name = "core_l4_clkdm",
1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1776 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1780 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1783,8 +1787,8 @@ static struct clk gpt11_fck = {
1783 1787
1784static struct clk gpt12_ick = { 1788static struct clk gpt12_ick = {
1785 .name = "gpt12_ick", 1789 .name = "gpt12_ick",
1790 .ops = &clkops_omap2_dflt_wait,
1786 .parent = &l4_ck, 1791 .parent = &l4_ck,
1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788 .clkdm_name = "core_l4_clkdm", 1792 .clkdm_name = "core_l4_clkdm",
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1794 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1793,8 +1797,8 @@ static struct clk gpt12_ick = {
1793 1797
1794static struct clk gpt12_fck = { 1798static struct clk gpt12_fck = {
1795 .name = "gpt12_fck", 1799 .name = "gpt12_fck",
1796 .parent = &func_32k_ck, 1800 .ops = &clkops_omap2_dflt_wait,
1797 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1801 .parent = &secure_32k_ck,
1798 .clkdm_name = "core_l4_clkdm", 1802 .clkdm_name = "core_l4_clkdm",
1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1800 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1804 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1807,9 +1811,9 @@ static struct clk gpt12_fck = {
1807 1811
1808static struct clk mcbsp1_ick = { 1812static struct clk mcbsp1_ick = {
1809 .name = "mcbsp_ick", 1813 .name = "mcbsp_ick",
1814 .ops = &clkops_omap2_dflt_wait,
1810 .id = 1, 1815 .id = 1,
1811 .parent = &l4_ck, 1816 .parent = &l4_ck,
1812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1813 .clkdm_name = "core_l4_clkdm", 1817 .clkdm_name = "core_l4_clkdm",
1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1818 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1819 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1818,9 +1822,9 @@ static struct clk mcbsp1_ick = {
1818 1822
1819static struct clk mcbsp1_fck = { 1823static struct clk mcbsp1_fck = {
1820 .name = "mcbsp_fck", 1824 .name = "mcbsp_fck",
1825 .ops = &clkops_omap2_dflt_wait,
1821 .id = 1, 1826 .id = 1,
1822 .parent = &func_96m_ck, 1827 .parent = &func_96m_ck,
1823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1824 .clkdm_name = "core_l4_clkdm", 1828 .clkdm_name = "core_l4_clkdm",
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1826 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1830 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1829,9 +1833,9 @@ static struct clk mcbsp1_fck = {
1829 1833
1830static struct clk mcbsp2_ick = { 1834static struct clk mcbsp2_ick = {
1831 .name = "mcbsp_ick", 1835 .name = "mcbsp_ick",
1836 .ops = &clkops_omap2_dflt_wait,
1832 .id = 2, 1837 .id = 2,
1833 .parent = &l4_ck, 1838 .parent = &l4_ck,
1834 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1835 .clkdm_name = "core_l4_clkdm", 1839 .clkdm_name = "core_l4_clkdm",
1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1840 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1841 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1840,9 +1844,9 @@ static struct clk mcbsp2_ick = {
1840 1844
1841static struct clk mcbsp2_fck = { 1845static struct clk mcbsp2_fck = {
1842 .name = "mcbsp_fck", 1846 .name = "mcbsp_fck",
1847 .ops = &clkops_omap2_dflt_wait,
1843 .id = 2, 1848 .id = 2,
1844 .parent = &func_96m_ck, 1849 .parent = &func_96m_ck,
1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846 .clkdm_name = "core_l4_clkdm", 1850 .clkdm_name = "core_l4_clkdm",
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1848 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1852 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1851,9 +1855,9 @@ static struct clk mcbsp2_fck = {
1851 1855
1852static struct clk mcbsp3_ick = { 1856static struct clk mcbsp3_ick = {
1853 .name = "mcbsp_ick", 1857 .name = "mcbsp_ick",
1858 .ops = &clkops_omap2_dflt_wait,
1854 .id = 3, 1859 .id = 3,
1855 .parent = &l4_ck, 1860 .parent = &l4_ck,
1856 .flags = CLOCK_IN_OMAP243X,
1857 .clkdm_name = "core_l4_clkdm", 1861 .clkdm_name = "core_l4_clkdm",
1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1859 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1863 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1862,9 +1866,9 @@ static struct clk mcbsp3_ick = {
1862 1866
1863static struct clk mcbsp3_fck = { 1867static struct clk mcbsp3_fck = {
1864 .name = "mcbsp_fck", 1868 .name = "mcbsp_fck",
1869 .ops = &clkops_omap2_dflt_wait,
1865 .id = 3, 1870 .id = 3,
1866 .parent = &func_96m_ck, 1871 .parent = &func_96m_ck,
1867 .flags = CLOCK_IN_OMAP243X,
1868 .clkdm_name = "core_l4_clkdm", 1872 .clkdm_name = "core_l4_clkdm",
1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1873 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1870 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1874 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1873,9 +1877,9 @@ static struct clk mcbsp3_fck = {
1873 1877
1874static struct clk mcbsp4_ick = { 1878static struct clk mcbsp4_ick = {
1875 .name = "mcbsp_ick", 1879 .name = "mcbsp_ick",
1880 .ops = &clkops_omap2_dflt_wait,
1876 .id = 4, 1881 .id = 4,
1877 .parent = &l4_ck, 1882 .parent = &l4_ck,
1878 .flags = CLOCK_IN_OMAP243X,
1879 .clkdm_name = "core_l4_clkdm", 1883 .clkdm_name = "core_l4_clkdm",
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1881 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1885 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1884,9 +1888,9 @@ static struct clk mcbsp4_ick = {
1884 1888
1885static struct clk mcbsp4_fck = { 1889static struct clk mcbsp4_fck = {
1886 .name = "mcbsp_fck", 1890 .name = "mcbsp_fck",
1891 .ops = &clkops_omap2_dflt_wait,
1887 .id = 4, 1892 .id = 4,
1888 .parent = &func_96m_ck, 1893 .parent = &func_96m_ck,
1889 .flags = CLOCK_IN_OMAP243X,
1890 .clkdm_name = "core_l4_clkdm", 1894 .clkdm_name = "core_l4_clkdm",
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1892 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1896 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1895,9 +1899,9 @@ static struct clk mcbsp4_fck = {
1895 1899
1896static struct clk mcbsp5_ick = { 1900static struct clk mcbsp5_ick = {
1897 .name = "mcbsp_ick", 1901 .name = "mcbsp_ick",
1902 .ops = &clkops_omap2_dflt_wait,
1898 .id = 5, 1903 .id = 5,
1899 .parent = &l4_ck, 1904 .parent = &l4_ck,
1900 .flags = CLOCK_IN_OMAP243X,
1901 .clkdm_name = "core_l4_clkdm", 1905 .clkdm_name = "core_l4_clkdm",
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1903 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1907 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1906,9 +1910,9 @@ static struct clk mcbsp5_ick = {
1906 1910
1907static struct clk mcbsp5_fck = { 1911static struct clk mcbsp5_fck = {
1908 .name = "mcbsp_fck", 1912 .name = "mcbsp_fck",
1913 .ops = &clkops_omap2_dflt_wait,
1909 .id = 5, 1914 .id = 5,
1910 .parent = &func_96m_ck, 1915 .parent = &func_96m_ck,
1911 .flags = CLOCK_IN_OMAP243X,
1912 .clkdm_name = "core_l4_clkdm", 1916 .clkdm_name = "core_l4_clkdm",
1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1914 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1918 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1917,10 +1921,10 @@ static struct clk mcbsp5_fck = {
1917 1921
1918static struct clk mcspi1_ick = { 1922static struct clk mcspi1_ick = {
1919 .name = "mcspi_ick", 1923 .name = "mcspi_ick",
1924 .ops = &clkops_omap2_dflt_wait,
1920 .id = 1, 1925 .id = 1,
1921 .parent = &l4_ck, 1926 .parent = &l4_ck,
1922 .clkdm_name = "core_l4_clkdm", 1927 .clkdm_name = "core_l4_clkdm",
1923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1929 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1926 .recalc = &followparent_recalc, 1930 .recalc = &followparent_recalc,
@@ -1928,9 +1932,9 @@ static struct clk mcspi1_ick = {
1928 1932
1929static struct clk mcspi1_fck = { 1933static struct clk mcspi1_fck = {
1930 .name = "mcspi_fck", 1934 .name = "mcspi_fck",
1935 .ops = &clkops_omap2_dflt_wait,
1931 .id = 1, 1936 .id = 1,
1932 .parent = &func_48m_ck, 1937 .parent = &func_48m_ck,
1933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1934 .clkdm_name = "core_l4_clkdm", 1938 .clkdm_name = "core_l4_clkdm",
1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1940 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -1939,9 +1943,9 @@ static struct clk mcspi1_fck = {
1939 1943
1940static struct clk mcspi2_ick = { 1944static struct clk mcspi2_ick = {
1941 .name = "mcspi_ick", 1945 .name = "mcspi_ick",
1946 .ops = &clkops_omap2_dflt_wait,
1942 .id = 2, 1947 .id = 2,
1943 .parent = &l4_ck, 1948 .parent = &l4_ck,
1944 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1945 .clkdm_name = "core_l4_clkdm", 1949 .clkdm_name = "core_l4_clkdm",
1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1951 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1950,9 +1954,9 @@ static struct clk mcspi2_ick = {
1950 1954
1951static struct clk mcspi2_fck = { 1955static struct clk mcspi2_fck = {
1952 .name = "mcspi_fck", 1956 .name = "mcspi_fck",
1957 .ops = &clkops_omap2_dflt_wait,
1953 .id = 2, 1958 .id = 2,
1954 .parent = &func_48m_ck, 1959 .parent = &func_48m_ck,
1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956 .clkdm_name = "core_l4_clkdm", 1960 .clkdm_name = "core_l4_clkdm",
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1958 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1962 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1961,9 +1965,9 @@ static struct clk mcspi2_fck = {
1961 1965
1962static struct clk mcspi3_ick = { 1966static struct clk mcspi3_ick = {
1963 .name = "mcspi_ick", 1967 .name = "mcspi_ick",
1968 .ops = &clkops_omap2_dflt_wait,
1964 .id = 3, 1969 .id = 3,
1965 .parent = &l4_ck, 1970 .parent = &l4_ck,
1966 .flags = CLOCK_IN_OMAP243X,
1967 .clkdm_name = "core_l4_clkdm", 1971 .clkdm_name = "core_l4_clkdm",
1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1969 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1973 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1972,9 +1976,9 @@ static struct clk mcspi3_ick = {
1972 1976
1973static struct clk mcspi3_fck = { 1977static struct clk mcspi3_fck = {
1974 .name = "mcspi_fck", 1978 .name = "mcspi_fck",
1979 .ops = &clkops_omap2_dflt_wait,
1975 .id = 3, 1980 .id = 3,
1976 .parent = &func_48m_ck, 1981 .parent = &func_48m_ck,
1977 .flags = CLOCK_IN_OMAP243X,
1978 .clkdm_name = "core_l4_clkdm", 1982 .clkdm_name = "core_l4_clkdm",
1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1983 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1980 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1984 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1983,8 +1987,8 @@ static struct clk mcspi3_fck = {
1983 1987
1984static struct clk uart1_ick = { 1988static struct clk uart1_ick = {
1985 .name = "uart1_ick", 1989 .name = "uart1_ick",
1990 .ops = &clkops_omap2_dflt_wait,
1986 .parent = &l4_ck, 1991 .parent = &l4_ck,
1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1988 .clkdm_name = "core_l4_clkdm", 1992 .clkdm_name = "core_l4_clkdm",
1989 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1993 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1990 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1994 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -1993,8 +1997,8 @@ static struct clk uart1_ick = {
1993 1997
1994static struct clk uart1_fck = { 1998static struct clk uart1_fck = {
1995 .name = "uart1_fck", 1999 .name = "uart1_fck",
2000 .ops = &clkops_omap2_dflt_wait,
1996 .parent = &func_48m_ck, 2001 .parent = &func_48m_ck,
1997 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1998 .clkdm_name = "core_l4_clkdm", 2002 .clkdm_name = "core_l4_clkdm",
1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2003 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2000 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 2004 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -2003,8 +2007,8 @@ static struct clk uart1_fck = {
2003 2007
2004static struct clk uart2_ick = { 2008static struct clk uart2_ick = {
2005 .name = "uart2_ick", 2009 .name = "uart2_ick",
2010 .ops = &clkops_omap2_dflt_wait,
2006 .parent = &l4_ck, 2011 .parent = &l4_ck,
2007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2008 .clkdm_name = "core_l4_clkdm", 2012 .clkdm_name = "core_l4_clkdm",
2009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2013 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2010 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2014 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2013,8 +2017,8 @@ static struct clk uart2_ick = {
2013 2017
2014static struct clk uart2_fck = { 2018static struct clk uart2_fck = {
2015 .name = "uart2_fck", 2019 .name = "uart2_fck",
2020 .ops = &clkops_omap2_dflt_wait,
2016 .parent = &func_48m_ck, 2021 .parent = &func_48m_ck,
2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018 .clkdm_name = "core_l4_clkdm", 2022 .clkdm_name = "core_l4_clkdm",
2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2023 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2020 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2024 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2023,8 +2027,8 @@ static struct clk uart2_fck = {
2023 2027
2024static struct clk uart3_ick = { 2028static struct clk uart3_ick = {
2025 .name = "uart3_ick", 2029 .name = "uart3_ick",
2030 .ops = &clkops_omap2_dflt_wait,
2026 .parent = &l4_ck, 2031 .parent = &l4_ck,
2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028 .clkdm_name = "core_l4_clkdm", 2032 .clkdm_name = "core_l4_clkdm",
2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2033 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2030 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2034 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2033,8 +2037,8 @@ static struct clk uart3_ick = {
2033 2037
2034static struct clk uart3_fck = { 2038static struct clk uart3_fck = {
2035 .name = "uart3_fck", 2039 .name = "uart3_fck",
2040 .ops = &clkops_omap2_dflt_wait,
2036 .parent = &func_48m_ck, 2041 .parent = &func_48m_ck,
2037 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038 .clkdm_name = "core_l4_clkdm", 2042 .clkdm_name = "core_l4_clkdm",
2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2043 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2040 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2044 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2043,8 +2047,8 @@ static struct clk uart3_fck = {
2043 2047
2044static struct clk gpios_ick = { 2048static struct clk gpios_ick = {
2045 .name = "gpios_ick", 2049 .name = "gpios_ick",
2050 .ops = &clkops_omap2_dflt_wait,
2046 .parent = &l4_ck, 2051 .parent = &l4_ck,
2047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2048 .clkdm_name = "core_l4_clkdm", 2052 .clkdm_name = "core_l4_clkdm",
2049 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2053 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2050 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2054 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2053,8 +2057,8 @@ static struct clk gpios_ick = {
2053 2057
2054static struct clk gpios_fck = { 2058static struct clk gpios_fck = {
2055 .name = "gpios_fck", 2059 .name = "gpios_fck",
2060 .ops = &clkops_omap2_dflt_wait,
2056 .parent = &func_32k_ck, 2061 .parent = &func_32k_ck,
2057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058 .clkdm_name = "wkup_clkdm", 2062 .clkdm_name = "wkup_clkdm",
2059 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2063 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2060 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2064 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2063,8 +2067,8 @@ static struct clk gpios_fck = {
2063 2067
2064static struct clk mpu_wdt_ick = { 2068static struct clk mpu_wdt_ick = {
2065 .name = "mpu_wdt_ick", 2069 .name = "mpu_wdt_ick",
2070 .ops = &clkops_omap2_dflt_wait,
2066 .parent = &l4_ck, 2071 .parent = &l4_ck,
2067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2068 .clkdm_name = "core_l4_clkdm", 2072 .clkdm_name = "core_l4_clkdm",
2069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2073 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2070 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2074 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2073,8 +2077,8 @@ static struct clk mpu_wdt_ick = {
2073 2077
2074static struct clk mpu_wdt_fck = { 2078static struct clk mpu_wdt_fck = {
2075 .name = "mpu_wdt_fck", 2079 .name = "mpu_wdt_fck",
2080 .ops = &clkops_omap2_dflt_wait,
2076 .parent = &func_32k_ck, 2081 .parent = &func_32k_ck,
2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078 .clkdm_name = "wkup_clkdm", 2082 .clkdm_name = "wkup_clkdm",
2079 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2083 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2080 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2084 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2083,9 +2087,9 @@ static struct clk mpu_wdt_fck = {
2083 2087
2084static struct clk sync_32k_ick = { 2088static struct clk sync_32k_ick = {
2085 .name = "sync_32k_ick", 2089 .name = "sync_32k_ick",
2090 .ops = &clkops_omap2_dflt_wait,
2086 .parent = &l4_ck, 2091 .parent = &l4_ck,
2087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2092 .flags = ENABLE_ON_INIT,
2088 ENABLE_ON_INIT,
2089 .clkdm_name = "core_l4_clkdm", 2093 .clkdm_name = "core_l4_clkdm",
2090 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2094 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2091 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 2095 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
@@ -2094,8 +2098,8 @@ static struct clk sync_32k_ick = {
2094 2098
2095static struct clk wdt1_ick = { 2099static struct clk wdt1_ick = {
2096 .name = "wdt1_ick", 2100 .name = "wdt1_ick",
2101 .ops = &clkops_omap2_dflt_wait,
2097 .parent = &l4_ck, 2102 .parent = &l4_ck,
2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099 .clkdm_name = "core_l4_clkdm", 2103 .clkdm_name = "core_l4_clkdm",
2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2104 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2101 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 2105 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
@@ -2104,9 +2108,9 @@ static struct clk wdt1_ick = {
2104 2108
2105static struct clk omapctrl_ick = { 2109static struct clk omapctrl_ick = {
2106 .name = "omapctrl_ick", 2110 .name = "omapctrl_ick",
2111 .ops = &clkops_omap2_dflt_wait,
2107 .parent = &l4_ck, 2112 .parent = &l4_ck,
2108 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2113 .flags = ENABLE_ON_INIT,
2109 ENABLE_ON_INIT,
2110 .clkdm_name = "core_l4_clkdm", 2114 .clkdm_name = "core_l4_clkdm",
2111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2115 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2112 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 2116 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
@@ -2115,8 +2119,8 @@ static struct clk omapctrl_ick = {
2115 2119
2116static struct clk icr_ick = { 2120static struct clk icr_ick = {
2117 .name = "icr_ick", 2121 .name = "icr_ick",
2122 .ops = &clkops_omap2_dflt_wait,
2118 .parent = &l4_ck, 2123 .parent = &l4_ck,
2119 .flags = CLOCK_IN_OMAP243X,
2120 .clkdm_name = "core_l4_clkdm", 2124 .clkdm_name = "core_l4_clkdm",
2121 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2125 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2122 .enable_bit = OMAP2430_EN_ICR_SHIFT, 2126 .enable_bit = OMAP2430_EN_ICR_SHIFT,
@@ -2125,8 +2129,8 @@ static struct clk icr_ick = {
2125 2129
2126static struct clk cam_ick = { 2130static struct clk cam_ick = {
2127 .name = "cam_ick", 2131 .name = "cam_ick",
2132 .ops = &clkops_omap2_dflt,
2128 .parent = &l4_ck, 2133 .parent = &l4_ck,
2129 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2130 .clkdm_name = "core_l4_clkdm", 2134 .clkdm_name = "core_l4_clkdm",
2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2132 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2136 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2140,8 +2144,8 @@ static struct clk cam_ick = {
2140 */ 2144 */
2141static struct clk cam_fck = { 2145static struct clk cam_fck = {
2142 .name = "cam_fck", 2146 .name = "cam_fck",
2147 .ops = &clkops_omap2_dflt,
2143 .parent = &func_96m_ck, 2148 .parent = &func_96m_ck,
2144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2145 .clkdm_name = "core_l3_clkdm", 2149 .clkdm_name = "core_l3_clkdm",
2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2150 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2151 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2150,8 +2154,8 @@ static struct clk cam_fck = {
2150 2154
2151static struct clk mailboxes_ick = { 2155static struct clk mailboxes_ick = {
2152 .name = "mailboxes_ick", 2156 .name = "mailboxes_ick",
2157 .ops = &clkops_omap2_dflt_wait,
2153 .parent = &l4_ck, 2158 .parent = &l4_ck,
2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155 .clkdm_name = "core_l4_clkdm", 2159 .clkdm_name = "core_l4_clkdm",
2156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2157 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 2161 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
@@ -2160,8 +2164,8 @@ static struct clk mailboxes_ick = {
2160 2164
2161static struct clk wdt4_ick = { 2165static struct clk wdt4_ick = {
2162 .name = "wdt4_ick", 2166 .name = "wdt4_ick",
2167 .ops = &clkops_omap2_dflt_wait,
2163 .parent = &l4_ck, 2168 .parent = &l4_ck,
2164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2165 .clkdm_name = "core_l4_clkdm", 2169 .clkdm_name = "core_l4_clkdm",
2166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2170 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2167 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2171 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2170,8 +2174,8 @@ static struct clk wdt4_ick = {
2170 2174
2171static struct clk wdt4_fck = { 2175static struct clk wdt4_fck = {
2172 .name = "wdt4_fck", 2176 .name = "wdt4_fck",
2177 .ops = &clkops_omap2_dflt_wait,
2173 .parent = &func_32k_ck, 2178 .parent = &func_32k_ck,
2174 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2175 .clkdm_name = "core_l4_clkdm", 2179 .clkdm_name = "core_l4_clkdm",
2176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2180 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2177 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2181 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2180,8 +2184,8 @@ static struct clk wdt4_fck = {
2180 2184
2181static struct clk wdt3_ick = { 2185static struct clk wdt3_ick = {
2182 .name = "wdt3_ick", 2186 .name = "wdt3_ick",
2187 .ops = &clkops_omap2_dflt_wait,
2183 .parent = &l4_ck, 2188 .parent = &l4_ck,
2184 .flags = CLOCK_IN_OMAP242X,
2185 .clkdm_name = "core_l4_clkdm", 2189 .clkdm_name = "core_l4_clkdm",
2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2187 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2191 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2190,8 +2194,8 @@ static struct clk wdt3_ick = {
2190 2194
2191static struct clk wdt3_fck = { 2195static struct clk wdt3_fck = {
2192 .name = "wdt3_fck", 2196 .name = "wdt3_fck",
2197 .ops = &clkops_omap2_dflt_wait,
2193 .parent = &func_32k_ck, 2198 .parent = &func_32k_ck,
2194 .flags = CLOCK_IN_OMAP242X,
2195 .clkdm_name = "core_l4_clkdm", 2199 .clkdm_name = "core_l4_clkdm",
2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2197 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2201 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2200,8 +2204,8 @@ static struct clk wdt3_fck = {
2200 2204
2201static struct clk mspro_ick = { 2205static struct clk mspro_ick = {
2202 .name = "mspro_ick", 2206 .name = "mspro_ick",
2207 .ops = &clkops_omap2_dflt_wait,
2203 .parent = &l4_ck, 2208 .parent = &l4_ck,
2204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2205 .clkdm_name = "core_l4_clkdm", 2209 .clkdm_name = "core_l4_clkdm",
2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2211 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2210,8 +2214,8 @@ static struct clk mspro_ick = {
2210 2214
2211static struct clk mspro_fck = { 2215static struct clk mspro_fck = {
2212 .name = "mspro_fck", 2216 .name = "mspro_fck",
2217 .ops = &clkops_omap2_dflt_wait,
2213 .parent = &func_96m_ck, 2218 .parent = &func_96m_ck,
2214 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215 .clkdm_name = "core_l4_clkdm", 2219 .clkdm_name = "core_l4_clkdm",
2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2217 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2221 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2220,8 +2224,8 @@ static struct clk mspro_fck = {
2220 2224
2221static struct clk mmc_ick = { 2225static struct clk mmc_ick = {
2222 .name = "mmc_ick", 2226 .name = "mmc_ick",
2227 .ops = &clkops_omap2_dflt_wait,
2223 .parent = &l4_ck, 2228 .parent = &l4_ck,
2224 .flags = CLOCK_IN_OMAP242X,
2225 .clkdm_name = "core_l4_clkdm", 2229 .clkdm_name = "core_l4_clkdm",
2226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2230 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2227 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2231 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2230,8 +2234,8 @@ static struct clk mmc_ick = {
2230 2234
2231static struct clk mmc_fck = { 2235static struct clk mmc_fck = {
2232 .name = "mmc_fck", 2236 .name = "mmc_fck",
2237 .ops = &clkops_omap2_dflt_wait,
2233 .parent = &func_96m_ck, 2238 .parent = &func_96m_ck,
2234 .flags = CLOCK_IN_OMAP242X,
2235 .clkdm_name = "core_l4_clkdm", 2239 .clkdm_name = "core_l4_clkdm",
2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2240 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2237 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2241 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2240,8 +2244,8 @@ static struct clk mmc_fck = {
2240 2244
2241static struct clk fac_ick = { 2245static struct clk fac_ick = {
2242 .name = "fac_ick", 2246 .name = "fac_ick",
2247 .ops = &clkops_omap2_dflt_wait,
2243 .parent = &l4_ck, 2248 .parent = &l4_ck,
2244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2245 .clkdm_name = "core_l4_clkdm", 2249 .clkdm_name = "core_l4_clkdm",
2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2250 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2247 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2251 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2250,8 +2254,8 @@ static struct clk fac_ick = {
2250 2254
2251static struct clk fac_fck = { 2255static struct clk fac_fck = {
2252 .name = "fac_fck", 2256 .name = "fac_fck",
2257 .ops = &clkops_omap2_dflt_wait,
2253 .parent = &func_12m_ck, 2258 .parent = &func_12m_ck,
2254 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2255 .clkdm_name = "core_l4_clkdm", 2259 .clkdm_name = "core_l4_clkdm",
2256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2257 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2261 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2260,8 +2264,8 @@ static struct clk fac_fck = {
2260 2264
2261static struct clk eac_ick = { 2265static struct clk eac_ick = {
2262 .name = "eac_ick", 2266 .name = "eac_ick",
2267 .ops = &clkops_omap2_dflt_wait,
2263 .parent = &l4_ck, 2268 .parent = &l4_ck,
2264 .flags = CLOCK_IN_OMAP242X,
2265 .clkdm_name = "core_l4_clkdm", 2269 .clkdm_name = "core_l4_clkdm",
2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2270 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2267 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2271 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2270,8 +2274,8 @@ static struct clk eac_ick = {
2270 2274
2271static struct clk eac_fck = { 2275static struct clk eac_fck = {
2272 .name = "eac_fck", 2276 .name = "eac_fck",
2277 .ops = &clkops_omap2_dflt_wait,
2273 .parent = &func_96m_ck, 2278 .parent = &func_96m_ck,
2274 .flags = CLOCK_IN_OMAP242X,
2275 .clkdm_name = "core_l4_clkdm", 2279 .clkdm_name = "core_l4_clkdm",
2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2281 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2280,8 +2284,8 @@ static struct clk eac_fck = {
2280 2284
2281static struct clk hdq_ick = { 2285static struct clk hdq_ick = {
2282 .name = "hdq_ick", 2286 .name = "hdq_ick",
2287 .ops = &clkops_omap2_dflt_wait,
2283 .parent = &l4_ck, 2288 .parent = &l4_ck,
2284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2285 .clkdm_name = "core_l4_clkdm", 2289 .clkdm_name = "core_l4_clkdm",
2286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2290 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2287 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2291 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2290,8 +2294,8 @@ static struct clk hdq_ick = {
2290 2294
2291static struct clk hdq_fck = { 2295static struct clk hdq_fck = {
2292 .name = "hdq_fck", 2296 .name = "hdq_fck",
2297 .ops = &clkops_omap2_dflt_wait,
2293 .parent = &func_12m_ck, 2298 .parent = &func_12m_ck,
2294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2295 .clkdm_name = "core_l4_clkdm", 2299 .clkdm_name = "core_l4_clkdm",
2296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2300 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2297 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2301 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2300,9 +2304,9 @@ static struct clk hdq_fck = {
2300 2304
2301static struct clk i2c2_ick = { 2305static struct clk i2c2_ick = {
2302 .name = "i2c_ick", 2306 .name = "i2c_ick",
2307 .ops = &clkops_omap2_dflt_wait,
2303 .id = 2, 2308 .id = 2,
2304 .parent = &l4_ck, 2309 .parent = &l4_ck,
2305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2306 .clkdm_name = "core_l4_clkdm", 2310 .clkdm_name = "core_l4_clkdm",
2307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2308 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2312 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2311,9 +2315,9 @@ static struct clk i2c2_ick = {
2311 2315
2312static struct clk i2c2_fck = { 2316static struct clk i2c2_fck = {
2313 .name = "i2c_fck", 2317 .name = "i2c_fck",
2318 .ops = &clkops_omap2_dflt_wait,
2314 .id = 2, 2319 .id = 2,
2315 .parent = &func_12m_ck, 2320 .parent = &func_12m_ck,
2316 .flags = CLOCK_IN_OMAP242X,
2317 .clkdm_name = "core_l4_clkdm", 2321 .clkdm_name = "core_l4_clkdm",
2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2319 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2323 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2322,9 +2326,9 @@ static struct clk i2c2_fck = {
2322 2326
2323static struct clk i2chs2_fck = { 2327static struct clk i2chs2_fck = {
2324 .name = "i2c_fck", 2328 .name = "i2c_fck",
2329 .ops = &clkops_omap2_dflt_wait,
2325 .id = 2, 2330 .id = 2,
2326 .parent = &func_96m_ck, 2331 .parent = &func_96m_ck,
2327 .flags = CLOCK_IN_OMAP243X,
2328 .clkdm_name = "core_l4_clkdm", 2332 .clkdm_name = "core_l4_clkdm",
2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2333 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2330 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, 2334 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
@@ -2333,9 +2337,9 @@ static struct clk i2chs2_fck = {
2333 2337
2334static struct clk i2c1_ick = { 2338static struct clk i2c1_ick = {
2335 .name = "i2c_ick", 2339 .name = "i2c_ick",
2340 .ops = &clkops_omap2_dflt_wait,
2336 .id = 1, 2341 .id = 1,
2337 .parent = &l4_ck, 2342 .parent = &l4_ck,
2338 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2339 .clkdm_name = "core_l4_clkdm", 2343 .clkdm_name = "core_l4_clkdm",
2340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2341 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2345 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2344,9 +2348,9 @@ static struct clk i2c1_ick = {
2344 2348
2345static struct clk i2c1_fck = { 2349static struct clk i2c1_fck = {
2346 .name = "i2c_fck", 2350 .name = "i2c_fck",
2351 .ops = &clkops_omap2_dflt_wait,
2347 .id = 1, 2352 .id = 1,
2348 .parent = &func_12m_ck, 2353 .parent = &func_12m_ck,
2349 .flags = CLOCK_IN_OMAP242X,
2350 .clkdm_name = "core_l4_clkdm", 2354 .clkdm_name = "core_l4_clkdm",
2351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2355 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2352 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2356 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2355,9 +2359,9 @@ static struct clk i2c1_fck = {
2355 2359
2356static struct clk i2chs1_fck = { 2360static struct clk i2chs1_fck = {
2357 .name = "i2c_fck", 2361 .name = "i2c_fck",
2362 .ops = &clkops_omap2_dflt_wait,
2358 .id = 1, 2363 .id = 1,
2359 .parent = &func_96m_ck, 2364 .parent = &func_96m_ck,
2360 .flags = CLOCK_IN_OMAP243X,
2361 .clkdm_name = "core_l4_clkdm", 2365 .clkdm_name = "core_l4_clkdm",
2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2363 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, 2367 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
@@ -2366,33 +2370,33 @@ static struct clk i2chs1_fck = {
2366 2370
2367static struct clk gpmc_fck = { 2371static struct clk gpmc_fck = {
2368 .name = "gpmc_fck", 2372 .name = "gpmc_fck",
2373 .ops = &clkops_null, /* RMK: missing? */
2369 .parent = &core_l3_ck, 2374 .parent = &core_l3_ck,
2370 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2375 .flags = ENABLE_ON_INIT,
2371 ENABLE_ON_INIT,
2372 .clkdm_name = "core_l3_clkdm", 2376 .clkdm_name = "core_l3_clkdm",
2373 .recalc = &followparent_recalc, 2377 .recalc = &followparent_recalc,
2374}; 2378};
2375 2379
2376static struct clk sdma_fck = { 2380static struct clk sdma_fck = {
2377 .name = "sdma_fck", 2381 .name = "sdma_fck",
2382 .ops = &clkops_null, /* RMK: missing? */
2378 .parent = &core_l3_ck, 2383 .parent = &core_l3_ck,
2379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2380 .clkdm_name = "core_l3_clkdm", 2384 .clkdm_name = "core_l3_clkdm",
2381 .recalc = &followparent_recalc, 2385 .recalc = &followparent_recalc,
2382}; 2386};
2383 2387
2384static struct clk sdma_ick = { 2388static struct clk sdma_ick = {
2385 .name = "sdma_ick", 2389 .name = "sdma_ick",
2390 .ops = &clkops_null, /* RMK: missing? */
2386 .parent = &l4_ck, 2391 .parent = &l4_ck,
2387 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2388 .clkdm_name = "core_l3_clkdm", 2392 .clkdm_name = "core_l3_clkdm",
2389 .recalc = &followparent_recalc, 2393 .recalc = &followparent_recalc,
2390}; 2394};
2391 2395
2392static struct clk vlynq_ick = { 2396static struct clk vlynq_ick = {
2393 .name = "vlynq_ick", 2397 .name = "vlynq_ick",
2398 .ops = &clkops_omap2_dflt_wait,
2394 .parent = &core_l3_ck, 2399 .parent = &core_l3_ck,
2395 .flags = CLOCK_IN_OMAP242X,
2396 .clkdm_name = "core_l3_clkdm", 2400 .clkdm_name = "core_l3_clkdm",
2397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2401 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2398 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2402 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2426,8 +2430,9 @@ static const struct clksel vlynq_fck_clksel[] = {
2426 2430
2427static struct clk vlynq_fck = { 2431static struct clk vlynq_fck = {
2428 .name = "vlynq_fck", 2432 .name = "vlynq_fck",
2433 .ops = &clkops_omap2_dflt_wait,
2429 .parent = &func_96m_ck, 2434 .parent = &func_96m_ck,
2430 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2435 .flags = DELAYED_APP,
2431 .clkdm_name = "core_l3_clkdm", 2436 .clkdm_name = "core_l3_clkdm",
2432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2433 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2438 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2442,8 +2447,9 @@ static struct clk vlynq_fck = {
2442 2447
2443static struct clk sdrc_ick = { 2448static struct clk sdrc_ick = {
2444 .name = "sdrc_ick", 2449 .name = "sdrc_ick",
2450 .ops = &clkops_omap2_dflt_wait,
2445 .parent = &l4_ck, 2451 .parent = &l4_ck,
2446 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2452 .flags = ENABLE_ON_INIT,
2447 .clkdm_name = "core_l4_clkdm", 2453 .clkdm_name = "core_l4_clkdm",
2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 2454 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2449 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 2455 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
@@ -2452,8 +2458,8 @@ static struct clk sdrc_ick = {
2452 2458
2453static struct clk des_ick = { 2459static struct clk des_ick = {
2454 .name = "des_ick", 2460 .name = "des_ick",
2461 .ops = &clkops_omap2_dflt_wait,
2455 .parent = &l4_ck, 2462 .parent = &l4_ck,
2456 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2457 .clkdm_name = "core_l4_clkdm", 2463 .clkdm_name = "core_l4_clkdm",
2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2464 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2459 .enable_bit = OMAP24XX_EN_DES_SHIFT, 2465 .enable_bit = OMAP24XX_EN_DES_SHIFT,
@@ -2462,8 +2468,8 @@ static struct clk des_ick = {
2462 2468
2463static struct clk sha_ick = { 2469static struct clk sha_ick = {
2464 .name = "sha_ick", 2470 .name = "sha_ick",
2471 .ops = &clkops_omap2_dflt_wait,
2465 .parent = &l4_ck, 2472 .parent = &l4_ck,
2466 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2467 .clkdm_name = "core_l4_clkdm", 2473 .clkdm_name = "core_l4_clkdm",
2468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2469 .enable_bit = OMAP24XX_EN_SHA_SHIFT, 2475 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
@@ -2472,8 +2478,8 @@ static struct clk sha_ick = {
2472 2478
2473static struct clk rng_ick = { 2479static struct clk rng_ick = {
2474 .name = "rng_ick", 2480 .name = "rng_ick",
2481 .ops = &clkops_omap2_dflt_wait,
2475 .parent = &l4_ck, 2482 .parent = &l4_ck,
2476 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2477 .clkdm_name = "core_l4_clkdm", 2483 .clkdm_name = "core_l4_clkdm",
2478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2479 .enable_bit = OMAP24XX_EN_RNG_SHIFT, 2485 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
@@ -2482,8 +2488,8 @@ static struct clk rng_ick = {
2482 2488
2483static struct clk aes_ick = { 2489static struct clk aes_ick = {
2484 .name = "aes_ick", 2490 .name = "aes_ick",
2491 .ops = &clkops_omap2_dflt_wait,
2485 .parent = &l4_ck, 2492 .parent = &l4_ck,
2486 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2487 .clkdm_name = "core_l4_clkdm", 2493 .clkdm_name = "core_l4_clkdm",
2488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2489 .enable_bit = OMAP24XX_EN_AES_SHIFT, 2495 .enable_bit = OMAP24XX_EN_AES_SHIFT,
@@ -2492,8 +2498,8 @@ static struct clk aes_ick = {
2492 2498
2493static struct clk pka_ick = { 2499static struct clk pka_ick = {
2494 .name = "pka_ick", 2500 .name = "pka_ick",
2501 .ops = &clkops_omap2_dflt_wait,
2495 .parent = &l4_ck, 2502 .parent = &l4_ck,
2496 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2497 .clkdm_name = "core_l4_clkdm", 2503 .clkdm_name = "core_l4_clkdm",
2498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2504 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2499 .enable_bit = OMAP24XX_EN_PKA_SHIFT, 2505 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
@@ -2502,8 +2508,8 @@ static struct clk pka_ick = {
2502 2508
2503static struct clk usb_fck = { 2509static struct clk usb_fck = {
2504 .name = "usb_fck", 2510 .name = "usb_fck",
2511 .ops = &clkops_omap2_dflt_wait,
2505 .parent = &func_48m_ck, 2512 .parent = &func_48m_ck,
2506 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2507 .clkdm_name = "core_l3_clkdm", 2513 .clkdm_name = "core_l3_clkdm",
2508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2509 .enable_bit = OMAP24XX_EN_USB_SHIFT, 2515 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -2512,8 +2518,8 @@ static struct clk usb_fck = {
2512 2518
2513static struct clk usbhs_ick = { 2519static struct clk usbhs_ick = {
2514 .name = "usbhs_ick", 2520 .name = "usbhs_ick",
2521 .ops = &clkops_omap2_dflt_wait,
2515 .parent = &core_l3_ck, 2522 .parent = &core_l3_ck,
2516 .flags = CLOCK_IN_OMAP243X,
2517 .clkdm_name = "core_l3_clkdm", 2523 .clkdm_name = "core_l3_clkdm",
2518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2524 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2519 .enable_bit = OMAP2430_EN_USBHS_SHIFT, 2525 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
@@ -2522,8 +2528,8 @@ static struct clk usbhs_ick = {
2522 2528
2523static struct clk mmchs1_ick = { 2529static struct clk mmchs1_ick = {
2524 .name = "mmchs_ick", 2530 .name = "mmchs_ick",
2531 .ops = &clkops_omap2_dflt_wait,
2525 .parent = &l4_ck, 2532 .parent = &l4_ck,
2526 .flags = CLOCK_IN_OMAP243X,
2527 .clkdm_name = "core_l4_clkdm", 2533 .clkdm_name = "core_l4_clkdm",
2528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2529 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2535 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2532,8 +2538,8 @@ static struct clk mmchs1_ick = {
2532 2538
2533static struct clk mmchs1_fck = { 2539static struct clk mmchs1_fck = {
2534 .name = "mmchs_fck", 2540 .name = "mmchs_fck",
2541 .ops = &clkops_omap2_dflt_wait,
2535 .parent = &func_96m_ck, 2542 .parent = &func_96m_ck,
2536 .flags = CLOCK_IN_OMAP243X,
2537 .clkdm_name = "core_l3_clkdm", 2543 .clkdm_name = "core_l3_clkdm",
2538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2544 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2539 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2545 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2542,9 +2548,9 @@ static struct clk mmchs1_fck = {
2542 2548
2543static struct clk mmchs2_ick = { 2549static struct clk mmchs2_ick = {
2544 .name = "mmchs_ick", 2550 .name = "mmchs_ick",
2551 .ops = &clkops_omap2_dflt_wait,
2545 .id = 1, 2552 .id = 1,
2546 .parent = &l4_ck, 2553 .parent = &l4_ck,
2547 .flags = CLOCK_IN_OMAP243X,
2548 .clkdm_name = "core_l4_clkdm", 2554 .clkdm_name = "core_l4_clkdm",
2549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2550 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2556 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2553,9 +2559,9 @@ static struct clk mmchs2_ick = {
2553 2559
2554static struct clk mmchs2_fck = { 2560static struct clk mmchs2_fck = {
2555 .name = "mmchs_fck", 2561 .name = "mmchs_fck",
2562 .ops = &clkops_omap2_dflt_wait,
2556 .id = 1, 2563 .id = 1,
2557 .parent = &func_96m_ck, 2564 .parent = &func_96m_ck,
2558 .flags = CLOCK_IN_OMAP243X,
2559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2560 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2566 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2561 .recalc = &followparent_recalc, 2567 .recalc = &followparent_recalc,
@@ -2563,8 +2569,8 @@ static struct clk mmchs2_fck = {
2563 2569
2564static struct clk gpio5_ick = { 2570static struct clk gpio5_ick = {
2565 .name = "gpio5_ick", 2571 .name = "gpio5_ick",
2572 .ops = &clkops_omap2_dflt_wait,
2566 .parent = &l4_ck, 2573 .parent = &l4_ck,
2567 .flags = CLOCK_IN_OMAP243X,
2568 .clkdm_name = "core_l4_clkdm", 2574 .clkdm_name = "core_l4_clkdm",
2569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2575 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2576 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2573,8 +2579,8 @@ static struct clk gpio5_ick = {
2573 2579
2574static struct clk gpio5_fck = { 2580static struct clk gpio5_fck = {
2575 .name = "gpio5_fck", 2581 .name = "gpio5_fck",
2582 .ops = &clkops_omap2_dflt_wait,
2576 .parent = &func_32k_ck, 2583 .parent = &func_32k_ck,
2577 .flags = CLOCK_IN_OMAP243X,
2578 .clkdm_name = "core_l4_clkdm", 2584 .clkdm_name = "core_l4_clkdm",
2579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2580 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2586 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2583,8 +2589,8 @@ static struct clk gpio5_fck = {
2583 2589
2584static struct clk mdm_intc_ick = { 2590static struct clk mdm_intc_ick = {
2585 .name = "mdm_intc_ick", 2591 .name = "mdm_intc_ick",
2592 .ops = &clkops_omap2_dflt_wait,
2586 .parent = &l4_ck, 2593 .parent = &l4_ck,
2587 .flags = CLOCK_IN_OMAP243X,
2588 .clkdm_name = "core_l4_clkdm", 2594 .clkdm_name = "core_l4_clkdm",
2589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2595 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2590 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, 2596 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
@@ -2593,8 +2599,8 @@ static struct clk mdm_intc_ick = {
2593 2599
2594static struct clk mmchsdb1_fck = { 2600static struct clk mmchsdb1_fck = {
2595 .name = "mmchsdb_fck", 2601 .name = "mmchsdb_fck",
2602 .ops = &clkops_omap2_dflt_wait,
2596 .parent = &func_32k_ck, 2603 .parent = &func_32k_ck,
2597 .flags = CLOCK_IN_OMAP243X,
2598 .clkdm_name = "core_l4_clkdm", 2604 .clkdm_name = "core_l4_clkdm",
2599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2605 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2600 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, 2606 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
@@ -2603,9 +2609,9 @@ static struct clk mmchsdb1_fck = {
2603 2609
2604static struct clk mmchsdb2_fck = { 2610static struct clk mmchsdb2_fck = {
2605 .name = "mmchsdb_fck", 2611 .name = "mmchsdb_fck",
2612 .ops = &clkops_omap2_dflt_wait,
2606 .id = 1, 2613 .id = 1,
2607 .parent = &func_32k_ck, 2614 .parent = &func_32k_ck,
2608 .flags = CLOCK_IN_OMAP243X,
2609 .clkdm_name = "core_l4_clkdm", 2615 .clkdm_name = "core_l4_clkdm",
2610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2611 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, 2617 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
@@ -2628,166 +2634,13 @@ static struct clk mmchsdb2_fck = {
2628 */ 2634 */
2629static struct clk virt_prcm_set = { 2635static struct clk virt_prcm_set = {
2630 .name = "virt_prcm_set", 2636 .name = "virt_prcm_set",
2631 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2637 .ops = &clkops_null,
2632 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, 2638 .flags = DELAYED_APP,
2633 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ 2639 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2634 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ 2640 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2635 .set_rate = &omap2_select_table_rate, 2641 .set_rate = &omap2_select_table_rate,
2636 .round_rate = &omap2_round_to_table_rate, 2642 .round_rate = &omap2_round_to_table_rate,
2637}; 2643};
2638 2644
2639static struct clk *onchip_24xx_clks[] __initdata = {
2640 /* external root sources */
2641 &func_32k_ck,
2642 &osc_ck,
2643 &sys_ck,
2644 &alt_ck,
2645 /* internal analog sources */
2646 &dpll_ck,
2647 &apll96_ck,
2648 &apll54_ck,
2649 /* internal prcm root sources */
2650 &func_54m_ck,
2651 &core_ck,
2652 &func_96m_ck,
2653 &func_48m_ck,
2654 &func_12m_ck,
2655 &wdt1_osc_ck,
2656 &sys_clkout_src,
2657 &sys_clkout,
2658 &sys_clkout2_src,
2659 &sys_clkout2,
2660 &emul_ck,
2661 /* mpu domain clocks */
2662 &mpu_ck,
2663 /* dsp domain clocks */
2664 &dsp_fck,
2665 &dsp_irate_ick,
2666 &dsp_ick, /* 242x */
2667 &iva2_1_ick, /* 243x */
2668 &iva1_ifck, /* 242x */
2669 &iva1_mpu_int_ifck, /* 242x */
2670 /* GFX domain clocks */
2671 &gfx_3d_fck,
2672 &gfx_2d_fck,
2673 &gfx_ick,
2674 /* Modem domain clocks */
2675 &mdm_ick,
2676 &mdm_osc_ck,
2677 /* DSS domain clocks */
2678 &dss_ick,
2679 &dss1_fck,
2680 &dss2_fck,
2681 &dss_54m_fck,
2682 /* L3 domain clocks */
2683 &core_l3_ck,
2684 &ssi_ssr_sst_fck,
2685 &usb_l4_ick,
2686 /* L4 domain clocks */
2687 &l4_ck, /* used as both core_l4 and wu_l4 */
2688 /* virtual meta-group clock */
2689 &virt_prcm_set,
2690 /* general l4 interface ck, multi-parent functional clk */
2691 &gpt1_ick,
2692 &gpt1_fck,
2693 &gpt2_ick,
2694 &gpt2_fck,
2695 &gpt3_ick,
2696 &gpt3_fck,
2697 &gpt4_ick,
2698 &gpt4_fck,
2699 &gpt5_ick,
2700 &gpt5_fck,
2701 &gpt6_ick,
2702 &gpt6_fck,
2703 &gpt7_ick,
2704 &gpt7_fck,
2705 &gpt8_ick,
2706 &gpt8_fck,
2707 &gpt9_ick,
2708 &gpt9_fck,
2709 &gpt10_ick,
2710 &gpt10_fck,
2711 &gpt11_ick,
2712 &gpt11_fck,
2713 &gpt12_ick,
2714 &gpt12_fck,
2715 &mcbsp1_ick,
2716 &mcbsp1_fck,
2717 &mcbsp2_ick,
2718 &mcbsp2_fck,
2719 &mcbsp3_ick,
2720 &mcbsp3_fck,
2721 &mcbsp4_ick,
2722 &mcbsp4_fck,
2723 &mcbsp5_ick,
2724 &mcbsp5_fck,
2725 &mcspi1_ick,
2726 &mcspi1_fck,
2727 &mcspi2_ick,
2728 &mcspi2_fck,
2729 &mcspi3_ick,
2730 &mcspi3_fck,
2731 &uart1_ick,
2732 &uart1_fck,
2733 &uart2_ick,
2734 &uart2_fck,
2735 &uart3_ick,
2736 &uart3_fck,
2737 &gpios_ick,
2738 &gpios_fck,
2739 &mpu_wdt_ick,
2740 &mpu_wdt_fck,
2741 &sync_32k_ick,
2742 &wdt1_ick,
2743 &omapctrl_ick,
2744 &icr_ick,
2745 &cam_fck,
2746 &cam_ick,
2747 &mailboxes_ick,
2748 &wdt4_ick,
2749 &wdt4_fck,
2750 &wdt3_ick,
2751 &wdt3_fck,
2752 &mspro_ick,
2753 &mspro_fck,
2754 &mmc_ick,
2755 &mmc_fck,
2756 &fac_ick,
2757 &fac_fck,
2758 &eac_ick,
2759 &eac_fck,
2760 &hdq_ick,
2761 &hdq_fck,
2762 &i2c1_ick,
2763 &i2c1_fck,
2764 &i2chs1_fck,
2765 &i2c2_ick,
2766 &i2c2_fck,
2767 &i2chs2_fck,
2768 &gpmc_fck,
2769 &sdma_fck,
2770 &sdma_ick,
2771 &vlynq_ick,
2772 &vlynq_fck,
2773 &sdrc_ick,
2774 &des_ick,
2775 &sha_ick,
2776 &rng_ick,
2777 &aes_ick,
2778 &pka_ick,
2779 &usb_fck,
2780 &usbhs_ick,
2781 &mmchs1_ick,
2782 &mmchs1_fck,
2783 &mmchs2_ick,
2784 &mmchs2_fck,
2785 &gpio5_ick,
2786 &gpio5_fck,
2787 &mdm_intc_ick,
2788 &mmchsdb1_fck,
2789 &mmchsdb2_fck,
2790};
2791
2792#endif 2645#endif
2793 2646
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 02:39:08 -0500